2 * Device Tree Include file for Marvell Armada 370 family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
48 * Contains definitions specific to the Armada 370 SoC that are not
49 * common to all Armada SoCs.
52 #include "armada-370-xp.dtsi"
58 model = "Marvell Armada 370 family SoC";
59 compatible = "marvell,armada370", "marvell,armada-370-xp";
68 compatible = "marvell,armada370-mbus", "simple-bus";
71 compatible = "marvell,bootrom";
72 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
75 pciec: pcie-controller@82000000 {
76 compatible = "marvell,armada-370-pcie";
84 bus-range = <0x00 0xff>;
87 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
88 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
89 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
90 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
91 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
92 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
96 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
97 reg = <0x0800 0 0 0 0>;
100 #interrupt-cells = <1>;
101 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
102 0x81000000 0 0 0x81000000 0x1 0 1 0>;
103 interrupt-map-mask = <0 0 0 0>;
104 interrupt-map = <0 0 0 0 &mpic 58>;
105 marvell,pcie-port = <0>;
106 marvell,pcie-lane = <0>;
107 clocks = <&gateclk 5>;
113 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
114 reg = <0x1000 0 0 0 0>;
115 #address-cells = <3>;
117 #interrupt-cells = <1>;
118 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
119 0x81000000 0 0 0x81000000 0x2 0 1 0>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &mpic 62>;
122 marvell,pcie-port = <1>;
123 marvell,pcie-lane = <0>;
124 clocks = <&gateclk 9>;
131 compatible = "marvell,aurora-outer-cache";
132 reg = <0x08000 0x1000>;
133 cache-id-part = <0x100>;
140 compatible = "marvell,armada-370-gpio",
141 "marvell,orion-gpio";
142 reg = <0x18100 0x40>, <0x181c0 0x08>;
143 reg-names = "gpio", "pwm";
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 interrupts = <82>, <83>, <84>, <85>;
151 clocks = <&coreclk 0>;
155 compatible = "marvell,armada-370-gpio",
156 "marvell,orion-gpio";
157 reg = <0x18140 0x40>, <0x181c8 0x08>;
158 reg-names = "gpio", "pwm";
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 interrupts = <87>, <88>, <89>, <90>;
166 clocks = <&coreclk 0>;
170 compatible = "marvell,armada-370-gpio",
171 "marvell,orion-gpio";
172 reg = <0x18180 0x40>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
182 systemc: system-controller@18200 {
183 compatible = "marvell,armada-370-xp-system-controller";
184 reg = <0x18200 0x100>;
187 gateclk: clock-gating-control@18220 {
188 compatible = "marvell,armada-370-gating-clock";
190 clocks = <&coreclk 0>;
194 coreclk: mvebu-sar@18230 {
195 compatible = "marvell,armada-370-core-clock";
196 reg = <0x18230 0x08>;
200 thermal: thermal@18300 {
201 compatible = "marvell,armada370-thermal";
211 cpuconf: cpu-config@21000 {
212 compatible = "marvell,armada-370-cpu-config";
216 audio_controller: audio-controller@30000 {
217 #sound-dai-cells = <1>;
218 compatible = "marvell,armada370-audio";
219 reg = <0x30000 0x4000>;
221 clocks = <&gateclk 0>;
222 clock-names = "internal";
227 compatible = "marvell,orion-xor";
246 compatible = "marvell,orion-xor";
265 compatible = "marvell,armada-370-crypto";
266 reg = <0x90000 0x10000>;
269 clocks = <&gateclk 23>;
270 clock-names = "cesa0";
271 marvell,crypto-srams = <&crypto_sram>;
272 marvell,crypto-sram-size = <0x7e0>;
276 crypto_sram: sa-sram {
277 compatible = "mmio-sram";
278 reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
280 clocks = <&gateclk 23>;
281 #address-cells = <1>;
283 ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
286 * The Armada 370 has an erratum preventing the use of
287 * the standard workflow for CPU idle support (relying
288 * on the BootROM code to enter/exit idle state).
289 * Reserve some amount of the crypto SRAM to put the
290 * cpuidle workaround.
300 * Default UART pinctrl setting without RTS/CTS, can be overwritten on
301 * board level if a different configuration is used.
305 pinctrl-0 = <&uart0_pins>;
306 pinctrl-names = "default";
310 pinctrl-0 = <&uart1_pins>;
311 pinctrl-names = "default";
315 reg = <0x11000 0x20>;
319 reg = <0x11100 0x20>;
323 reg = <0x20a00 0x1d0>, <0x21870 0x58>;
327 compatible = "marvell,armada-370-timer";
328 clocks = <&coreclk 2>;
332 compatible = "marvell,armada-370-wdt";
333 clocks = <&coreclk 2>;
337 clocks = <&coreclk 0>;
341 clocks = <&coreclk 0>;
345 compatible = "marvell,armada-370-neta";
349 compatible = "marvell,armada-370-neta";
353 compatible = "marvell,mv88f6710-pinctrl";
355 spi0_pins1: spi0-pins1 {
356 marvell,pins = "mpp33", "mpp34",
358 marvell,function = "spi0";
361 spi0_pins2: spi0_pins2 {
362 marvell,pins = "mpp32", "mpp63",
364 marvell,function = "spi0";
367 spi1_pins: spi1-pins {
368 marvell,pins = "mpp49", "mpp50",
370 marvell,function = "spi1";
373 uart0_pins: uart0-pins {
374 marvell,pins = "mpp0", "mpp1";
375 marvell,function = "uart0";
378 uart1_pins: uart1-pins {
379 marvell,pins = "mpp41", "mpp42";
380 marvell,function = "uart1";
383 sdio_pins1: sdio-pins1 {
384 marvell,pins = "mpp9", "mpp11", "mpp12",
385 "mpp13", "mpp14", "mpp15";
386 marvell,function = "sd0";
389 sdio_pins2: sdio-pins2 {
390 marvell,pins = "mpp47", "mpp48", "mpp49",
391 "mpp50", "mpp51", "mpp52";
392 marvell,function = "sd0";
395 sdio_pins3: sdio-pins3 {
396 marvell,pins = "mpp48", "mpp49", "mpp50",
397 "mpp51", "mpp52", "mpp53";
398 marvell,function = "sd0";
401 i2c0_pins: i2c0-pins {
402 marvell,pins = "mpp2", "mpp3";
403 marvell,function = "i2c0";
406 i2s_pins1: i2s-pins1 {
407 marvell,pins = "mpp5", "mpp6", "mpp7",
408 "mpp8", "mpp9", "mpp10",
410 marvell,function = "audio";
413 i2s_pins2: i2s-pins2 {
414 marvell,pins = "mpp49", "mpp47", "mpp50",
415 "mpp59", "mpp57", "mpp61",
416 "mpp62", "mpp60", "mpp58";
417 marvell,function = "audio";
420 mdio_pins: mdio-pins {
421 marvell,pins = "mpp17", "mpp18";
422 marvell,function = "ge";
425 ge0_rgmii_pins: ge0-rgmii-pins {
426 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
427 "mpp9", "mpp10", "mpp11", "mpp12",
428 "mpp13", "mpp14", "mpp15", "mpp16";
429 marvell,function = "ge0";
432 ge1_rgmii_pins: ge1-rgmii-pins {
433 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
434 "mpp23", "mpp24", "mpp25", "mpp26",
435 "mpp27", "mpp28", "mpp29", "mpp30";
436 marvell,function = "ge1";
441 * Default SPI pinctrl setting, can be overwritten on
442 * board level if a different configuration is used.
445 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
446 pinctrl-0 = <&spi0_pins1>;
447 pinctrl-names = "default";
451 compatible = "marvell,armada-370-spi", "marvell,orion-spi";
452 pinctrl-0 = <&spi1_pins>;
453 pinctrl-names = "default";