2 * Device Tree Include file for Marvell 98dx3236 family SoC
4 * Copyright (C) 2016 Allied Telesis Labs
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
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19 * GNU General Public License for more details.
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44 * Contains definitions specific to the 98dx3236 SoC that are not
45 * common to all Armada XP SoCs.
48 #include "armada-370-xp.dtsi"
54 model = "Marvell 98DX3236 SoC";
55 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
66 enable-method = "marvell,98dx3236-smp";
70 compatible = "marvell,sheeva-v7";
73 clock-latency = <1000000>;
78 compatible = "marvell,armadaxp-mbus", "simple-bus";
80 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
81 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
82 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
83 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
84 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
87 compatible = "marvell,bootrom";
88 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
92 * 98DX3236 has 1 x1 PCIe unit Gen2.0
94 pciec: pcie-controller@82000000 {
95 compatible = "marvell,armada-xp-pcie";
102 msi-parent = <&mpic>;
103 bus-range = <0x00 0xff>;
106 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
107 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
108 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
112 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
113 reg = <0x0800 0 0 0 0>;
114 #address-cells = <3>;
116 #interrupt-cells = <1>;
117 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
118 0x81000000 0 0 0x81000000 0x1 0 1 0>;
119 interrupt-map-mask = <0 0 0 0>;
120 interrupt-map = <0 0 0 0 &mpic 58>;
121 marvell,pcie-port = <0>;
122 marvell,pcie-lane = <0>;
123 clocks = <&gateclk 5>;
130 compatible = "marvell,armada-xp-sdram-controller";
131 reg = <0x1400 0x500>;
135 compatible = "marvell,aurora-system-cache";
136 reg = <0x08000 0x1000>;
137 cache-id-part = <0x100>;
144 compatible = "marvell,orion-gpio";
145 reg = <0x18100 0x40>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 interrupts = <82>, <83>, <84>, <85>;
156 compatible = "marvell,orion-gpio";
157 reg = <0x18140 0x40>;
161 gpio2: gpio@18180 { /* rework some properties */
162 compatible = "marvell,orion-gpio";
163 reg = <0x18180 0x40>;
164 ngpios = <1>; /* only gpio #32 */
167 interrupt-controller;
168 #interrupt-cells = <2>;
172 systemc: system-controller@18200 {
173 compatible = "marvell,armada-370-xp-system-controller";
174 reg = <0x18200 0x500>;
177 gateclk: clock-gating-control@18220 {
178 compatible = "marvell,mv98dx3236-gating-clock";
180 clocks = <&coreclk 0>;
184 cpuclk: clock-complex@18700 {
186 compatible = "marvell,mv98dx3236-cpu-clock";
187 reg = <0x18700 0x24>, <0x1c054 0x10>;
188 clocks = <&coreclk 1>;
191 corediv-clock@18740 {
196 compatible = "marvell,armada-xp-cpu-config";
201 compatible = "marvell,armada-xp-neta";
205 compatible = "marvell,armada-xp-neta";
209 compatible = "marvell,orion-xor";
212 clocks = <&gateclk 22>;
229 clocks = <&dfx_coredivclk 0>;
233 compatible = "marvell,orion-xor";
236 clocks = <&gateclk 28>;
253 dfx: dfx-server@ac000000 {
254 compatible = "marvell,dfx-server", "simple-bus";
255 #address-cells = <1>;
257 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
258 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
260 coreclk: mvebu-sar@f8204 {
261 compatible = "marvell,mv98dx3236-core-clock";
266 dfx_coredivclk: corediv-clock@f8268 {
267 compatible = "marvell,mv98dx3236-corediv-clock";
271 clock-output-names = "nand";
275 switch: switch@a8000000 {
276 compatible = "simple-bus";
277 #address-cells = <1>;
279 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
281 pp0: packet-processor@0 {
282 compatible = "marvell,prestera-98dx3236";
284 interrupts = <33>, <34>, <35>;
291 /* 25 MHz reference crystal */
293 compatible = "fixed-clock";
295 clock-frequency = <25000000>;
301 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
302 reg = <0x11000 0x100>;
306 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
307 reg = <0x11100 0x100>;
311 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
319 compatible = "marvell,armada-xp-timer";
320 clocks = <&coreclk 2>, <&refclk>;
321 clock-names = "nbclk", "fixed";
325 compatible = "marvell,armada-xp-wdt";
326 clocks = <&coreclk 2>, <&refclk>;
327 clock-names = "nbclk", "fixed";
331 reg = <0x20800 0x20>;
335 clocks = <&gateclk 18>;
339 clocks = <&gateclk 19>;
343 compatible = "marvell,98dx3236-pinctrl";
345 spi0_pins: spi0-pins {
346 marvell,pins = "mpp0", "mpp1",
348 marvell,function = "spi0";
353 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
354 pinctrl-0 = <&spi0_pins>;
355 pinctrl-names = "default";