arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35
  36 #include "skeleton.dtsi"
  37
  38 / {
  39         compatible = "brcm,cygnus";
  40         model = "Broadcom Cygnus SoC";
  41         interrupt-parent = <&gic>;
  42
  43         aliases {
  44                 serial0 = &uart3;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         next-level-cache = <&L2>;
  55                         reg = <0x0>;
  56                 };
  57         };
  58
  59         /include/ "bcm-cygnus-clock.dtsi"
  60
  61         pinctrl: pinctrl@0x0301d0c8 {
  62                 compatible = "brcm,cygnus-pinmux";
  63                 reg = <0x0301d0c8 0x30>,
  64                       <0x0301d24c 0x2c>;
  65         };
  66
  67         gpio_crmu: gpio@03024800 {
  68                 compatible = "brcm,cygnus-crmu-gpio";
  69                 reg = <0x03024800 0x50>,
  70                       <0x03024008 0x18>;
  71                 #gpio-cells = <2>;
  72                 gpio-controller;
  73         };
  74
  75         gpio_ccm: gpio@1800a000 {
  76                 compatible = "brcm,cygnus-ccm-gpio";
  77                 reg = <0x1800a000 0x50>,
  78                       <0x0301d164 0x20>;
  79                 #gpio-cells = <2>;
  80                 gpio-controller;
  81                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-controller;
  83         };
  84
  85         gpio_asiu: gpio@180a5000 {
  86                 compatible = "brcm,cygnus-asiu-gpio";
  87                 reg = <0x180a5000 0x668>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90
  91                 pinmux = <&pinctrl>;
  92
  93                 interrupt-controller;
  94                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
  95         };
  96
  97         amba {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 compatible = "arm,amba-bus", "simple-bus";
 101                 interrupt-parent = <&gic>;
 102                 ranges;
 103
 104                 wdt@18009000 {
 105                          compatible = "arm,sp805" , "arm,primecell";
 106                          reg = <0x18009000 0x1000>;
 107                          interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 108                          clocks = <&axi81_clk>;
 109                          clock-names = "apb_pclk";
 110                 };
 111         };
 112
 113         i2c0: i2c@18008000 {
 114                 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 115                 reg = <0x18008000 0x100>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 119                 clock-frequency = <100000>;
 120                 status = "disabled";
 121         };
 122
 123         i2c1: i2c@1800b000 {
 124                 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 125                 reg = <0x1800b000 0x100>;
 126                 #address-cells = <1>;
 127                 #size-cells = <0>;
 128                 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 129                 clock-frequency = <100000>;
 130                 status = "disabled";
 131         };
 132
 133         pcie0: pcie@18012000 {
 134                 compatible = "brcm,iproc-pcie";
 135                 reg = <0x18012000 0x1000>;
 136
 137                 #interrupt-cells = <1>;
 138                 interrupt-map-mask = <0 0 0 0>;
 139                 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
 140
 141                 linux,pci-domain = <0>;
 142
 143                 bus-range = <0x00 0xff>;
 144
 145                 #address-cells = <3>;
 146                 #size-cells = <2>;
 147                 device_type = "pci";
 148                 ranges = <0x81000000 0 0          0x28000000 0 0x00010000
 149                           0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
 150
 151                 status = "disabled";
 152         };
 153
 154         pcie1: pcie@18013000 {
 155                 compatible = "brcm,iproc-pcie";
 156                 reg = <0x18013000 0x1000>;
 157
 158                 #interrupt-cells = <1>;
 159                 interrupt-map-mask = <0 0 0 0>;
 160                 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
 161
 162                 linux,pci-domain = <1>;
 163
 164                 bus-range = <0x00 0xff>;
 165
 166                 #address-cells = <3>;
 167                 #size-cells = <2>;
 168                 device_type = "pci";
 169                 ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 170                           0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 171
 172                 status = "disabled";
 173         };
 174
 175         uart0: serial@18020000 {
 176                 compatible = "snps,dw-apb-uart";
 177                 reg = <0x18020000 0x100>;
 178                 reg-shift = <2>;
 179                 reg-io-width = <4>;
 180                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&axi81_clk>;
 182                 clock-frequency = <100000000>;
 183                 status = "disabled";
 184         };
 185
 186         uart1: serial@18021000 {
 187                 compatible = "snps,dw-apb-uart";
 188                 reg = <0x18021000 0x100>;
 189                 reg-shift = <2>;
 190                 reg-io-width = <4>;
 191                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&axi81_clk>;
 193                 clock-frequency = <100000000>;
 194                 status = "disabled";
 195         };
 196
 197         uart2: serial@18022000 {
 198                 compatible = "snps,dw-apb-uart";
 199                 reg = <0x18020000 0x100>;
 200                 reg-shift = <2>;
 201                 reg-io-width = <4>;
 202                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&axi81_clk>;
 204                 clock-frequency = <100000000>;
 205                 status = "disabled";
 206         };
 207
 208         uart3: serial@18023000 {
 209                 compatible = "snps,dw-apb-uart";
 210                 reg = <0x18023000 0x100>;
 211                 reg-shift = <2>;
 212                 reg-io-width = <4>;
 213                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&axi81_clk>;
 215                 clock-frequency = <100000000>;
 216                 status = "disabled";
 217         };
 218
 219         nand: nand@18046000 {
 220                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 221                 reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>;
 222                 reg-names = "nand", "iproc-idm", "iproc-ext";
 223                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 224
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227
 228                 brcm,nand-has-wp;
 229         };
 230
 231         gic: interrupt-controller@19021000 {
 232                 compatible = "arm,cortex-a9-gic";
 233                 #interrupt-cells = <3>;
 234                 #address-cells = <0>;
 235                 interrupt-controller;
 236                 reg = <0x19021000 0x1000>,
 237                       <0x19020100 0x100>;
 238         };
 239
 240         L2: l2-cache {
 241                 compatible = "arm,pl310-cache";
 242                 reg = <0x19022000 0x1000>;
 243                 cache-unified;
 244                 cache-level = <2>;
 245         };
 246
 247         timer@19020200 {
 248                 compatible = "arm,cortex-a9-global-timer";
 249                 reg = <0x19020200 0x100>;
 250                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&periph_clk>;
 252         };
 253
 254 };