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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
36 #include "skeleton.dtsi"
39 compatible = "brcm,cygnus";
40 model = "Broadcom Cygnus SoC";
41 interrupt-parent = <&gic>;
53 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
59 /include/ "bcm-cygnus-clock.dtsi"
62 compatible = "simple-bus";
63 ranges = <0x00000000 0x19000000 0x1000000>;
68 compatible = "arm,cortex-a9-global-timer";
69 reg = <0x20200 0x100>;
70 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&periph_clk>;
74 gic: interrupt-controller@21000 {
75 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
79 reg = <0x21000 0x1000>,
84 compatible = "arm,pl310-cache";
85 reg = <0x22000 0x1000>;
92 compatible = "simple-bus";
97 pinctrl: pinctrl@0x0301d0c8 {
98 compatible = "brcm,cygnus-pinmux";
99 reg = <0x0301d0c8 0x30>,
103 gpio_crmu: gpio@03024800 {
104 compatible = "brcm,cygnus-crmu-gpio";
105 reg = <0x03024800 0x50>,
111 gpio_ccm: gpio@1800a000 {
112 compatible = "brcm,cygnus-ccm-gpio";
113 reg = <0x1800a000 0x50>,
117 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-controller;
121 gpio_asiu: gpio@180a5000 {
122 compatible = "brcm,cygnus-asiu-gpio";
123 reg = <0x180a5000 0x668>;
129 interrupt-controller;
130 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
134 compatible = "arm,sp805" , "arm,primecell";
135 reg = <0x18009000 0x1000>;
136 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&axi81_clk>;
138 clock-names = "apb_pclk";
142 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
143 reg = <0x18008000 0x100>;
144 #address-cells = <1>;
146 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
147 clock-frequency = <100000>;
152 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
153 reg = <0x1800b000 0x100>;
154 #address-cells = <1>;
156 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
157 clock-frequency = <100000>;
161 pcie0: pcie@18012000 {
162 compatible = "brcm,iproc-pcie";
163 reg = <0x18012000 0x1000>;
165 #interrupt-cells = <1>;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
169 linux,pci-domain = <0>;
171 bus-range = <0x00 0xff>;
173 #address-cells = <3>;
176 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
177 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
182 pcie1: pcie@18013000 {
183 compatible = "brcm,iproc-pcie";
184 reg = <0x18013000 0x1000>;
186 #interrupt-cells = <1>;
187 interrupt-map-mask = <0 0 0 0>;
188 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
190 linux,pci-domain = <1>;
192 bus-range = <0x00 0xff>;
194 #address-cells = <3>;
197 ranges = <0x81000000 0 0 0x48000000 0 0x00010000
198 0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
203 uart0: serial@18020000 {
204 compatible = "snps,dw-apb-uart";
205 reg = <0x18020000 0x100>;
208 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&axi81_clk>;
210 clock-frequency = <100000000>;
214 uart1: serial@18021000 {
215 compatible = "snps,dw-apb-uart";
216 reg = <0x18021000 0x100>;
219 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&axi81_clk>;
221 clock-frequency = <100000000>;
225 uart2: serial@18022000 {
226 compatible = "snps,dw-apb-uart";
227 reg = <0x18020000 0x100>;
230 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&axi81_clk>;
232 clock-frequency = <100000000>;
236 uart3: serial@18023000 {
237 compatible = "snps,dw-apb-uart";
238 reg = <0x18023000 0x100>;
241 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&axi81_clk>;
243 clock-frequency = <100000000>;
247 nand: nand@18046000 {
248 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
250 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
252 reg-names = "nand", "iproc-idm", "iproc-ext";
253 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;