arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35
  36 #include "skeleton.dtsi"
  37
  38 / {
  39         compatible = "brcm,cygnus";
  40         model = "Broadcom Cygnus SoC";
  41         interrupt-parent = <&gic>;
  42
  43         aliases {
  44                 serial0 = &uart3;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         next-level-cache = <&L2>;
  55                         reg = <0x0>;
  56                 };
  57         };
  58
  59         /include/ "bcm-cygnus-clock.dtsi"
  60
  61         core {
  62                 compatible = "simple-bus";
  63                 ranges = <0x00000000 0x19000000 0x1000000>;
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66
  67                 timer@20200 {
  68                         compatible = "arm,cortex-a9-global-timer";
  69                         reg = <0x20200 0x100>;
  70                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&periph_clk>;
  72                 };
  73
  74                 gic: interrupt-controller@21000 {
  75                         compatible = "arm,cortex-a9-gic";
  76                         #interrupt-cells = <3>;
  77                         #address-cells = <0>;
  78                         interrupt-controller;
  79                         reg = <0x21000 0x1000>,
  80                               <0x20100 0x100>;
  81                 };
  82
  83                 L2: l2-cache {
  84                         compatible = "arm,pl310-cache";
  85                         reg = <0x22000 0x1000>;
  86                         cache-unified;
  87                         cache-level = <2>;
  88                 };
  89         };
  90
  91         pinctrl: pinctrl@0x0301d0c8 {
  92                 compatible = "brcm,cygnus-pinmux";
  93                 reg = <0x0301d0c8 0x30>,
  94                       <0x0301d24c 0x2c>;
  95         };
  96
  97         gpio_crmu: gpio@03024800 {
  98                 compatible = "brcm,cygnus-crmu-gpio";
  99                 reg = <0x03024800 0x50>,
 100                       <0x03024008 0x18>;
 101                 #gpio-cells = <2>;
 102                 gpio-controller;
 103         };
 104
 105         gpio_ccm: gpio@1800a000 {
 106                 compatible = "brcm,cygnus-ccm-gpio";
 107                 reg = <0x1800a000 0x50>,
 108                       <0x0301d164 0x20>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 112                 interrupt-controller;
 113         };
 114
 115         gpio_asiu: gpio@180a5000 {
 116                 compatible = "brcm,cygnus-asiu-gpio";
 117                 reg = <0x180a5000 0x668>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120
 121                 pinmux = <&pinctrl>;
 122
 123                 interrupt-controller;
 124                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 125         };
 126
 127         amba {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 compatible = "arm,amba-bus", "simple-bus";
 131                 interrupt-parent = <&gic>;
 132                 ranges;
 133
 134                 wdt@18009000 {
 135                          compatible = "arm,sp805" , "arm,primecell";
 136                          reg = <0x18009000 0x1000>;
 137                          interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 138                          clocks = <&axi81_clk>;
 139                          clock-names = "apb_pclk";
 140                 };
 141         };
 142
 143         i2c0: i2c@18008000 {
 144                 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 145                 reg = <0x18008000 0x100>;
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 149                 clock-frequency = <100000>;
 150                 status = "disabled";
 151         };
 152
 153         i2c1: i2c@1800b000 {
 154                 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 155                 reg = <0x1800b000 0x100>;
 156                 #address-cells = <1>;
 157                 #size-cells = <0>;
 158                 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 159                 clock-frequency = <100000>;
 160                 status = "disabled";
 161         };
 162
 163         pcie0: pcie@18012000 {
 164                 compatible = "brcm,iproc-pcie";
 165                 reg = <0x18012000 0x1000>;
 166
 167                 #interrupt-cells = <1>;
 168                 interrupt-map-mask = <0 0 0 0>;
 169                 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
 170
 171                 linux,pci-domain = <0>;
 172
 173                 bus-range = <0x00 0xff>;
 174
 175                 #address-cells = <3>;
 176                 #size-cells = <2>;
 177                 device_type = "pci";
 178                 ranges = <0x81000000 0 0          0x28000000 0 0x00010000
 179                           0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
 180
 181                 status = "disabled";
 182         };
 183
 184         pcie1: pcie@18013000 {
 185                 compatible = "brcm,iproc-pcie";
 186                 reg = <0x18013000 0x1000>;
 187
 188                 #interrupt-cells = <1>;
 189                 interrupt-map-mask = <0 0 0 0>;
 190                 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
 191
 192                 linux,pci-domain = <1>;
 193
 194                 bus-range = <0x00 0xff>;
 195
 196                 #address-cells = <3>;
 197                 #size-cells = <2>;
 198                 device_type = "pci";
 199                 ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 200                           0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 201
 202                 status = "disabled";
 203         };
 204
 205         uart0: serial@18020000 {
 206                 compatible = "snps,dw-apb-uart";
 207                 reg = <0x18020000 0x100>;
 208                 reg-shift = <2>;
 209                 reg-io-width = <4>;
 210                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&axi81_clk>;
 212                 clock-frequency = <100000000>;
 213                 status = "disabled";
 214         };
 215
 216         uart1: serial@18021000 {
 217                 compatible = "snps,dw-apb-uart";
 218                 reg = <0x18021000 0x100>;
 219                 reg-shift = <2>;
 220                 reg-io-width = <4>;
 221                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&axi81_clk>;
 223                 clock-frequency = <100000000>;
 224                 status = "disabled";
 225         };
 226
 227         uart2: serial@18022000 {
 228                 compatible = "snps,dw-apb-uart";
 229                 reg = <0x18020000 0x100>;
 230                 reg-shift = <2>;
 231                 reg-io-width = <4>;
 232                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&axi81_clk>;
 234                 clock-frequency = <100000000>;
 235                 status = "disabled";
 236         };
 237
 238         uart3: serial@18023000 {
 239                 compatible = "snps,dw-apb-uart";
 240                 reg = <0x18023000 0x100>;
 241                 reg-shift = <2>;
 242                 reg-io-width = <4>;
 243                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&axi81_clk>;
 245                 clock-frequency = <100000000>;
 246                 status = "disabled";
 247         };
 248
 249         nand: nand@18046000 {
 250                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 251                 reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>;
 252                 reg-names = "nand", "iproc-idm", "iproc-ext";
 253                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 254
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257
 258                 brcm,nand-has-wp;
 259         };
 260 };