2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 #interrupt-cells = <3>;
71 reg = <0x48281000 0x1000>;
72 interrupt-parent = <&gic>;
76 * The soc node represents the soc top level view. It is used for IPs
77 * that are not memory mapped in the MPU view or for the MPU itself.
80 compatible = "ti,omap-infra";
82 compatible = "ti,omap5-mpu";
88 * XXX: Use a flat representation of the SOC interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since it will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
95 compatible = "ti,dra7-l3-noc", "simple-bus";
99 ti,hwmods = "l3_main_1", "l3_main_2";
100 reg = <0x44000000 0x1000000>,
102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
105 l4_cfg: l4@4a000000 {
106 compatible = "ti,dra7-l4-cfg", "simple-bus";
107 #address-cells = <1>;
109 ranges = <0 0x4a000000 0x22c000>;
112 compatible = "ti,dra7-scm-core", "simple-bus";
113 reg = <0x2000 0x2000>;
114 #address-cells = <1>;
116 ranges = <0 0x2000 0x2000>;
118 scm_conf: scm_conf@0 {
119 compatible = "syscon";
121 #address-cells = <1>;
124 pbias_regulator: pbias_regulator {
125 compatible = "ti,pbias-omap";
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap5 {
129 regulator-name = "pbias_mmc_omap5";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
136 dra7_pmx_core: pinmux@1400 {
137 compatible = "ti,dra7-padconf",
139 reg = <0x1400 0x0464>;
140 #address-cells = <1>;
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 pinctrl-single,register-width = <32>;
145 pinctrl-single,function-mask = <0x3fffffff>;
149 cm_core_aon: cm_core_aon@5000 {
150 compatible = "ti,dra7-cm-core-aon";
151 reg = <0x5000 0x2000>;
153 cm_core_aon_clocks: clocks {
154 #address-cells = <1>;
158 cm_core_aon_clockdomains: clockdomains {
162 cm_core: cm_core@8000 {
163 compatible = "ti,dra7-cm-core";
164 reg = <0x8000 0x3000>;
166 cm_core_clocks: clocks {
167 #address-cells = <1>;
171 cm_core_clockdomains: clockdomains {
176 l4_wkup: l4@4ae00000 {
177 compatible = "ti,dra7-l4-wkup", "simple-bus";
178 #address-cells = <1>;
180 ranges = <0 0x4ae00000 0x3f000>;
182 counter32k: counter@4000 {
183 compatible = "ti,omap-counter32k";
185 ti,hwmods = "counter_32k";
189 compatible = "ti,dra7-prm";
190 reg = <0x6000 0x3000>;
191 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
198 prm_clockdomains: clockdomains {
204 compatible = "simple-bus";
206 #address-cells = <1>;
207 ranges = <0x51000000 0x51000000 0x3000
208 0x0 0x20000000 0x10000000>;
210 compatible = "ti,dra7-pcie";
211 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
212 reg-names = "rc_dbics", "ti_conf", "config";
213 interrupts = <0 232 0x4>, <0 233 0x4>;
214 #address-cells = <3>;
217 ranges = <0x81000000 0 0 0x03000 0 0x00010000
218 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
219 #interrupt-cells = <1>;
223 phy-names = "pcie-phy0";
224 interrupt-map-mask = <0 0 0 7>;
225 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
226 <0 0 0 2 &pcie1_intc 2>,
227 <0 0 0 3 &pcie1_intc 3>,
228 <0 0 0 4 &pcie1_intc 4>;
229 pcie1_intc: interrupt-controller {
230 interrupt-controller;
231 #address-cells = <0>;
232 #interrupt-cells = <1>;
238 compatible = "simple-bus";
240 #address-cells = <1>;
241 ranges = <0x51800000 0x51800000 0x3000
242 0x0 0x30000000 0x10000000>;
245 compatible = "ti,dra7-pcie";
246 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
247 reg-names = "rc_dbics", "ti_conf", "config";
248 interrupts = <0 355 0x4>, <0 356 0x4>;
249 #address-cells = <3>;
252 ranges = <0x81000000 0 0 0x03000 0 0x00010000
253 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
254 #interrupt-cells = <1>;
258 phy-names = "pcie-phy0";
259 interrupt-map-mask = <0 0 0 7>;
260 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
261 <0 0 0 2 &pcie2_intc 2>,
262 <0 0 0 3 &pcie2_intc 3>,
263 <0 0 0 4 &pcie2_intc 4>;
264 pcie2_intc: interrupt-controller {
265 interrupt-controller;
266 #address-cells = <0>;
267 #interrupt-cells = <1>;
272 bandgap: bandgap@4a0021e0 {
273 reg = <0x4a0021e0 0xc
279 compatible = "ti,dra752-bandgap";
280 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
281 #thermal-sensor-cells = <1>;
284 dra7_ctrl_core: ctrl_core@4a002000 {
285 compatible = "syscon";
286 reg = <0x4a002000 0x6d0>;
289 dra7_ctrl_general: tisyscon@4a002e00 {
290 compatible = "syscon";
291 reg = <0x4a002e00 0x7c>;
294 sdma: dma-controller@4a056000 {
295 compatible = "ti,omap4430-sdma";
296 reg = <0x4a056000 0x1000>;
297 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
303 dma-requests = <127>;
306 gpio1: gpio@4ae10000 {
307 compatible = "ti,omap4-gpio";
308 reg = <0x4ae10000 0x200>;
309 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
317 gpio2: gpio@48055000 {
318 compatible = "ti,omap4-gpio";
319 reg = <0x48055000 0x200>;
320 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio3: gpio@48057000 {
329 compatible = "ti,omap4-gpio";
330 reg = <0x48057000 0x200>;
331 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
339 gpio4: gpio@48059000 {
340 compatible = "ti,omap4-gpio";
341 reg = <0x48059000 0x200>;
342 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
350 gpio5: gpio@4805b000 {
351 compatible = "ti,omap4-gpio";
352 reg = <0x4805b000 0x200>;
353 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
361 gpio6: gpio@4805d000 {
362 compatible = "ti,omap4-gpio";
363 reg = <0x4805d000 0x200>;
364 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
372 gpio7: gpio@48051000 {
373 compatible = "ti,omap4-gpio";
374 reg = <0x48051000 0x200>;
375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
383 gpio8: gpio@48053000 {
384 compatible = "ti,omap4-gpio";
385 reg = <0x48053000 0x200>;
386 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
394 uart1: serial@4806a000 {
395 compatible = "ti,omap4-uart";
396 reg = <0x4806a000 0x100>;
397 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
399 clock-frequency = <48000000>;
401 dmas = <&sdma 49>, <&sdma 50>;
402 dma-names = "tx", "rx";
405 uart2: serial@4806c000 {
406 compatible = "ti,omap4-uart";
407 reg = <0x4806c000 0x100>;
408 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
410 clock-frequency = <48000000>;
412 dmas = <&sdma 51>, <&sdma 52>;
413 dma-names = "tx", "rx";
416 uart3: serial@48020000 {
417 compatible = "ti,omap4-uart";
418 reg = <0x48020000 0x100>;
419 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
421 clock-frequency = <48000000>;
423 dmas = <&sdma 53>, <&sdma 54>;
424 dma-names = "tx", "rx";
427 uart4: serial@4806e000 {
428 compatible = "ti,omap4-uart";
429 reg = <0x4806e000 0x100>;
430 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
432 clock-frequency = <48000000>;
434 dmas = <&sdma 55>, <&sdma 56>;
435 dma-names = "tx", "rx";
438 uart5: serial@48066000 {
439 compatible = "ti,omap4-uart";
440 reg = <0x48066000 0x100>;
441 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
443 clock-frequency = <48000000>;
445 dmas = <&sdma 63>, <&sdma 64>;
446 dma-names = "tx", "rx";
449 uart6: serial@48068000 {
450 compatible = "ti,omap4-uart";
451 reg = <0x48068000 0x100>;
452 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
454 clock-frequency = <48000000>;
456 dmas = <&sdma 79>, <&sdma 80>;
457 dma-names = "tx", "rx";
460 uart7: serial@48420000 {
461 compatible = "ti,omap4-uart";
462 reg = <0x48420000 0x100>;
463 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
465 clock-frequency = <48000000>;
469 uart8: serial@48422000 {
470 compatible = "ti,omap4-uart";
471 reg = <0x48422000 0x100>;
472 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
474 clock-frequency = <48000000>;
478 uart9: serial@48424000 {
479 compatible = "ti,omap4-uart";
480 reg = <0x48424000 0x100>;
481 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
483 clock-frequency = <48000000>;
487 uart10: serial@4ae2b000 {
488 compatible = "ti,omap4-uart";
489 reg = <0x4ae2b000 0x100>;
490 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "uart10";
492 clock-frequency = <48000000>;
496 mailbox1: mailbox@4a0f4000 {
497 compatible = "ti,omap4-mailbox";
498 reg = <0x4a0f4000 0x200>;
499 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
502 ti,hwmods = "mailbox1";
504 ti,mbox-num-users = <3>;
505 ti,mbox-num-fifos = <8>;
509 mailbox2: mailbox@4883a000 {
510 compatible = "ti,omap4-mailbox";
511 reg = <0x4883a000 0x200>;
512 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
516 ti,hwmods = "mailbox2";
518 ti,mbox-num-users = <4>;
519 ti,mbox-num-fifos = <12>;
523 mailbox3: mailbox@4883c000 {
524 compatible = "ti,omap4-mailbox";
525 reg = <0x4883c000 0x200>;
526 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
530 ti,hwmods = "mailbox3";
532 ti,mbox-num-users = <4>;
533 ti,mbox-num-fifos = <12>;
537 mailbox4: mailbox@4883e000 {
538 compatible = "ti,omap4-mailbox";
539 reg = <0x4883e000 0x200>;
540 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
544 ti,hwmods = "mailbox4";
546 ti,mbox-num-users = <4>;
547 ti,mbox-num-fifos = <12>;
551 mailbox5: mailbox@48840000 {
552 compatible = "ti,omap4-mailbox";
553 reg = <0x48840000 0x200>;
554 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
558 ti,hwmods = "mailbox5";
560 ti,mbox-num-users = <4>;
561 ti,mbox-num-fifos = <12>;
565 mailbox6: mailbox@48842000 {
566 compatible = "ti,omap4-mailbox";
567 reg = <0x48842000 0x200>;
568 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
572 ti,hwmods = "mailbox6";
574 ti,mbox-num-users = <4>;
575 ti,mbox-num-fifos = <12>;
579 mailbox7: mailbox@48844000 {
580 compatible = "ti,omap4-mailbox";
581 reg = <0x48844000 0x200>;
582 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
586 ti,hwmods = "mailbox7";
588 ti,mbox-num-users = <4>;
589 ti,mbox-num-fifos = <12>;
593 mailbox8: mailbox@48846000 {
594 compatible = "ti,omap4-mailbox";
595 reg = <0x48846000 0x200>;
596 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
600 ti,hwmods = "mailbox8";
602 ti,mbox-num-users = <4>;
603 ti,mbox-num-fifos = <12>;
607 mailbox9: mailbox@4885e000 {
608 compatible = "ti,omap4-mailbox";
609 reg = <0x4885e000 0x200>;
610 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
614 ti,hwmods = "mailbox9";
616 ti,mbox-num-users = <4>;
617 ti,mbox-num-fifos = <12>;
621 mailbox10: mailbox@48860000 {
622 compatible = "ti,omap4-mailbox";
623 reg = <0x48860000 0x200>;
624 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
628 ti,hwmods = "mailbox10";
630 ti,mbox-num-users = <4>;
631 ti,mbox-num-fifos = <12>;
635 mailbox11: mailbox@48862000 {
636 compatible = "ti,omap4-mailbox";
637 reg = <0x48862000 0x200>;
638 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
642 ti,hwmods = "mailbox11";
644 ti,mbox-num-users = <4>;
645 ti,mbox-num-fifos = <12>;
649 mailbox12: mailbox@48864000 {
650 compatible = "ti,omap4-mailbox";
651 reg = <0x48864000 0x200>;
652 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
656 ti,hwmods = "mailbox12";
658 ti,mbox-num-users = <4>;
659 ti,mbox-num-fifos = <12>;
663 mailbox13: mailbox@48802000 {
664 compatible = "ti,omap4-mailbox";
665 reg = <0x48802000 0x200>;
666 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
670 ti,hwmods = "mailbox13";
672 ti,mbox-num-users = <4>;
673 ti,mbox-num-fifos = <12>;
677 timer1: timer@4ae18000 {
678 compatible = "ti,omap5430-timer";
679 reg = <0x4ae18000 0x80>;
680 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
681 ti,hwmods = "timer1";
685 timer2: timer@48032000 {
686 compatible = "ti,omap5430-timer";
687 reg = <0x48032000 0x80>;
688 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
689 ti,hwmods = "timer2";
692 timer3: timer@48034000 {
693 compatible = "ti,omap5430-timer";
694 reg = <0x48034000 0x80>;
695 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "timer3";
699 timer4: timer@48036000 {
700 compatible = "ti,omap5430-timer";
701 reg = <0x48036000 0x80>;
702 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
703 ti,hwmods = "timer4";
706 timer5: timer@48820000 {
707 compatible = "ti,omap5430-timer";
708 reg = <0x48820000 0x80>;
709 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
710 ti,hwmods = "timer5";
713 timer6: timer@48822000 {
714 compatible = "ti,omap5430-timer";
715 reg = <0x48822000 0x80>;
716 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
717 ti,hwmods = "timer6";
720 timer7: timer@48824000 {
721 compatible = "ti,omap5430-timer";
722 reg = <0x48824000 0x80>;
723 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "timer7";
727 timer8: timer@48826000 {
728 compatible = "ti,omap5430-timer";
729 reg = <0x48826000 0x80>;
730 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
731 ti,hwmods = "timer8";
734 timer9: timer@4803e000 {
735 compatible = "ti,omap5430-timer";
736 reg = <0x4803e000 0x80>;
737 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "timer9";
741 timer10: timer@48086000 {
742 compatible = "ti,omap5430-timer";
743 reg = <0x48086000 0x80>;
744 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
745 ti,hwmods = "timer10";
748 timer11: timer@48088000 {
749 compatible = "ti,omap5430-timer";
750 reg = <0x48088000 0x80>;
751 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "timer11";
755 timer13: timer@48828000 {
756 compatible = "ti,omap5430-timer";
757 reg = <0x48828000 0x80>;
758 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
759 ti,hwmods = "timer13";
763 timer14: timer@4882a000 {
764 compatible = "ti,omap5430-timer";
765 reg = <0x4882a000 0x80>;
766 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
767 ti,hwmods = "timer14";
771 timer15: timer@4882c000 {
772 compatible = "ti,omap5430-timer";
773 reg = <0x4882c000 0x80>;
774 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
775 ti,hwmods = "timer15";
779 timer16: timer@4882e000 {
780 compatible = "ti,omap5430-timer";
781 reg = <0x4882e000 0x80>;
782 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
783 ti,hwmods = "timer16";
788 compatible = "ti,omap3-wdt";
789 reg = <0x4ae14000 0x80>;
790 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
791 ti,hwmods = "wd_timer2";
794 hwspinlock: spinlock@4a0f6000 {
795 compatible = "ti,omap4-hwspinlock";
796 reg = <0x4a0f6000 0x1000>;
797 ti,hwmods = "spinlock";
802 compatible = "ti,omap5-dmm";
803 reg = <0x4e000000 0x800>;
804 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
809 compatible = "ti,omap4-i2c";
810 reg = <0x48070000 0x100>;
811 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
812 #address-cells = <1>;
819 compatible = "ti,omap4-i2c";
820 reg = <0x48072000 0x100>;
821 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
822 #address-cells = <1>;
829 compatible = "ti,omap4-i2c";
830 reg = <0x48060000 0x100>;
831 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
832 #address-cells = <1>;
839 compatible = "ti,omap4-i2c";
840 reg = <0x4807a000 0x100>;
841 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
842 #address-cells = <1>;
849 compatible = "ti,omap4-i2c";
850 reg = <0x4807c000 0x100>;
851 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
852 #address-cells = <1>;
859 compatible = "ti,omap4-hsmmc";
860 reg = <0x4809c000 0x400>;
861 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
864 ti,needs-special-reset;
865 dmas = <&sdma 61>, <&sdma 62>;
866 dma-names = "tx", "rx";
868 pbias-supply = <&pbias_mmc_reg>;
872 compatible = "ti,omap4-hsmmc";
873 reg = <0x480b4000 0x400>;
874 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
876 ti,needs-special-reset;
877 dmas = <&sdma 47>, <&sdma 48>;
878 dma-names = "tx", "rx";
883 compatible = "ti,omap4-hsmmc";
884 reg = <0x480ad000 0x400>;
885 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
887 ti,needs-special-reset;
888 dmas = <&sdma 77>, <&sdma 78>;
889 dma-names = "tx", "rx";
894 compatible = "ti,omap4-hsmmc";
895 reg = <0x480d1000 0x400>;
896 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
898 ti,needs-special-reset;
899 dmas = <&sdma 57>, <&sdma 58>;
900 dma-names = "tx", "rx";
904 abb_mpu: regulator-abb-mpu {
905 compatible = "ti,abb-v3";
906 regulator-name = "abb_mpu";
907 #address-cells = <0>;
909 clocks = <&sys_clkin1>;
910 ti,settling-time = <50>;
911 ti,clock-cycles = <16>;
913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
914 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
916 reg-names = "setup-address", "control-address",
917 "int-address", "efuse-address",
919 ti,tranxdone-status-mask = <0x80>;
920 /* LDOVBBMPU_FBB_MUX_CTRL */
921 ti,ldovbb-override-mask = <0x400>;
922 /* LDOVBBMPU_FBB_VSET_OUT */
923 ti,ldovbb-vset-mask = <0x1F>;
926 * NOTE: only FBB mode used but actual vset will
927 * determine final biasing
930 /*uV ABB efuse rbb_m fbb_m vset_m*/
931 1060000 0 0x0 0 0x02000000 0x01F00000
932 1160000 0 0x4 0 0x02000000 0x01F00000
933 1210000 0 0x8 0 0x02000000 0x01F00000
937 abb_ivahd: regulator-abb-ivahd {
938 compatible = "ti,abb-v3";
939 regulator-name = "abb_ivahd";
940 #address-cells = <0>;
942 clocks = <&sys_clkin1>;
943 ti,settling-time = <50>;
944 ti,clock-cycles = <16>;
946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
947 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
949 reg-names = "setup-address", "control-address",
950 "int-address", "efuse-address",
952 ti,tranxdone-status-mask = <0x40000000>;
953 /* LDOVBBIVA_FBB_MUX_CTRL */
954 ti,ldovbb-override-mask = <0x400>;
955 /* LDOVBBIVA_FBB_VSET_OUT */
956 ti,ldovbb-vset-mask = <0x1F>;
959 * NOTE: only FBB mode used but actual vset will
960 * determine final biasing
963 /*uV ABB efuse rbb_m fbb_m vset_m*/
964 1055000 0 0x0 0 0x02000000 0x01F00000
965 1150000 0 0x4 0 0x02000000 0x01F00000
966 1250000 0 0x8 0 0x02000000 0x01F00000
970 abb_dspeve: regulator-abb-dspeve {
971 compatible = "ti,abb-v3";
972 regulator-name = "abb_dspeve";
973 #address-cells = <0>;
975 clocks = <&sys_clkin1>;
976 ti,settling-time = <50>;
977 ti,clock-cycles = <16>;
979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
980 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
982 reg-names = "setup-address", "control-address",
983 "int-address", "efuse-address",
985 ti,tranxdone-status-mask = <0x20000000>;
986 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
987 ti,ldovbb-override-mask = <0x400>;
988 /* LDOVBBDSPEVE_FBB_VSET_OUT */
989 ti,ldovbb-vset-mask = <0x1F>;
992 * NOTE: only FBB mode used but actual vset will
993 * determine final biasing
996 /*uV ABB efuse rbb_m fbb_m vset_m*/
997 1055000 0 0x0 0 0x02000000 0x01F00000
998 1150000 0 0x4 0 0x02000000 0x01F00000
999 1250000 0 0x8 0 0x02000000 0x01F00000
1003 abb_gpu: regulator-abb-gpu {
1004 compatible = "ti,abb-v3";
1005 regulator-name = "abb_gpu";
1006 #address-cells = <0>;
1008 clocks = <&sys_clkin1>;
1009 ti,settling-time = <50>;
1010 ti,clock-cycles = <16>;
1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1013 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
1015 reg-names = "setup-address", "control-address",
1016 "int-address", "efuse-address",
1018 ti,tranxdone-status-mask = <0x10000000>;
1019 /* LDOVBBGPU_FBB_MUX_CTRL */
1020 ti,ldovbb-override-mask = <0x400>;
1021 /* LDOVBBGPU_FBB_VSET_OUT */
1022 ti,ldovbb-vset-mask = <0x1F>;
1025 * NOTE: only FBB mode used but actual vset will
1026 * determine final biasing
1029 /*uV ABB efuse rbb_m fbb_m vset_m*/
1030 1090000 0 0x0 0 0x02000000 0x01F00000
1031 1210000 0 0x4 0 0x02000000 0x01F00000
1032 1280000 0 0x8 0 0x02000000 0x01F00000
1036 mcspi1: spi@48098000 {
1037 compatible = "ti,omap4-mcspi";
1038 reg = <0x48098000 0x200>;
1039 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1040 #address-cells = <1>;
1042 ti,hwmods = "mcspi1";
1043 ti,spi-num-cs = <4>;
1052 dma-names = "tx0", "rx0", "tx1", "rx1",
1053 "tx2", "rx2", "tx3", "rx3";
1054 status = "disabled";
1057 mcspi2: spi@4809a000 {
1058 compatible = "ti,omap4-mcspi";
1059 reg = <0x4809a000 0x200>;
1060 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cells = <1>;
1063 ti,hwmods = "mcspi2";
1064 ti,spi-num-cs = <2>;
1069 dma-names = "tx0", "rx0", "tx1", "rx1";
1070 status = "disabled";
1073 mcspi3: spi@480b8000 {
1074 compatible = "ti,omap4-mcspi";
1075 reg = <0x480b8000 0x200>;
1076 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1077 #address-cells = <1>;
1079 ti,hwmods = "mcspi3";
1080 ti,spi-num-cs = <2>;
1081 dmas = <&sdma 15>, <&sdma 16>;
1082 dma-names = "tx0", "rx0";
1083 status = "disabled";
1086 mcspi4: spi@480ba000 {
1087 compatible = "ti,omap4-mcspi";
1088 reg = <0x480ba000 0x200>;
1089 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1090 #address-cells = <1>;
1092 ti,hwmods = "mcspi4";
1093 ti,spi-num-cs = <1>;
1094 dmas = <&sdma 70>, <&sdma 71>;
1095 dma-names = "tx0", "rx0";
1096 status = "disabled";
1099 qspi: qspi@4b300000 {
1100 compatible = "ti,dra7xxx-qspi";
1101 reg = <0x4b300000 0x100>;
1102 reg-names = "qspi_base";
1103 #address-cells = <1>;
1106 clocks = <&qspi_gfclk_div>;
1107 clock-names = "fck";
1109 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1110 status = "disabled";
1113 omap_control_sata: control-phy@4a002374 {
1114 compatible = "ti,control-phy-pipe3";
1115 reg = <0x4a002374 0x4>;
1116 reg-names = "power";
1117 clocks = <&sys_clkin1>;
1118 clock-names = "sysclk";
1123 compatible = "ti,omap-ocp2scp";
1124 #address-cells = <1>;
1127 reg = <0x4a090000 0x20>;
1128 ti,hwmods = "ocp2scp3";
1129 sata_phy: phy@4A096000 {
1130 compatible = "ti,phy-pipe3-sata";
1131 reg = <0x4A096000 0x80>, /* phy_rx */
1132 <0x4A096400 0x64>, /* phy_tx */
1133 <0x4A096800 0x40>; /* pll_ctrl */
1134 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1135 ctrl-module = <&omap_control_sata>;
1136 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1137 clock-names = "sysclk", "refclk";
1141 pcie1_phy: pciephy@4a094000 {
1142 compatible = "ti,phy-pipe3-pcie";
1143 reg = <0x4a094000 0x80>, /* phy_rx */
1144 <0x4a094400 0x64>; /* phy_tx */
1145 reg-names = "phy_rx", "phy_tx";
1146 ctrl-module = <&omap_control_pcie1phy>;
1147 clocks = <&dpll_pcie_ref_ck>,
1148 <&dpll_pcie_ref_m2ldo_ck>,
1149 <&optfclk_pciephy1_32khz>,
1150 <&optfclk_pciephy1_clk>,
1151 <&optfclk_pciephy1_div_clk>,
1152 <&optfclk_pciephy_div>;
1153 clock-names = "dpll_ref", "dpll_ref_m2",
1154 "wkupclk", "refclk",
1155 "div-clk", "phy-div";
1159 pcie2_phy: pciephy@4a095000 {
1160 compatible = "ti,phy-pipe3-pcie";
1161 reg = <0x4a095000 0x80>, /* phy_rx */
1162 <0x4a095400 0x64>; /* phy_tx */
1163 reg-names = "phy_rx", "phy_tx";
1164 ctrl-module = <&omap_control_pcie2phy>;
1165 clocks = <&dpll_pcie_ref_ck>,
1166 <&dpll_pcie_ref_m2ldo_ck>,
1167 <&optfclk_pciephy2_32khz>,
1168 <&optfclk_pciephy2_clk>,
1169 <&optfclk_pciephy2_div_clk>,
1170 <&optfclk_pciephy_div>;
1171 clock-names = "dpll_ref", "dpll_ref_m2",
1172 "wkupclk", "refclk",
1173 "div-clk", "phy-div";
1175 status = "disabled";
1179 sata: sata@4a141100 {
1180 compatible = "snps,dwc-ahci";
1181 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1182 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1184 phy-names = "sata-phy";
1185 clocks = <&sata_ref_clk>;
1189 omap_control_pcie1phy: control-phy@0x4a003c40 {
1190 compatible = "ti,control-phy-pcie";
1191 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1192 reg-names = "power", "control_sma", "pcie_pcs";
1193 clocks = <&sys_clkin1>;
1194 clock-names = "sysclk";
1197 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1198 compatible = "ti,control-phy-pcie";
1199 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1200 reg-names = "power", "control_sma", "pcie_pcs";
1201 clocks = <&sys_clkin1>;
1202 clock-names = "sysclk";
1203 status = "disabled";
1207 compatible = "ti,am3352-rtc";
1208 reg = <0x48838000 0x100>;
1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1211 ti,hwmods = "rtcss";
1212 clocks = <&sys_32k_ck>;
1215 omap_control_usb2phy1: control-phy@4a002300 {
1216 compatible = "ti,control-phy-usb2";
1217 reg = <0x4a002300 0x4>;
1218 reg-names = "power";
1221 omap_control_usb3phy1: control-phy@4a002370 {
1222 compatible = "ti,control-phy-pipe3";
1223 reg = <0x4a002370 0x4>;
1224 reg-names = "power";
1227 omap_control_usb2phy2: control-phy@0x4a002e74 {
1228 compatible = "ti,control-phy-usb2-dra7";
1229 reg = <0x4a002e74 0x4>;
1230 reg-names = "power";
1235 compatible = "ti,omap-ocp2scp";
1236 #address-cells = <1>;
1239 reg = <0x4a080000 0x20>;
1240 ti,hwmods = "ocp2scp1";
1242 usb2_phy1: phy@4a084000 {
1243 compatible = "ti,omap-usb2";
1244 reg = <0x4a084000 0x400>;
1245 ctrl-module = <&omap_control_usb2phy1>;
1246 clocks = <&usb_phy1_always_on_clk32k>,
1247 <&usb_otg_ss1_refclk960m>;
1248 clock-names = "wkupclk",
1253 usb2_phy2: phy@4a085000 {
1254 compatible = "ti,omap-usb2";
1255 reg = <0x4a085000 0x400>;
1256 ctrl-module = <&omap_control_usb2phy2>;
1257 clocks = <&usb_phy2_always_on_clk32k>,
1258 <&usb_otg_ss2_refclk960m>;
1259 clock-names = "wkupclk",
1264 usb3_phy1: phy@4a084400 {
1265 compatible = "ti,omap-usb3";
1266 reg = <0x4a084400 0x80>,
1269 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1270 ctrl-module = <&omap_control_usb3phy1>;
1271 clocks = <&usb_phy3_always_on_clk32k>,
1273 <&usb_otg_ss1_refclk960m>;
1274 clock-names = "wkupclk",
1281 omap_dwc3_1: omap_dwc3_1@48880000 {
1282 compatible = "ti,dwc3";
1283 ti,hwmods = "usb_otg_ss1";
1284 reg = <0x48880000 0x10000>;
1285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1286 #address-cells = <1>;
1290 usb1: usb@48890000 {
1291 compatible = "snps,dwc3";
1292 reg = <0x48890000 0x17000>;
1293 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1294 phys = <&usb2_phy1>, <&usb3_phy1>;
1295 phy-names = "usb2-phy", "usb3-phy";
1297 maximum-speed = "super-speed";
1299 snps,dis_u3_susphy_quirk;
1300 snps,dis_u2_susphy_quirk;
1304 omap_dwc3_2: omap_dwc3_2@488c0000 {
1305 compatible = "ti,dwc3";
1306 ti,hwmods = "usb_otg_ss2";
1307 reg = <0x488c0000 0x10000>;
1308 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cells = <1>;
1313 usb2: usb@488d0000 {
1314 compatible = "snps,dwc3";
1315 reg = <0x488d0000 0x17000>;
1316 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1317 phys = <&usb2_phy2>;
1318 phy-names = "usb2-phy";
1320 maximum-speed = "high-speed";
1322 snps,dis_u3_susphy_quirk;
1323 snps,dis_u2_susphy_quirk;
1327 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1328 omap_dwc3_3: omap_dwc3_3@48900000 {
1329 compatible = "ti,dwc3";
1330 ti,hwmods = "usb_otg_ss3";
1331 reg = <0x48900000 0x10000>;
1332 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cells = <1>;
1337 status = "disabled";
1338 usb3: usb@48910000 {
1339 compatible = "snps,dwc3";
1340 reg = <0x48910000 0x17000>;
1341 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1343 maximum-speed = "high-speed";
1345 snps,dis_u3_susphy_quirk;
1346 snps,dis_u2_susphy_quirk;
1351 compatible = "ti,am3352-elm";
1352 reg = <0x48078000 0xfc0>; /* device IO registers */
1353 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1355 status = "disabled";
1358 gpmc: gpmc@50000000 {
1359 compatible = "ti,am3352-gpmc";
1361 reg = <0x50000000 0x37c>; /* device IO registers */
1362 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1364 gpmc,num-waitpins = <2>;
1365 #address-cells = <2>;
1367 status = "disabled";
1371 compatible = "ti,dra7-atl";
1372 reg = <0x4843c000 0x3ff>;
1374 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1375 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1376 clocks = <&atl_gfclk_mux>;
1377 clock-names = "fck";
1378 status = "disabled";
1381 crossbar_mpu: crossbar@4a002a48 {
1382 compatible = "ti,irq-crossbar";
1383 reg = <0x4a002a48 0x130>;
1384 interrupt-controller;
1385 interrupt-parent = <&wakeupgen>;
1386 #interrupt-cells = <3>;
1387 ti,max-irqs = <160>;
1388 ti,max-crossbar-sources = <MAX_SOURCES>;
1390 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1391 ti,irqs-skip = <10 133 139 140>;
1392 ti,irqs-safe-map = <0>;
1395 mac: ethernet@4a100000 {
1396 compatible = "ti,cpsw";
1398 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1399 clock-names = "fck", "cpts";
1400 cpdma_channels = <8>;
1401 ale_entries = <1024>;
1402 bd_ram_size = <0x2000>;
1405 mac_control = <0x20>;
1408 cpts_clock_mult = <0x80000000>;
1409 cpts_clock_shift = <29>;
1410 reg = <0x48484000 0x1000
1412 #address-cells = <1>;
1420 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "disabled";
1427 davinci_mdio: mdio@48485000 {
1428 compatible = "ti,davinci_mdio";
1429 #address-cells = <1>;
1431 ti,hwmods = "davinci_mdio";
1432 bus_freq = <1000000>;
1433 reg = <0x48485000 0x100>;
1436 cpsw_emac0: slave@48480200 {
1437 /* Filled in by U-Boot */
1438 mac-address = [ 00 00 00 00 00 00 ];
1441 cpsw_emac1: slave@48480300 {
1442 /* Filled in by U-Boot */
1443 mac-address = [ 00 00 00 00 00 00 ];
1446 phy_sel: cpsw-phy-sel@4a002554 {
1447 compatible = "ti,dra7xx-cpsw-phy-sel";
1448 reg= <0x4a002554 0x4>;
1449 reg-names = "gmii-sel";
1453 dcan1: can@481cc000 {
1454 compatible = "ti,dra7-d_can";
1455 ti,hwmods = "dcan1";
1456 reg = <0x4ae3c000 0x2000>;
1457 syscon-raminit = <&scm_conf 0x558 0>;
1458 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&dcan1_sys_clk_mux>;
1460 status = "disabled";
1463 dcan2: can@481d0000 {
1464 compatible = "ti,dra7-d_can";
1465 ti,hwmods = "dcan2";
1466 reg = <0x48480000 0x2000>;
1467 syscon-raminit = <&scm_conf 0x558 1>;
1468 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&sys_clkin1>;
1470 status = "disabled";
1474 thermal_zones: thermal-zones {
1475 #include "omap4-cpu-thermal.dtsi"
1476 #include "omap5-gpu-thermal.dtsi"
1477 #include "omap5-core-thermal.dtsi"
1483 polling-delay = <500>; /* milliseconds */
1486 /include/ "dra7xx-clocks.dtsi"