2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
58 compatible = "arm,cortex-a15";
60 clock-frequency = <1800000000>;
61 cci-control-port = <&cci_control1>;
66 compatible = "arm,cortex-a15";
68 clock-frequency = <1800000000>;
69 cci-control-port = <&cci_control1>;
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1800000000>;
77 cci-control-port = <&cci_control1>;
82 compatible = "arm,cortex-a15";
84 clock-frequency = <1800000000>;
85 cci-control-port = <&cci_control1>;
90 compatible = "arm,cortex-a7";
92 clock-frequency = <1000000000>;
93 cci-control-port = <&cci_control0>;
98 compatible = "arm,cortex-a7";
100 clock-frequency = <1000000000>;
101 cci-control-port = <&cci_control0>;
106 compatible = "arm,cortex-a7";
108 clock-frequency = <1000000000>;
109 cci-control-port = <&cci_control0>;
114 compatible = "arm,cortex-a7";
116 clock-frequency = <1000000000>;
117 cci-control-port = <&cci_control0>;
122 compatible = "arm,cci-400";
123 #address-cells = <1>;
125 reg = <0x10d20000 0x1000>;
126 ranges = <0x0 0x10d20000 0x6000>;
128 cci_control0: slave-if@4000 {
129 compatible = "arm,cci-400-ctrl-if";
130 interface-type = "ace";
131 reg = <0x4000 0x1000>;
133 cci_control1: slave-if@5000 {
134 compatible = "arm,cci-400-ctrl-if";
135 interface-type = "ace";
136 reg = <0x5000 0x1000>;
141 compatible = "mmio-sram";
142 reg = <0x02020000 0x54000>;
143 #address-cells = <1>;
145 ranges = <0 0x02020000 0x54000>;
148 compatible = "samsung,exynos4210-sysram";
153 compatible = "samsung,exynos4210-sysram-ns";
154 reg = <0x53000 0x1000>;
158 clock: clock-controller@10010000 {
159 compatible = "samsung,exynos5420-clock";
160 reg = <0x10010000 0x30000>;
164 clock_audss: audss-clock-controller@3810000 {
165 compatible = "samsung,exynos5420-audss-clock";
166 reg = <0x03810000 0x0C>;
168 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
169 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
170 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
173 mfc: codec@11000000 {
174 compatible = "samsung,mfc-v7";
175 reg = <0x11000000 0x10000>;
176 interrupts = <0 96 0>;
177 clocks = <&clock CLK_MFC>;
181 mmc_0: mmc@12200000 {
182 compatible = "samsung,exynos5420-dw-mshc-smu";
183 interrupts = <0 75 0>;
184 #address-cells = <1>;
186 reg = <0x12200000 0x2000>;
187 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
188 clock-names = "biu", "ciu";
193 mmc_1: mmc@12210000 {
194 compatible = "samsung,exynos5420-dw-mshc-smu";
195 interrupts = <0 76 0>;
196 #address-cells = <1>;
198 reg = <0x12210000 0x2000>;
199 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
200 clock-names = "biu", "ciu";
205 mmc_2: mmc@12220000 {
206 compatible = "samsung,exynos5420-dw-mshc";
207 interrupts = <0 77 0>;
208 #address-cells = <1>;
210 reg = <0x12220000 0x1000>;
211 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
212 clock-names = "biu", "ciu";
218 compatible = "samsung,exynos4210-mct";
219 reg = <0x101C0000 0x800>;
220 interrupt-controller;
221 #interrups-cells = <1>;
222 interrupt-parent = <&mct_map>;
223 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
224 <8>, <9>, <10>, <11>;
225 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
226 clock-names = "fin_pll", "mct";
229 #interrupt-cells = <1>;
230 #address-cells = <0>;
232 interrupt-map = <0 &combiner 23 3>,
247 gsc_pd: power-domain@10044000 {
248 compatible = "samsung,exynos4210-pd";
249 reg = <0x10044000 0x20>;
252 isp_pd: power-domain@10044020 {
253 compatible = "samsung,exynos4210-pd";
254 reg = <0x10044020 0x20>;
257 mfc_pd: power-domain@10044060 {
258 compatible = "samsung,exynos4210-pd";
259 reg = <0x10044060 0x20>;
262 disp_pd: power-domain@100440C0 {
263 compatible = "samsung,exynos4210-pd";
264 reg = <0x100440C0 0x20>;
267 mau_pd: power-domain@100440E0 {
268 compatible = "samsung,exynos4210-pd";
269 reg = <0x100440E0 0x20>;
272 g2d_pd: power-domain@10044100 {
273 compatible = "samsung,exynos4210-pd";
274 reg = <0x10044100 0x20>;
277 msc_pd: power-domain@10044120 {
278 compatible = "samsung,exynos4210-pd";
279 reg = <0x10044120 0x20>;
282 pinctrl_0: pinctrl@13400000 {
283 compatible = "samsung,exynos5420-pinctrl";
284 reg = <0x13400000 0x1000>;
285 interrupts = <0 45 0>;
287 wakeup-interrupt-controller {
288 compatible = "samsung,exynos4210-wakeup-eint";
289 interrupt-parent = <&gic>;
290 interrupts = <0 32 0>;
294 pinctrl_1: pinctrl@13410000 {
295 compatible = "samsung,exynos5420-pinctrl";
296 reg = <0x13410000 0x1000>;
297 interrupts = <0 78 0>;
300 pinctrl_2: pinctrl@14000000 {
301 compatible = "samsung,exynos5420-pinctrl";
302 reg = <0x14000000 0x1000>;
303 interrupts = <0 46 0>;
306 pinctrl_3: pinctrl@14010000 {
307 compatible = "samsung,exynos5420-pinctrl";
308 reg = <0x14010000 0x1000>;
309 interrupts = <0 50 0>;
312 pinctrl_4: pinctrl@03860000 {
313 compatible = "samsung,exynos5420-pinctrl";
314 reg = <0x03860000 0x1000>;
315 interrupts = <0 47 0>;
319 clocks = <&clock CLK_RTC>;
325 #address-cells = <1>;
327 compatible = "arm,amba-bus";
328 interrupt-parent = <&gic>;
331 adma: adma@03880000 {
332 compatible = "arm,pl330", "arm,primecell";
333 reg = <0x03880000 0x1000>;
334 interrupts = <0 110 0>;
335 clocks = <&clock_audss EXYNOS_ADMA>;
336 clock-names = "apb_pclk";
339 #dma-requests = <16>;
342 pdma0: pdma@121A0000 {
343 compatible = "arm,pl330", "arm,primecell";
344 reg = <0x121A0000 0x1000>;
345 interrupts = <0 34 0>;
346 clocks = <&clock CLK_PDMA0>;
347 clock-names = "apb_pclk";
350 #dma-requests = <32>;
353 pdma1: pdma@121B0000 {
354 compatible = "arm,pl330", "arm,primecell";
355 reg = <0x121B0000 0x1000>;
356 interrupts = <0 35 0>;
357 clocks = <&clock CLK_PDMA1>;
358 clock-names = "apb_pclk";
361 #dma-requests = <32>;
364 mdma0: mdma@10800000 {
365 compatible = "arm,pl330", "arm,primecell";
366 reg = <0x10800000 0x1000>;
367 interrupts = <0 33 0>;
368 clocks = <&clock CLK_MDMA0>;
369 clock-names = "apb_pclk";
375 mdma1: mdma@11C10000 {
376 compatible = "arm,pl330", "arm,primecell";
377 reg = <0x11C10000 0x1000>;
378 interrupts = <0 124 0>;
379 clocks = <&clock CLK_MDMA1>;
380 clock-names = "apb_pclk";
388 compatible = "samsung,exynos5420-i2s";
389 reg = <0x03830000 0x100>;
393 dma-names = "tx", "rx", "tx-sec";
394 clocks = <&clock_audss EXYNOS_I2S_BUS>,
395 <&clock_audss EXYNOS_I2S_BUS>,
396 <&clock_audss EXYNOS_SCLK_I2S>;
397 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
398 samsung,idma-addr = <0x03000000>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_bus>;
405 compatible = "samsung,exynos5420-i2s";
406 reg = <0x12D60000 0x100>;
409 dma-names = "tx", "rx";
410 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
411 clock-names = "iis", "i2s_opclk0";
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2s1_bus>;
418 compatible = "samsung,exynos5420-i2s";
419 reg = <0x12D70000 0x100>;
422 dma-names = "tx", "rx";
423 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
424 clock-names = "iis", "i2s_opclk0";
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2s2_bus>;
430 spi_0: spi@12d20000 {
431 compatible = "samsung,exynos4210-spi";
432 reg = <0x12d20000 0x100>;
433 interrupts = <0 66 0>;
436 dma-names = "tx", "rx";
437 #address-cells = <1>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&spi0_bus>;
441 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
442 clock-names = "spi", "spi_busclk0";
446 spi_1: spi@12d30000 {
447 compatible = "samsung,exynos4210-spi";
448 reg = <0x12d30000 0x100>;
449 interrupts = <0 67 0>;
452 dma-names = "tx", "rx";
453 #address-cells = <1>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&spi1_bus>;
457 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
458 clock-names = "spi", "spi_busclk0";
462 spi_2: spi@12d40000 {
463 compatible = "samsung,exynos4210-spi";
464 reg = <0x12d40000 0x100>;
465 interrupts = <0 68 0>;
468 dma-names = "tx", "rx";
469 #address-cells = <1>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi2_bus>;
473 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
474 clock-names = "spi", "spi_busclk0";
478 uart_0: serial@12C00000 {
479 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
480 clock-names = "uart", "clk_uart_baud0";
483 uart_1: serial@12C10000 {
484 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
485 clock-names = "uart", "clk_uart_baud0";
488 uart_2: serial@12C20000 {
489 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
490 clock-names = "uart", "clk_uart_baud0";
493 uart_3: serial@12C30000 {
494 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
495 clock-names = "uart", "clk_uart_baud0";
499 compatible = "samsung,exynos4210-pwm";
500 reg = <0x12dd0000 0x100>;
501 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
503 clocks = <&clock CLK_PWM>;
504 clock-names = "timers";
507 dp_phy: video-phy@10040728 {
508 compatible = "samsung,exynos5250-dp-video-phy";
509 reg = <0x10040728 4>;
513 dp: dp-controller@145B0000 {
514 clocks = <&clock CLK_DP1>;
520 fimd: fimd@14400000 {
521 samsung,power-domain = <&disp_pd>;
522 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
523 clock-names = "sclk_fimd", "fimd";
527 compatible = "samsung,exynos-adc-v2";
528 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
529 interrupts = <0 106 0>;
530 clocks = <&clock CLK_TSADC>;
532 #io-channel-cells = <1>;
537 i2c_0: i2c@12C60000 {
538 compatible = "samsung,s3c2440-i2c";
539 reg = <0x12C60000 0x100>;
540 interrupts = <0 56 0>;
541 #address-cells = <1>;
543 clocks = <&clock CLK_I2C0>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c0_bus>;
550 i2c_1: i2c@12C70000 {
551 compatible = "samsung,s3c2440-i2c";
552 reg = <0x12C70000 0x100>;
553 interrupts = <0 57 0>;
554 #address-cells = <1>;
556 clocks = <&clock CLK_I2C1>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c1_bus>;
563 i2c_2: i2c@12C80000 {
564 compatible = "samsung,s3c2440-i2c";
565 reg = <0x12C80000 0x100>;
566 interrupts = <0 58 0>;
567 #address-cells = <1>;
569 clocks = <&clock CLK_I2C2>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_bus>;
576 i2c_3: i2c@12C90000 {
577 compatible = "samsung,s3c2440-i2c";
578 reg = <0x12C90000 0x100>;
579 interrupts = <0 59 0>;
580 #address-cells = <1>;
582 clocks = <&clock CLK_I2C3>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c3_bus>;
589 hsi2c_4: i2c@12CA0000 {
590 compatible = "samsung,exynos5-hsi2c";
591 reg = <0x12CA0000 0x1000>;
592 interrupts = <0 60 0>;
593 #address-cells = <1>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c4_hs_bus>;
597 clocks = <&clock CLK_USI0>;
598 clock-names = "hsi2c";
602 hsi2c_5: i2c@12CB0000 {
603 compatible = "samsung,exynos5-hsi2c";
604 reg = <0x12CB0000 0x1000>;
605 interrupts = <0 61 0>;
606 #address-cells = <1>;
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c5_hs_bus>;
610 clocks = <&clock CLK_USI1>;
611 clock-names = "hsi2c";
615 hsi2c_6: i2c@12CC0000 {
616 compatible = "samsung,exynos5-hsi2c";
617 reg = <0x12CC0000 0x1000>;
618 interrupts = <0 62 0>;
619 #address-cells = <1>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c6_hs_bus>;
623 clocks = <&clock CLK_USI2>;
624 clock-names = "hsi2c";
628 hsi2c_7: i2c@12CD0000 {
629 compatible = "samsung,exynos5-hsi2c";
630 reg = <0x12CD0000 0x1000>;
631 interrupts = <0 63 0>;
632 #address-cells = <1>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c7_hs_bus>;
636 clocks = <&clock CLK_USI3>;
637 clock-names = "hsi2c";
641 hsi2c_8: i2c@12E00000 {
642 compatible = "samsung,exynos5-hsi2c";
643 reg = <0x12E00000 0x1000>;
644 interrupts = <0 87 0>;
645 #address-cells = <1>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&i2c8_hs_bus>;
649 clocks = <&clock CLK_USI4>;
650 clock-names = "hsi2c";
654 hsi2c_9: i2c@12E10000 {
655 compatible = "samsung,exynos5-hsi2c";
656 reg = <0x12E10000 0x1000>;
657 interrupts = <0 88 0>;
658 #address-cells = <1>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&i2c9_hs_bus>;
662 clocks = <&clock CLK_USI5>;
663 clock-names = "hsi2c";
667 hsi2c_10: i2c@12E20000 {
668 compatible = "samsung,exynos5-hsi2c";
669 reg = <0x12E20000 0x1000>;
670 interrupts = <0 203 0>;
671 #address-cells = <1>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c10_hs_bus>;
675 clocks = <&clock CLK_USI6>;
676 clock-names = "hsi2c";
680 hdmi: hdmi@14530000 {
681 compatible = "samsung,exynos4212-hdmi";
682 reg = <0x14530000 0x70000>;
683 interrupts = <0 95 0>;
684 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
685 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
686 <&clock CLK_MOUT_HDMI>;
687 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
688 "sclk_hdmiphy", "mout_hdmi";
692 mixer: mixer@14450000 {
693 compatible = "samsung,exynos5420-mixer";
694 reg = <0x14450000 0x10000>;
695 interrupts = <0 94 0>;
696 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
697 clock-names = "mixer", "sclk_hdmi";
700 gsc_0: video-scaler@13e00000 {
701 compatible = "samsung,exynos5-gsc";
702 reg = <0x13e00000 0x1000>;
703 interrupts = <0 85 0>;
704 clocks = <&clock CLK_GSCL0>;
705 clock-names = "gscl";
706 samsung,power-domain = <&gsc_pd>;
709 gsc_1: video-scaler@13e10000 {
710 compatible = "samsung,exynos5-gsc";
711 reg = <0x13e10000 0x1000>;
712 interrupts = <0 86 0>;
713 clocks = <&clock CLK_GSCL1>;
714 clock-names = "gscl";
715 samsung,power-domain = <&gsc_pd>;
718 pmu_system_controller: system-controller@10040000 {
719 compatible = "samsung,exynos5420-pmu", "syscon";
720 reg = <0x10040000 0x5000>;
723 tmu_cpu0: tmu@10060000 {
724 compatible = "samsung,exynos5420-tmu";
725 reg = <0x10060000 0x100>;
726 interrupts = <0 65 0>;
727 clocks = <&clock CLK_TMU>;
728 clock-names = "tmu_apbif";
731 tmu_cpu1: tmu@10064000 {
732 compatible = "samsung,exynos5420-tmu";
733 reg = <0x10064000 0x100>;
734 interrupts = <0 183 0>;
735 clocks = <&clock CLK_TMU>;
736 clock-names = "tmu_apbif";
739 tmu_cpu2: tmu@10068000 {
740 compatible = "samsung,exynos5420-tmu-ext-triminfo";
741 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
742 interrupts = <0 184 0>;
743 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
744 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
747 tmu_cpu3: tmu@1006c000 {
748 compatible = "samsung,exynos5420-tmu-ext-triminfo";
749 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
750 interrupts = <0 185 0>;
751 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
752 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
755 tmu_gpu: tmu@100a0000 {
756 compatible = "samsung,exynos5420-tmu-ext-triminfo";
757 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
758 interrupts = <0 215 0>;
759 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
760 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
763 watchdog: watchdog@101D0000 {
764 compatible = "samsung,exynos5420-wdt";
765 reg = <0x101D0000 0x100>;
766 interrupts = <0 42 0>;
767 clocks = <&clock CLK_WDT>;
768 clock-names = "watchdog";
769 samsung,syscon-phandle = <&pmu_system_controller>;
773 compatible = "samsung,exynos4210-secss";
774 reg = <0x10830000 0x10000>;
775 interrupts = <0 112 0>;
776 clocks = <&clock 471>;
777 clock-names = "secss";
778 samsung,power-domain = <&g2d_pd>;