2 * Copyright 2011-2012 Calxeda, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
19 /* First 4KB has pen for secondary cores. */
20 /memreserve/ 0x00000000 0x0001000;
23 model = "Calxeda Highbank";
24 compatible = "calxeda,highbank";
34 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
50 compatible = "arm,cortex-a9";
52 next-level-cache = <&L2>;
58 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
68 device_type = "memory";
69 reg = <0x00000000 0xff900000>;
73 bootargs = "console=ttyAMA0";
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
84 compatible = "arm,cortex-a9-twd-timer";
85 reg = <0xfff10600 0x20>;
86 interrupts = <1 13 0xf01>;
87 clocks = <&a9periphclk>;
91 compatible = "arm,cortex-a9-twd-wdt";
92 reg = <0xfff10620 0x20>;
93 interrupts = <1 14 0xf01>;
94 clocks = <&a9periphclk>;
97 intc: interrupt-controller@fff11000 {
98 compatible = "arm,cortex-a9-gic";
99 #interrupt-cells = <3>;
101 #address-cells = <1>;
102 interrupt-controller;
103 reg = <0xfff11000 0x1000>,
108 compatible = "arm,pl310-cache";
109 reg = <0xfff12000 0x1000>;
110 interrupts = <0 70 4>;
116 compatible = "arm,cortex-a9-pmu";
117 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
121 compatible = "calxeda,hb-ahci";
122 reg = <0xffe08000 0x10000>;
123 interrupts = <0 83 4>;
124 calxeda,port-phys = <&combophy5 0 &combophy0 0
125 &combophy0 1 &combophy0 2
131 compatible = "calxeda,hb-sdhci";
132 reg = <0xffe0e000 0x1000>;
133 interrupts = <0 90 4>;
137 memory-controller@fff00000 {
138 compatible = "calxeda,hb-ddr-ctrl";
139 reg = <0xfff00000 0x1000>;
140 interrupts = <0 91 4>;
144 compatible = "arm,pl320", "arm,primecell";
145 reg = <0xfff20000 0x1000>;
146 interrupts = <0 7 4>;
148 clock-names = "apb_pclk";
151 gpioe: gpio@fff30000 {
153 compatible = "arm,pl061", "arm,primecell";
155 reg = <0xfff30000 0x1000>;
156 interrupts = <0 14 4>;
158 clock-names = "apb_pclk";
161 gpiof: gpio@fff31000 {
163 compatible = "arm,pl061", "arm,primecell";
165 reg = <0xfff31000 0x1000>;
166 interrupts = <0 15 4>;
168 clock-names = "apb_pclk";
171 gpiog: gpio@fff32000 {
173 compatible = "arm,pl061", "arm,primecell";
175 reg = <0xfff32000 0x1000>;
176 interrupts = <0 16 4>;
178 clock-names = "apb_pclk";
181 gpioh: gpio@fff33000 {
183 compatible = "arm,pl061", "arm,primecell";
185 reg = <0xfff33000 0x1000>;
186 interrupts = <0 17 4>;
188 clock-names = "apb_pclk";
192 compatible = "arm,sp804", "arm,primecell";
193 reg = <0xfff34000 0x1000>;
194 interrupts = <0 18 4>;
196 clock-names = "apb_pclk";
200 compatible = "arm,pl031", "arm,primecell";
201 reg = <0xfff35000 0x1000>;
202 interrupts = <0 19 4>;
204 clock-names = "apb_pclk";
208 compatible = "arm,pl011", "arm,primecell";
209 reg = <0xfff36000 0x1000>;
210 interrupts = <0 20 4>;
212 clock-names = "apb_pclk";
216 compatible = "ipmi-smic";
217 device_type = "ipmi";
218 reg = <0xfff3a000 0x1000>;
219 interrupts = <0 24 4>;
225 compatible = "calxeda,hb-sregs";
226 reg = <0xfff3c000 0x1000>;
229 #address-cells = <1>;
234 compatible = "fixed-clock";
235 clock-frequency = <33333000>;
240 compatible = "calxeda,hb-pll-clock";
247 compatible = "calxeda,hb-pll-clock";
252 a9periphclk: a9periphclk {
254 compatible = "calxeda,hb-a9periph-clock";
261 compatible = "calxeda,hb-a9bus-clock";
268 compatible = "calxeda,hb-pll-clock";
275 compatible = "calxeda,hb-emmc-clock";
282 compatible = "fixed-clock";
283 clock-frequency = <150000000>;
289 compatible = "calxeda,hb-sregs-l2-ecc";
290 reg = <0xfff3c200 0x100>;
291 interrupts = <0 71 4 0 72 4>;
295 compatible = "arm,pl330", "arm,primecell";
296 reg = <0xfff3d000 0x1000>;
297 interrupts = <0 92 4>;
299 clock-names = "apb_pclk";
303 compatible = "calxeda,hb-xgmac";
304 reg = <0xfff50000 0x1000>;
305 interrupts = <0 77 4 0 78 4 0 79 4>;
309 compatible = "calxeda,hb-xgmac";
310 reg = <0xfff51000 0x1000>;
311 interrupts = <0 80 4 0 81 4 0 82 4>;
314 combophy0: combo-phy@fff58000 {
315 compatible = "calxeda,hb-combophy";
317 reg = <0xfff58000 0x1000>;
321 combophy5: combo-phy@fff5d000 {
322 compatible = "calxeda,hb-combophy";
324 reg = <0xfff5d000 0x1000>;