arch/arm/boot/dts/imx6q.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         compatible = "arm,cortex-a9";
  30                         reg = <0>;
  31                         next-level-cache = <&L2>;
  32                 };
  33
  34                 cpu@1 {
  35                         compatible = "arm,cortex-a9";
  36                         reg = <1>;
  37                         next-level-cache = <&L2>;
  38                 };
  39
  40                 cpu@2 {
  41                         compatible = "arm,cortex-a9";
  42                         reg = <2>;
  43                         next-level-cache = <&L2>;
  44                 };
  45
  46                 cpu@3 {
  47                         compatible = "arm,cortex-a9";
  48                         reg = <3>;
  49                         next-level-cache = <&L2>;
  50                 };
  51         };
  52
  53         intc: interrupt-controller@00a01000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 #interrupt-cells = <3>;
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 interrupt-controller;
  59                 reg = <0x00a01000 0x1000>,
  60                       <0x00a00100 0x100>;
  61         };
  62
  63         clocks {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 ckil {
  68                         compatible = "fsl,imx-ckil", "fixed-clock";
  69                         clock-frequency = <32768>;
  70                 };
  71
  72                 ckih1 {
  73                         compatible = "fsl,imx-ckih1", "fixed-clock";
  74                         clock-frequency = <0>;
  75                 };
  76
  77                 osc {
  78                         compatible = "fsl,imx-osc", "fixed-clock";
  79                         clock-frequency = <24000000>;
  80                 };
  81         };
  82
  83         soc {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 compatible = "simple-bus";
  87                 interrupt-parent = <&intc>;
  88                 ranges;
  89
  90                 timer@00a00600 {
  91                         compatible = "arm,cortex-a9-twd-timer";
  92                         reg = <0x00a00600 0x20>;
  93                         interrupts = <1 13 0xf01>;
  94                 };
  95
  96                 L2: l2-cache@00a02000 {
  97                         compatible = "arm,pl310-cache";
  98                         reg = <0x00a02000 0x1000>;
  99                         interrupts = <0 92 0x04>;
 100                         cache-unified;
 101                         cache-level = <2>;
 102                 };
 103
 104                 aips-bus@02000000 { /* AIPS1 */
 105                         compatible = "fsl,aips-bus", "simple-bus";
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         reg = <0x02000000 0x100000>;
 109                         ranges;
 110
 111                         spba-bus@02000000 {
 112                                 compatible = "fsl,spba-bus", "simple-bus";
 113                                 #address-cells = <1>;
 114                                 #size-cells = <1>;
 115                                 reg = <0x02000000 0x40000>;
 116                                 ranges;
 117
 118                                 spdif@02004000 {
 119                                         reg = <0x02004000 0x4000>;
 120                                         interrupts = <0 52 0x04>;
 121                                 };
 122
 123                                 ecspi@02008000 { /* eCSPI1 */
 124                                         #address-cells = <1>;
 125                                         #size-cells = <0>;
 126                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 127                                         reg = <0x02008000 0x4000>;
 128                                         interrupts = <0 31 0x04>;
 129                                         status = "disabled";
 130                                 };
 131
 132                                 ecspi@0200c000 { /* eCSPI2 */
 133                                         #address-cells = <1>;
 134                                         #size-cells = <0>;
 135                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 136                                         reg = <0x0200c000 0x4000>;
 137                                         interrupts = <0 32 0x04>;
 138                                         status = "disabled";
 139                                 };
 140
 141                                 ecspi@02010000 { /* eCSPI3 */
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 145                                         reg = <0x02010000 0x4000>;
 146                                         interrupts = <0 33 0x04>;
 147                                         status = "disabled";
 148                                 };
 149
 150                                 ecspi@02014000 { /* eCSPI4 */
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x02014000 0x4000>;
 155                                         interrupts = <0 34 0x04>;
 156                                         status = "disabled";
 157                                 };
 158
 159                                 ecspi@02018000 { /* eCSPI5 */
 160                                         #address-cells = <1>;
 161                                         #size-cells = <0>;
 162                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 163                                         reg = <0x02018000 0x4000>;
 164                                         interrupts = <0 35 0x04>;
 165                                         status = "disabled";
 166                                 };
 167
 168                                 uart1: serial@02020000 {
 169                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 170                                         reg = <0x02020000 0x4000>;
 171                                         interrupts = <0 26 0x04>;
 172                                         status = "disabled";
 173                                 };
 174
 175                                 esai@02024000 {
 176                                         reg = <0x02024000 0x4000>;
 177                                         interrupts = <0 51 0x04>;
 178                                 };
 179
 180                                 ssi@02028000 { /* SSI1 */
 181                                         reg = <0x02028000 0x4000>;
 182                                         interrupts = <0 46 0x04>;
 183                                 };
 184
 185                                 ssi@0202c000 { /* SSI2 */
 186                                         reg = <0x0202c000 0x4000>;
 187                                         interrupts = <0 47 0x04>;
 188                                 };
 189
 190                                 ssi@02030000 { /* SSI3 */
 191                                         reg = <0x02030000 0x4000>;
 192                                         interrupts = <0 48 0x04>;
 193                                 };
 194
 195                                 asrc@02034000 {
 196                                         reg = <0x02034000 0x4000>;
 197                                         interrupts = <0 50 0x04>;
 198                                 };
 199
 200                                 spba@0203c000 {
 201                                         reg = <0x0203c000 0x4000>;
 202                                 };
 203                         };
 204
 205                         vpu@02040000 {
 206                                 reg = <0x02040000 0x3c000>;
 207                                 interrupts = <0 3 0x04 0 12 0x04>;
 208                         };
 209
 210                         aipstz@0207c000 { /* AIPSTZ1 */
 211                                 reg = <0x0207c000 0x4000>;
 212                         };
 213
 214                         pwm@02080000 { /* PWM1 */
 215                                 reg = <0x02080000 0x4000>;
 216                                 interrupts = <0 83 0x04>;
 217                         };
 218
 219                         pwm@02084000 { /* PWM2 */
 220                                 reg = <0x02084000 0x4000>;
 221                                 interrupts = <0 84 0x04>;
 222                         };
 223
 224                         pwm@02088000 { /* PWM3 */
 225                                 reg = <0x02088000 0x4000>;
 226                                 interrupts = <0 85 0x04>;
 227                         };
 228
 229                         pwm@0208c000 { /* PWM4 */
 230                                 reg = <0x0208c000 0x4000>;
 231                                 interrupts = <0 86 0x04>;
 232                         };
 233
 234                         flexcan@02090000 { /* CAN1 */
 235                                 reg = <0x02090000 0x4000>;
 236                                 interrupts = <0 110 0x04>;
 237                         };
 238
 239                         flexcan@02094000 { /* CAN2 */
 240                                 reg = <0x02094000 0x4000>;
 241                                 interrupts = <0 111 0x04>;
 242                         };
 243
 244                         gpt@02098000 {
 245                                 compatible = "fsl,imx6q-gpt";
 246                                 reg = <0x02098000 0x4000>;
 247                                 interrupts = <0 55 0x04>;
 248                         };
 249
 250                         gpio1: gpio@0209c000 {
 251                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 252                                 reg = <0x0209c000 0x4000>;
 253                                 interrupts = <0 66 0x04 0 67 0x04>;
 254                                 gpio-controller;
 255                                 #gpio-cells = <2>;
 256                                 interrupt-controller;
 257                                 #interrupt-cells = <1>;
 258                         };
 259
 260                         gpio2: gpio@020a0000 {
 261                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 262                                 reg = <0x020a0000 0x4000>;
 263                                 interrupts = <0 68 0x04 0 69 0x04>;
 264                                 gpio-controller;
 265                                 #gpio-cells = <2>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <1>;
 268                         };
 269
 270                         gpio3: gpio@020a4000 {
 271                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 272                                 reg = <0x020a4000 0x4000>;
 273                                 interrupts = <0 70 0x04 0 71 0x04>;
 274                                 gpio-controller;
 275                                 #gpio-cells = <2>;
 276                                 interrupt-controller;
 277                                 #interrupt-cells = <1>;
 278                         };
 279
 280                         gpio4: gpio@020a8000 {
 281                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 282                                 reg = <0x020a8000 0x4000>;
 283                                 interrupts = <0 72 0x04 0 73 0x04>;
 284                                 gpio-controller;
 285                                 #gpio-cells = <2>;
 286                                 interrupt-controller;
 287                                 #interrupt-cells = <1>;
 288                         };
 289
 290                         gpio5: gpio@020ac000 {
 291                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 292                                 reg = <0x020ac000 0x4000>;
 293                                 interrupts = <0 74 0x04 0 75 0x04>;
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 interrupt-controller;
 297                                 #interrupt-cells = <1>;
 298                         };
 299
 300                         gpio6: gpio@020b0000 {
 301                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 302                                 reg = <0x020b0000 0x4000>;
 303                                 interrupts = <0 76 0x04 0 77 0x04>;
 304                                 gpio-controller;
 305                                 #gpio-cells = <2>;
 306                                 interrupt-controller;
 307                                 #interrupt-cells = <1>;
 308                         };
 309
 310                         gpio7: gpio@020b4000 {
 311                                 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
 312                                 reg = <0x020b4000 0x4000>;
 313                                 interrupts = <0 78 0x04 0 79 0x04>;
 314                                 gpio-controller;
 315                                 #gpio-cells = <2>;
 316                                 interrupt-controller;
 317                                 #interrupt-cells = <1>;
 318                         };
 319
 320                         kpp@020b8000 {
 321                                 reg = <0x020b8000 0x4000>;
 322                                 interrupts = <0 82 0x04>;
 323                         };
 324
 325                         wdog@020bc000 { /* WDOG1 */
 326                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 327                                 reg = <0x020bc000 0x4000>;
 328                                 interrupts = <0 80 0x04>;
 329                                 status = "disabled";
 330                         };
 331
 332                         wdog@020c0000 { /* WDOG2 */
 333                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 334                                 reg = <0x020c0000 0x4000>;
 335                                 interrupts = <0 81 0x04>;
 336                                 status = "disabled";
 337                         };
 338
 339                         ccm@020c4000 {
 340                                 compatible = "fsl,imx6q-ccm";
 341                                 reg = <0x020c4000 0x4000>;
 342                                 interrupts = <0 87 0x04 0 88 0x04>;
 343                         };
 344
 345                         anatop@020c8000 {
 346                                 compatible = "fsl,imx6q-anatop";
 347                                 reg = <0x020c8000 0x1000>;
 348                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 349
 350                                 regulator-1p1@110 {
 351                                         compatible = "fsl,anatop-regulator";
 352                                         regulator-name = "vdd1p1";
 353                                         regulator-min-microvolt = <800000>;
 354                                         regulator-max-microvolt = <1375000>;
 355                                         regulator-always-on;
 356                                         anatop-reg-offset = <0x110>;
 357                                         anatop-vol-bit-shift = <8>;
 358                                         anatop-vol-bit-width = <5>;
 359                                         anatop-min-bit-val = <4>;
 360                                         anatop-min-voltage = <800000>;
 361                                         anatop-max-voltage = <1375000>;
 362                                 };
 363
 364                                 regulator-3p0@120 {
 365                                         compatible = "fsl,anatop-regulator";
 366                                         regulator-name = "vdd3p0";
 367                                         regulator-min-microvolt = <2800000>;
 368                                         regulator-max-microvolt = <3150000>;
 369                                         regulator-always-on;
 370                                         anatop-reg-offset = <0x120>;
 371                                         anatop-vol-bit-shift = <8>;
 372                                         anatop-vol-bit-width = <5>;
 373                                         anatop-min-bit-val = <0>;
 374                                         anatop-min-voltage = <2625000>;
 375                                         anatop-max-voltage = <3400000>;
 376                                 };
 377
 378                                 regulator-2p5@130 {
 379                                         compatible = "fsl,anatop-regulator";
 380                                         regulator-name = "vdd2p5";
 381                                         regulator-min-microvolt = <2000000>;
 382                                         regulator-max-microvolt = <2750000>;
 383                                         regulator-always-on;
 384                                         anatop-reg-offset = <0x130>;
 385                                         anatop-vol-bit-shift = <8>;
 386                                         anatop-vol-bit-width = <5>;
 387                                         anatop-min-bit-val = <0>;
 388                                         anatop-min-voltage = <2000000>;
 389                                         anatop-max-voltage = <2750000>;
 390                                 };
 391
 392                                 regulator-vddcore@140 {
 393                                         compatible = "fsl,anatop-regulator";
 394                                         regulator-name = "cpu";
 395                                         regulator-min-microvolt = <725000>;
 396                                         regulator-max-microvolt = <1450000>;
 397                                         regulator-always-on;
 398                                         anatop-reg-offset = <0x140>;
 399                                         anatop-vol-bit-shift = <0>;
 400                                         anatop-vol-bit-width = <5>;
 401                                         anatop-min-bit-val = <1>;
 402                                         anatop-min-voltage = <725000>;
 403                                         anatop-max-voltage = <1450000>;
 404                                 };
 405
 406                                 regulator-vddpu@140 {
 407                                         compatible = "fsl,anatop-regulator";
 408                                         regulator-name = "vddpu";
 409                                         regulator-min-microvolt = <725000>;
 410                                         regulator-max-microvolt = <1450000>;
 411                                         regulator-always-on;
 412                                         anatop-reg-offset = <0x140>;
 413                                         anatop-vol-bit-shift = <9>;
 414                                         anatop-vol-bit-width = <5>;
 415                                         anatop-min-bit-val = <1>;
 416                                         anatop-min-voltage = <725000>;
 417                                         anatop-max-voltage = <1450000>;
 418                                 };
 419
 420                                 regulator-vddsoc@140 {
 421                                         compatible = "fsl,anatop-regulator";
 422                                         regulator-name = "vddsoc";
 423                                         regulator-min-microvolt = <725000>;
 424                                         regulator-max-microvolt = <1450000>;
 425                                         regulator-always-on;
 426                                         anatop-reg-offset = <0x140>;
 427                                         anatop-vol-bit-shift = <18>;
 428                                         anatop-vol-bit-width = <5>;
 429                                         anatop-min-bit-val = <1>;
 430                                         anatop-min-voltage = <725000>;
 431                                         anatop-max-voltage = <1450000>;
 432                                 };
 433                         };
 434
 435                         usbphy@020c9000 { /* USBPHY1 */
 436                                 reg = <0x020c9000 0x1000>;
 437                                 interrupts = <0 44 0x04>;
 438                         };
 439
 440                         usbphy@020ca000 { /* USBPHY2 */
 441                                 reg = <0x020ca000 0x1000>;
 442                                 interrupts = <0 45 0x04>;
 443                         };
 444
 445                         snvs@020cc000 {
 446                                 reg = <0x020cc000 0x4000>;
 447                                 interrupts = <0 19 0x04 0 20 0x04>;
 448                         };
 449
 450                         epit@020d0000 { /* EPIT1 */
 451                                 reg = <0x020d0000 0x4000>;
 452                                 interrupts = <0 56 0x04>;
 453                         };
 454
 455                         epit@020d4000 { /* EPIT2 */
 456                                 reg = <0x020d4000 0x4000>;
 457                                 interrupts = <0 57 0x04>;
 458                         };
 459
 460                         src@020d8000 {
 461                                 compatible = "fsl,imx6q-src";
 462                                 reg = <0x020d8000 0x4000>;
 463                                 interrupts = <0 91 0x04 0 96 0x04>;
 464                         };
 465
 466                         gpc@020dc000 {
 467                                 compatible = "fsl,imx6q-gpc";
 468                                 reg = <0x020dc000 0x4000>;
 469                                 interrupts = <0 89 0x04 0 90 0x04>;
 470                         };
 471
 472                         iomuxc@020e0000 {
 473                                 compatible = "fsl,imx6q-iomuxc";
 474                                 reg = <0x020e0000 0x4000>;
 475
 476                                 /* shared pinctrl settings */
 477                                 usdhc3 {
 478                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 479                                                 fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
 480                                                             1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
 481                                                             1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
 482                                                             1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
 483                                                             1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
 484                                                             1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
 485                                                             1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
 486                                                             1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
 487                                                             1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
 488                                                             1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
 489                                         };
 490                                 };
 491
 492                                 usdhc4 {
 493                                         pinctrl_usdhc4_1: usdhc4grp-1 {
 494                                                 fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
 495                                                             1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
 496                                                             1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
 497                                                             1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
 498                                                             1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
 499                                                             1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
 500                                                             1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
 501                                                             1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
 502                                                             1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
 503                                                             1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
 504                                         };
 505                                 };
 506                         };
 507
 508                         dcic@020e4000 { /* DCIC1 */
 509                                 reg = <0x020e4000 0x4000>;
 510                                 interrupts = <0 124 0x04>;
 511                         };
 512
 513                         dcic@020e8000 { /* DCIC2 */
 514                                 reg = <0x020e8000 0x4000>;
 515                                 interrupts = <0 125 0x04>;
 516                         };
 517
 518                         sdma@020ec000 {
 519                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 520                                 reg = <0x020ec000 0x4000>;
 521                                 interrupts = <0 2 0x04>;
 522                         };
 523                 };
 524
 525                 aips-bus@02100000 { /* AIPS2 */
 526                         compatible = "fsl,aips-bus", "simple-bus";
 527                         #address-cells = <1>;
 528                         #size-cells = <1>;
 529                         reg = <0x02100000 0x100000>;
 530                         ranges;
 531
 532                         caam@02100000 {
 533                                 reg = <0x02100000 0x40000>;
 534                                 interrupts = <0 105 0x04 0 106 0x04>;
 535                         };
 536
 537                         aipstz@0217c000 { /* AIPSTZ2 */
 538                                 reg = <0x0217c000 0x4000>;
 539                         };
 540
 541                         ethernet@02188000 {
 542                                 compatible = "fsl,imx6q-fec";
 543                                 reg = <0x02188000 0x4000>;
 544                                 interrupts = <0 118 0x04 0 119 0x04>;
 545                                 status = "disabled";
 546                         };
 547
 548                         mlb@0218c000 {
 549                                 reg = <0x0218c000 0x4000>;
 550                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 551                         };
 552
 553                         usdhc@02190000 { /* uSDHC1 */
 554                                 compatible = "fsl,imx6q-usdhc";
 555                                 reg = <0x02190000 0x4000>;
 556                                 interrupts = <0 22 0x04>;
 557                                 status = "disabled";
 558                         };
 559
 560                         usdhc@02194000 { /* uSDHC2 */
 561                                 compatible = "fsl,imx6q-usdhc";
 562                                 reg = <0x02194000 0x4000>;
 563                                 interrupts = <0 23 0x04>;
 564                                 status = "disabled";
 565                         };
 566
 567                         usdhc@02198000 { /* uSDHC3 */
 568                                 compatible = "fsl,imx6q-usdhc";
 569                                 reg = <0x02198000 0x4000>;
 570                                 interrupts = <0 24 0x04>;
 571                                 status = "disabled";
 572                         };
 573
 574                         usdhc@0219c000 { /* uSDHC4 */
 575                                 compatible = "fsl,imx6q-usdhc";
 576                                 reg = <0x0219c000 0x4000>;
 577                                 interrupts = <0 25 0x04>;
 578                                 status = "disabled";
 579                         };
 580
 581                         i2c@021a0000 { /* I2C1 */
 582                                 #address-cells = <1>;
 583                                 #size-cells = <0>;
 584                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 585                                 reg = <0x021a0000 0x4000>;
 586                                 interrupts = <0 36 0x04>;
 587                                 status = "disabled";
 588                         };
 589
 590                         i2c@021a4000 { /* I2C2 */
 591                                 #address-cells = <1>;
 592                                 #size-cells = <0>;
 593                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 594                                 reg = <0x021a4000 0x4000>;
 595                                 interrupts = <0 37 0x04>;
 596                                 status = "disabled";
 597                         };
 598
 599                         i2c@021a8000 { /* I2C3 */
 600                                 #address-cells = <1>;
 601                                 #size-cells = <0>;
 602                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
 603                                 reg = <0x021a8000 0x4000>;
 604                                 interrupts = <0 38 0x04>;
 605                                 status = "disabled";
 606                         };
 607
 608                         romcp@021ac000 {
 609                                 reg = <0x021ac000 0x4000>;
 610                         };
 611
 612                         mmdc@021b0000 { /* MMDC0 */
 613                                 compatible = "fsl,imx6q-mmdc";
 614                                 reg = <0x021b0000 0x4000>;
 615                         };
 616
 617                         mmdc@021b4000 { /* MMDC1 */
 618                                 reg = <0x021b4000 0x4000>;
 619                         };
 620
 621                         weim@021b8000 {
 622                                 reg = <0x021b8000 0x4000>;
 623                                 interrupts = <0 14 0x04>;
 624                         };
 625
 626                         ocotp@021bc000 {
 627                                 reg = <0x021bc000 0x4000>;
 628                         };
 629
 630                         ocotp@021c0000 {
 631                                 reg = <0x021c0000 0x4000>;
 632                                 interrupts = <0 21 0x04>;
 633                         };
 634
 635                         tzasc@021d0000 { /* TZASC1 */
 636                                 reg = <0x021d0000 0x4000>;
 637                                 interrupts = <0 108 0x04>;
 638                         };
 639
 640                         tzasc@021d4000 { /* TZASC2 */
 641                                 reg = <0x021d4000 0x4000>;
 642                                 interrupts = <0 109 0x04>;
 643                         };
 644
 645                         audmux@021d8000 {
 646                                 reg = <0x021d8000 0x4000>;
 647                         };
 648
 649                         mipi@021dc000 { /* MIPI-CSI */
 650                                 reg = <0x021dc000 0x4000>;
 651                         };
 652
 653                         mipi@021e0000 { /* MIPI-DSI */
 654                                 reg = <0x021e0000 0x4000>;
 655                         };
 656
 657                         vdoa@021e4000 {
 658                                 reg = <0x021e4000 0x4000>;
 659                                 interrupts = <0 18 0x04>;
 660                         };
 661
 662                         uart2: serial@021e8000 {
 663                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 664                                 reg = <0x021e8000 0x4000>;
 665                                 interrupts = <0 27 0x04>;
 666                                 status = "disabled";
 667                         };
 668
 669                         uart3: serial@021ec000 {
 670                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 671                                 reg = <0x021ec000 0x4000>;
 672                                 interrupts = <0 28 0x04>;
 673                                 status = "disabled";
 674                         };
 675
 676                         uart4: serial@021f0000 {
 677                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 678                                 reg = <0x021f0000 0x4000>;
 679                                 interrupts = <0 29 0x04>;
 680                                 status = "disabled";
 681                         };
 682
 683                         uart5: serial@021f4000 {
 684                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 685                                 reg = <0x021f4000 0x4000>;
 686                                 interrupts = <0 30 0x04>;
 687                                 status = "disabled";
 688                         };
 689                 };
 690         };
 691 };