arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 / {
  14         memory {
  15                 reg = <0x10000000 0x80000000>;
  16         };
  17
  18         sound-spdif {
  19                 compatible = "fsl,imx-audio-spdif",
  20                            "fsl,imx-sabreauto-spdif";
  21                 model = "imx-spdif";
  22                 spdif-controller = <&spdif>;
  23                 spdif-in;
  24         };
  25
  26         sound-hdmi {
  27                 compatible = "fsl,imx6q-audio-hdmi",
  28                              "fsl,imx-audio-hdmi";
  29                 model = "imx-audio-hdmi";
  30                 hdmi-controller = <&hdmi_audio>;
  31         };
  32
  33         max7310_reset: max7310-reset {
  34                 compatible = "gpio-reset";
  35                 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  36                 reset-delay-us = <1>;
  37                 #reset-cells = <0>;
  38         };
  39 };
  40
  41 &ecspi1 {
  42         fsl,spi-num-chipselects = <1>;
  43         cs-gpios = <&gpio3 19 0>;
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  46         status = "disabled"; /* pin conflict with WEIM NOR */
  47
  48         flash: m25p80@0 {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 compatible = "st,m25p32";
  52                 spi-max-frequency = <20000000>;
  53                 reg = <0>;
  54         };
  55 };
  56
  57 &fec {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_enet>;
  60         phy-mode = "rgmii";
  61         status = "okay";
  62 };
  63
  64 &gpmi {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_gpmi_nand>;
  67         status = "okay";
  68 };
  69
  70 &i2c2 {
  71         clock-frequency = <100000>;
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_i2c2>;
  74         status = "okay";
  75
  76         hdmi: edid@50 {
  77                 compatible = "fsl,imx6-hdmi-i2c";
  78                 reg = <0x50>;
  79         };
  80 };
  81
  82 &i2c3 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_i2c3>;
  85         pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  86         status = "okay";
  87
  88         max7310_a: gpio@30 {
  89                 compatible = "maxim,max7310";
  90                 reg = <0x30>;
  91                 gpio-controller;
  92                 #gpio-cells = <2>;
  93                 resets = <&max7310_reset>;
  94         };
  95
  96         max7310_b: gpio@32 {
  97                 compatible = "maxim,max7310";
  98                 reg = <0x32>;
  99                 gpio-controller;
 100                 #gpio-cells = <2>;
 101         };
 102
 103         max7310_c: gpio@34 {
 104                 compatible = "maxim,max7310";
 105                 reg = <0x34>;
 106                 gpio-controller;
 107                 #gpio-cells = <2>;
 108         };
 109 };
 110
 111 &iomuxc {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_hog>;
 114
 115         imx6qdl-sabreauto {
 116                 pinctrl_hog: hoggrp {
 117                         fsl,pins = <
 118                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 119                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 120                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 121                                 MX6QDL_PAD_EIM_A24__GPIO5_IO04   0x80000000
 122                                 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  0x80000000
 123                         >;
 124                 };
 125
 126                 pinctrl_ecspi1: ecspi1grp {
 127                         fsl,pins = <
 128                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 129                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 130                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 131                         >;
 132                 };
 133
 134                 pinctrl_ecspi1_cs: ecspi1cs {
 135                         fsl,pins = <
 136                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 137                         >;
 138                 };
 139
 140                 pinctrl_enet: enetgrp {
 141                         fsl,pins = <
 142                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 143                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 144                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 145                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 146                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 147                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 148                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 149                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 150                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 151                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 152                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 153                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 154                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 155                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 156                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 157                         >;
 158                 };
 159
 160                 pinctrl_gpmi_nand: gpminandgrp {
 161                         fsl,pins = <
 162                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 163                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 164                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 165                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 166                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 167                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 168                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 169                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 170                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 171                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 172                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 173                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 174                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 175                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 176                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 177                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 178                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 179                         >;
 180                 };
 181
 182                 pinctrl_i2c2: i2c2grp {
 183                         fsl,pins = <
 184                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 185                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 186                         >;
 187                 };
 188
 189                 pinctrl_i2c3: i2c3grp {
 190                         fsl,pins = <
 191                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 192                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 193                         >;
 194                 };
 195
 196                 pinctrl_spdif: spdifgrp {
 197                         fsl,pins = <
 198                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 199                         >;
 200                 };
 201
 202                 pinctrl_uart4: uart4grp {
 203                         fsl,pins = <
 204                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 205                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 206                         >;
 207                 };
 208
 209                 pinctrl_usdhc3: usdhc3grp {
 210                         fsl,pins = <
 211                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 212                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 213                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 214                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 215                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 216                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 217                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 218                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 219                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 220                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 221                         >;
 222                 };
 223
 224                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 225                         fsl,pins = <
 226                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 227                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 228                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 229                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 230                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 231                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 232                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 233                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 234                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 235                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 236                         >;
 237                 };
 238
 239                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 240                         fsl,pins = <
 241                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 242                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 243                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 244                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 245                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 246                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 247                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 248                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 249                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 250                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 251                         >;
 252                 };
 253
 254                 pinctrl_weim_cs0: weimcs0grp {
 255                         fsl,pins = <
 256                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 257                         >;
 258                 };
 259
 260                 pinctrl_weim_nor: weimnorgrp {
 261                         fsl,pins = <
 262                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 263                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 264                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 265                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 266                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 267                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 268                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 269                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 270                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 271                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 272                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 273                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 274                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 275                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 276                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 277                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 278                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 279                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 280                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 281                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 282                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 283                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 284                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 285                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 286                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 287                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 288                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 289                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 290                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 291                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 292                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 293                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 294                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 295                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 296                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 297                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 298                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 299                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 300                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 301                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 302                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 303                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 304                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 305                         >;
 306                 };
 307
 308                 pinctrl_hdmi_cec: hdmicecgrp {
 309                         fsl,pins = <
 310                                 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
 311                         >;
 312                 };
 313         };
 314 };
 315
 316 &spdif {
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_spdif>;
 319         status = "okay";
 320 };
 321
 322 &uart4 {
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_uart4>;
 325         status = "okay";
 326 };
 327
 328 &usdhc3 {
 329         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 330         pinctrl-0 = <&pinctrl_usdhc3>;
 331         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 332         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 333         cd-gpios = <&gpio6 15 0>;
 334         wp-gpios = <&gpio1 13 0>;
 335         status = "okay";
 336 };
 337
 338 &weim {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 341         #address-cells = <2>;
 342         #size-cells = <1>;
 343         ranges = <0 0 0x08000000 0x08000000>;
 344         status = "disabled"; /* pin conflict with SPI NOR */
 345
 346         nor@0,0 {
 347                 compatible = "cfi-flash";
 348                 reg = <0 0 0x02000000>;
 349                 #address-cells = <1>;
 350                 #size-cells = <1>;
 351                 bank-width = <2>;
 352                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 353                                 0x0000c000 0x1404a38e 0x00000000>;
 354         };
 355 };
 356
 357 &hdmi_audio {
 358         status = "okay";
 359 };
 360
 361 &hdmi_cec {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_hdmi_cec>;
 364         status = "okay";
 365 };
 366
 367 &hdmi_core {
 368         ipu_id = <0>;
 369         disp_id = <0>;
 370         status = "okay";
 371 };
 372
 373 &hdmi_video {
 374         fsl,phy_reg_vlev = <0x0294>;
 375         fsl,phy_reg_cksymtx = <0x800d>;
 376         status = "okay";
 377 };