2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/pwm/pwm.h>
22 lcdif_23bit_pins_a = &pinctrl_disp0_1;
23 lcdif_24bit_pins_a = &pinctrl_disp0_2;
26 reg_can_xcvr = ®_can_xcvr;
34 reg = <0 0>; /* will be filled by U-Boot */
41 compatible = "fixed-clock";
44 clock-frequency = <27000000>;
49 compatible = "gpio-keys";
52 label = "Power Button";
53 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_POWER>;
60 compatible = "gpio-leds";
64 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
70 compatible = "simple-bus";
74 reg_3v3_etn: regulator@0 {
75 compatible = "regulator-fixed";
77 regulator-name = "3V3_ETN";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_etnphy_power>;
82 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
86 reg_2v5: regulator@1 {
87 compatible = "regulator-fixed";
89 regulator-name = "2V5";
90 regulator-min-microvolt = <2500000>;
91 regulator-max-microvolt = <2500000>;
95 reg_3v3: regulator@2 {
96 compatible = "regulator-fixed";
98 regulator-name = "3V3";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
104 reg_can_xcvr: regulator@3 {
105 compatible = "regulator-fixed";
107 regulator-name = "CAN XCVR";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
112 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
116 reg_lcd0_pwr: regulator@4 {
117 compatible = "regulator-fixed";
119 regulator-name = "LCD0 POWER";
120 regulator-min-microvolt = <3300000>;
121 regulator-max-microvolt = <3300000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_lcd0_pwr>;
124 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
130 reg_lcd1_pwr: regulator@5 {
131 compatible = "regulator-fixed";
133 regulator-name = "LCD1 POWER";
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_lcd1_pwr>;
138 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
144 reg_usbh1_vbus: regulator@6 {
145 compatible = "regulator-fixed";
147 regulator-name = "usbh1_vbus";
148 regulator-min-microvolt = <5000000>;
149 regulator-max-microvolt = <5000000>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_usbh1_vbus>;
152 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
156 reg_usbotg_vbus: regulator@7 {
157 compatible = "regulator-fixed";
159 regulator-name = "usbotg_vbus";
160 regulator-min-microvolt = <5000000>;
161 regulator-max-microvolt = <5000000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_usbotg_vbus>;
164 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
170 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
171 "fsl,imx-audio-sgtl5000";
172 model = "sgtl5000-audio";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_audmux>;
175 ssi-controller = <&ssi1>;
176 audio-codec = <&sgtl5000>;
178 "MIC_IN", "Mic Jack",
179 "Mic Jack", "Mic Bias",
180 "Headphone Jack", "HP_OUT";
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_flexcan1>;
193 xceiver-supply = <®_can_xcvr>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_flexcan2>;
200 xceiver-supply = <®_can_xcvr>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_ecspi1>;
207 fsl,spi-num-chipselects = <2>;
209 &gpio2 30 GPIO_ACTIVE_HIGH
210 &gpio3 19 GPIO_ACTIVE_HIGH
215 compatible = "spidev";
217 spi-max-frequency = <54000000>;
221 compatible = "spidev";
223 spi-max-frequency = <54000000>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_enet>;
231 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
232 phy-handle = <&etnphy>;
233 phy-supply = <®_3v3_etn>;
237 #address-cells = <1>;
240 etnphy: ethernet-phy@0 {
241 compatible = "ethernet-phy-ieee802.3-c22";
243 interrupt-parent = <&gpio2>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_gpmi_nand>;
254 fsl,no-blockmark-swap;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_i2c1>;
261 clock-frequency = <400000>;
265 compatible = "dallas,ds1339";
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_i2c3>;
273 clock-frequency = <400000>;
276 sgtl5000: sgtl5000@0a {
277 compatible = "fsl,sgtl5000";
279 VDDA-supply = <®_2v5>;
280 VDDIO-supply = <®_3v3>;
284 polytouch: edt-ft5x06@38 {
285 compatible = "edt,edt-ft5x06";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_edt_ft5x06>;
289 interrupt-parent = <&gpio6>;
290 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
291 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
292 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
296 touchscreen: tsc2007@48 {
297 compatible = "ti,tsc2007";
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_tsc2007>;
301 interrupt-parent = <&gpio3>;
303 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
304 ti,x-plate-ohms = <660>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_hog>;
314 pinctrl_hog: hoggrp {
316 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
317 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
318 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
319 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
323 pinctrl_audmux: audmuxgrp {
325 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
326 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
327 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
328 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
332 pinctrl_disp0_1: disp0grp-1 {
334 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
335 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
336 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
337 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
338 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
339 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
340 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
341 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
342 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
343 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
344 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
345 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
346 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
347 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
348 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
349 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
350 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
351 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
352 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
353 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
354 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
355 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
356 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
357 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
358 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
359 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
360 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
361 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
365 pinctrl_disp0_2: disp0grp-2 {
367 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
368 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
369 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
370 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
371 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
372 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
373 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
374 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
375 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
376 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
377 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
378 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
379 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
380 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
381 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
382 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
383 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
384 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
385 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
386 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
387 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
388 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
389 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
390 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
391 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
392 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
393 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
394 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
398 pinctrl_ecspi1: ecspi1grp {
400 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
401 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
402 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
403 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
404 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
405 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
409 pinctrl_edt_ft5x06: edt-ft5x06grp {
411 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
412 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
413 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
417 pinctrl_enet: enetgrp {
419 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
420 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
421 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
422 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
423 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
424 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
425 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
426 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
427 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
431 pinctrl_etnphy_power: etnphy-pwrgrp {
433 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
437 pinctrl_flexcan1: flexcan1grp {
439 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
440 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
444 pinctrl_flexcan2: flexcan2grp {
446 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
447 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
451 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
453 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
457 pinctrl_gpmi_nand: gpminandgrp {
459 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
460 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
461 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
462 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
463 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
464 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
465 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
466 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
467 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
468 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
469 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
470 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
471 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
472 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
473 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
477 pinctrl_i2c1: i2c1grp {
479 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
480 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
484 pinctrl_i2c3: i2c3grp {
486 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
487 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
491 pinctrl_kpp: kppgrp {
493 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
494 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
495 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
496 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
497 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
498 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
499 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
500 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
504 pinctrl_lcd0_pwr: lcd0-pwrgrp {
506 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
510 pinctrl_lcd1_pwr: lcd1-pwrgrp {
512 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
516 pinctrl_pwm1: pwm1grp {
518 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
522 pinctrl_pwm2: pwm2grp {
524 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
528 pinctrl_tsc2007: tsc2007grp {
530 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
534 pinctrl_uart1: uart1grp {
536 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
537 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
541 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
543 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
544 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
548 pinctrl_uart2: uart2grp {
550 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
551 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
555 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
557 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
558 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
562 pinctrl_uart3: uart3grp {
564 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
565 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
569 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
571 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
572 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
576 pinctrl_usbh1_vbus: usbh1-vbusgrp {
578 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
582 pinctrl_usbotg: usbotggrp {
584 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
588 pinctrl_usbotg_vbus: usbotg-vbusgrp {
590 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
594 pinctrl_usdhc1: usdhc1grp {
596 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
597 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
598 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
599 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
600 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
601 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
602 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
606 pinctrl_usdhc2: usdhc2grp {
608 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
609 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
610 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
611 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
612 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
613 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
614 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_kpp>;
624 /* row/col 0,1 are mapped to KPP row/col 6,7 */
626 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
627 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
628 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
629 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
630 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
631 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
632 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
633 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
634 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
635 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
636 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_pwm1>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&pinctrl_pwm2>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pinctrl_uart1>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
678 vbus-supply = <®_usbh1_vbus>;
680 disable-over-current;
685 vbus-supply = <®_usbotg_vbus>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_usbotg>;
688 dr_mode = "peripheral";
689 disable-over-current;
694 pinctrl-names = "default";
695 pinctrl-0 = <&pinctrl_usdhc1>;
698 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&pinctrl_usdhc2>;
708 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;