arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 gpio5 = &gpio6;
  23                 gpio6 = &gpio7;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36         };
  37
  38         intc: interrupt-controller@00a01000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 interrupt-controller;
  44                 reg = <0x00a01000 0x1000>,
  45                       <0x00a00100 0x100>;
  46         };
  47
  48         clocks {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56
  57                 ckih1 {
  58                         compatible = "fsl,imx-ckih1", "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 osc {
  63                         compatible = "fsl,imx-osc", "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&intc>;
  73                 ranges;
  74
  75                 dma_apbh: dma-apbh@00110000 {
  76                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  77                         reg = <0x00110000 0x2000>;
  78                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  82                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  83                         #dma-cells = <1>;
  84                         dma-channels = <4>;
  85                         clocks = <&clks 106>;
  86                 };
  87
  88                 gpmi: gpmi-nand@00112000 {
  89                         compatible = "fsl,imx6q-gpmi-nand";
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  93                         reg-names = "gpmi-nand", "bch";
  94                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
  95                         interrupt-names = "bch";
  96                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  97                                  <&clks 150>, <&clks 149>;
  98                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  99                                       "gpmi_bch_apb", "per1_bch";
 100                         dmas = <&dma_apbh 0>;
 101                         dma-names = "rx-tx";
 102                         status = "disabled";
 103                 };
 104
 105                 timer@00a00600 {
 106                         compatible = "arm,cortex-a9-twd-timer";
 107                         reg = <0x00a00600 0x20>;
 108                         interrupts = <1 13 0xf01>;
 109                         clocks = <&clks 15>;
 110                 };
 111
 112                 L2: l2-cache@00a02000 {
 113                         compatible = "arm,pl310-cache";
 114                         reg = <0x00a02000 0x1000>;
 115                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 116                         cache-unified;
 117                         cache-level = <2>;
 118                         arm,tag-latency = <4 2 3>;
 119                         arm,data-latency = <4 2 3>;
 120                 };
 121
 122                 pcie: pcie@0x01000000 {
 123                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 124                         reg = <0x01ffc000 0x4000>; /* DBI */
 125                         #address-cells = <3>;
 126                         #size-cells = <2>;
 127                         device_type = "pci";
 128                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 129                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 130                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 131                         num-lanes = <1>;
 132                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
 134                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 135                         status = "disabled";
 136                 };
 137
 138                 pmu {
 139                         compatible = "arm,cortex-a9-pmu";
 140                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 141                 };
 142
 143                 aips-bus@02000000 { /* AIPS1 */
 144                         compatible = "fsl,aips-bus", "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         reg = <0x02000000 0x100000>;
 148                         ranges;
 149
 150                         spba-bus@02000000 {
 151                                 compatible = "fsl,spba-bus", "simple-bus";
 152                                 #address-cells = <1>;
 153                                 #size-cells = <1>;
 154                                 reg = <0x02000000 0x40000>;
 155                                 ranges;
 156
 157                                 spdif: spdif@02004000 {
 158                                         compatible = "fsl,imx35-spdif";
 159                                         reg = <0x02004000 0x4000>;
 160                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 161                                         dmas = <&sdma 14 18 0>,
 162                                                <&sdma 15 18 0>;
 163                                         dma-names = "rx", "tx";
 164                                         clocks = <&clks 197>, <&clks 3>,
 165                                                  <&clks 197>, <&clks 107>,
 166                                                  <&clks 0>,   <&clks 118>,
 167                                                  <&clks 0>,  <&clks 139>,
 168                                                  <&clks 0>;
 169                                         clock-names = "core",  "rxtx0",
 170                                                       "rxtx1", "rxtx2",
 171                                                       "rxtx3", "rxtx4",
 172                                                       "rxtx5", "rxtx6",
 173                                                       "rxtx7";
 174                                         status = "disabled";
 175                                 };
 176
 177                                 ecspi1: ecspi@02008000 {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 181                                         reg = <0x02008000 0x4000>;
 182                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 183                                         clocks = <&clks 112>, <&clks 112>;
 184                                         clock-names = "ipg", "per";
 185                                         status = "disabled";
 186                                 };
 187
 188                                 ecspi2: ecspi@0200c000 {
 189                                         #address-cells = <1>;
 190                                         #size-cells = <0>;
 191                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 192                                         reg = <0x0200c000 0x4000>;
 193                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 194                                         clocks = <&clks 113>, <&clks 113>;
 195                                         clock-names = "ipg", "per";
 196                                         status = "disabled";
 197                                 };
 198
 199                                 ecspi3: ecspi@02010000 {
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 203                                         reg = <0x02010000 0x4000>;
 204                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 205                                         clocks = <&clks 114>, <&clks 114>;
 206                                         clock-names = "ipg", "per";
 207                                         status = "disabled";
 208                                 };
 209
 210                                 ecspi4: ecspi@02014000 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 214                                         reg = <0x02014000 0x4000>;
 215                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 216                                         clocks = <&clks 115>, <&clks 115>;
 217                                         clock-names = "ipg", "per";
 218                                         status = "disabled";
 219                                 };
 220
 221                                 uart1: serial@02020000 {
 222                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 223                                         reg = <0x02020000 0x4000>;
 224                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 225                                         clocks = <&clks 160>, <&clks 161>;
 226                                         clock-names = "ipg", "per";
 227                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 228                                         dma-names = "rx", "tx";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 esai: esai@02024000 {
 233                                         reg = <0x02024000 0x4000>;
 234                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 235                                 };
 236
 237                                 ssi1: ssi@02028000 {
 238                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 239                                         reg = <0x02028000 0x4000>;
 240                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks 178>;
 242                                         dmas = <&sdma 37 1 0>,
 243                                                <&sdma 38 1 0>;
 244                                         dma-names = "rx", "tx";
 245                                         fsl,fifo-depth = <15>;
 246                                         fsl,ssi-dma-events = <38 37>;
 247                                         status = "disabled";
 248                                 };
 249
 250                                 ssi2: ssi@0202c000 {
 251                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 252                                         reg = <0x0202c000 0x4000>;
 253                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks 179>;
 255                                         dmas = <&sdma 41 1 0>,
 256                                                <&sdma 42 1 0>;
 257                                         dma-names = "rx", "tx";
 258                                         fsl,fifo-depth = <15>;
 259                                         fsl,ssi-dma-events = <42 41>;
 260                                         status = "disabled";
 261                                 };
 262
 263                                 ssi3: ssi@02030000 {
 264                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 265                                         reg = <0x02030000 0x4000>;
 266                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 267                                         clocks = <&clks 180>;
 268                                         dmas = <&sdma 45 1 0>,
 269                                                <&sdma 46 1 0>;
 270                                         dma-names = "rx", "tx";
 271                                         fsl,fifo-depth = <15>;
 272                                         fsl,ssi-dma-events = <46 45>;
 273                                         status = "disabled";
 274                                 };
 275
 276                                 asrc: asrc@02034000 {
 277                                         reg = <0x02034000 0x4000>;
 278                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 279                                 };
 280
 281                                 spba@0203c000 {
 282                                         reg = <0x0203c000 0x4000>;
 283                                 };
 284                         };
 285
 286                         vpu: vpu@02040000 {
 287                                 reg = <0x02040000 0x3c000>;
 288                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 289                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 290                         };
 291
 292                         aipstz@0207c000 { /* AIPSTZ1 */
 293                                 reg = <0x0207c000 0x4000>;
 294                         };
 295
 296                         pwm1: pwm@02080000 {
 297                                 #pwm-cells = <2>;
 298                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 299                                 reg = <0x02080000 0x4000>;
 300                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 301                                 clocks = <&clks 62>, <&clks 145>;
 302                                 clock-names = "ipg", "per";
 303                         };
 304
 305                         pwm2: pwm@02084000 {
 306                                 #pwm-cells = <2>;
 307                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 308                                 reg = <0x02084000 0x4000>;
 309                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 310                                 clocks = <&clks 62>, <&clks 146>;
 311                                 clock-names = "ipg", "per";
 312                         };
 313
 314                         pwm3: pwm@02088000 {
 315                                 #pwm-cells = <2>;
 316                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 317                                 reg = <0x02088000 0x4000>;
 318                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 319                                 clocks = <&clks 62>, <&clks 147>;
 320                                 clock-names = "ipg", "per";
 321                         };
 322
 323                         pwm4: pwm@0208c000 {
 324                                 #pwm-cells = <2>;
 325                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 326                                 reg = <0x0208c000 0x4000>;
 327                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clks 62>, <&clks 148>;
 329                                 clock-names = "ipg", "per";
 330                         };
 331
 332                         can1: flexcan@02090000 {
 333                                 compatible = "fsl,imx6q-flexcan";
 334                                 reg = <0x02090000 0x4000>;
 335                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&clks 108>, <&clks 109>;
 337                                 clock-names = "ipg", "per";
 338                                 status = "disabled";
 339                         };
 340
 341                         can2: flexcan@02094000 {
 342                                 compatible = "fsl,imx6q-flexcan";
 343                                 reg = <0x02094000 0x4000>;
 344                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clks 110>, <&clks 111>;
 346                                 clock-names = "ipg", "per";
 347                                 status = "disabled";
 348                         };
 349
 350                         gpt: gpt@02098000 {
 351                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 352                                 reg = <0x02098000 0x4000>;
 353                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 354                                 clocks = <&clks 119>, <&clks 120>;
 355                                 clock-names = "ipg", "per";
 356                         };
 357
 358                         gpio1: gpio@0209c000 {
 359                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 360                                 reg = <0x0209c000 0x4000>;
 361                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 362                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 363                                 gpio-controller;
 364                                 #gpio-cells = <2>;
 365                                 interrupt-controller;
 366                                 #interrupt-cells = <2>;
 367                         };
 368
 369                         gpio2: gpio@020a0000 {
 370                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 371                                 reg = <0x020a0000 0x4000>;
 372                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 373                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                         };
 379
 380                         gpio3: gpio@020a4000 {
 381                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 382                                 reg = <0x020a4000 0x4000>;
 383                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 384                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 385                                 gpio-controller;
 386                                 #gpio-cells = <2>;
 387                                 interrupt-controller;
 388                                 #interrupt-cells = <2>;
 389                         };
 390
 391                         gpio4: gpio@020a8000 {
 392                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 393                                 reg = <0x020a8000 0x4000>;
 394                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 395                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 396                                 gpio-controller;
 397                                 #gpio-cells = <2>;
 398                                 interrupt-controller;
 399                                 #interrupt-cells = <2>;
 400                         };
 401
 402                         gpio5: gpio@020ac000 {
 403                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 404                                 reg = <0x020ac000 0x4000>;
 405                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 406                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 407                                 gpio-controller;
 408                                 #gpio-cells = <2>;
 409                                 interrupt-controller;
 410                                 #interrupt-cells = <2>;
 411                         };
 412
 413                         gpio6: gpio@020b0000 {
 414                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 415                                 reg = <0x020b0000 0x4000>;
 416                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 418                                 gpio-controller;
 419                                 #gpio-cells = <2>;
 420                                 interrupt-controller;
 421                                 #interrupt-cells = <2>;
 422                         };
 423
 424                         gpio7: gpio@020b4000 {
 425                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 426                                 reg = <0x020b4000 0x4000>;
 427                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 429                                 gpio-controller;
 430                                 #gpio-cells = <2>;
 431                                 interrupt-controller;
 432                                 #interrupt-cells = <2>;
 433                         };
 434
 435                         kpp: kpp@020b8000 {
 436                                 reg = <0x020b8000 0x4000>;
 437                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 438                         };
 439
 440                         wdog1: wdog@020bc000 {
 441                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 442                                 reg = <0x020bc000 0x4000>;
 443                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 444                                 clocks = <&clks 0>;
 445                         };
 446
 447                         wdog2: wdog@020c0000 {
 448                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 449                                 reg = <0x020c0000 0x4000>;
 450                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 451                                 clocks = <&clks 0>;
 452                                 status = "disabled";
 453                         };
 454
 455                         clks: ccm@020c4000 {
 456                                 compatible = "fsl,imx6q-ccm";
 457                                 reg = <0x020c4000 0x4000>;
 458                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 460                                 #clock-cells = <1>;
 461                         };
 462
 463                         anatop: anatop@020c8000 {
 464                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 465                                 reg = <0x020c8000 0x1000>;
 466                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 468                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 469
 470                                 regulator-1p1@110 {
 471                                         compatible = "fsl,anatop-regulator";
 472                                         regulator-name = "vdd1p1";
 473                                         regulator-min-microvolt = <800000>;
 474                                         regulator-max-microvolt = <1375000>;
 475                                         regulator-always-on;
 476                                         anatop-reg-offset = <0x110>;
 477                                         anatop-vol-bit-shift = <8>;
 478                                         anatop-vol-bit-width = <5>;
 479                                         anatop-min-bit-val = <4>;
 480                                         anatop-min-voltage = <800000>;
 481                                         anatop-max-voltage = <1375000>;
 482                                 };
 483
 484                                 regulator-3p0@120 {
 485                                         compatible = "fsl,anatop-regulator";
 486                                         regulator-name = "vdd3p0";
 487                                         regulator-min-microvolt = <2800000>;
 488                                         regulator-max-microvolt = <3150000>;
 489                                         regulator-always-on;
 490                                         anatop-reg-offset = <0x120>;
 491                                         anatop-vol-bit-shift = <8>;
 492                                         anatop-vol-bit-width = <5>;
 493                                         anatop-min-bit-val = <0>;
 494                                         anatop-min-voltage = <2625000>;
 495                                         anatop-max-voltage = <3400000>;
 496                                 };
 497
 498                                 regulator-2p5@130 {
 499                                         compatible = "fsl,anatop-regulator";
 500                                         regulator-name = "vdd2p5";
 501                                         regulator-min-microvolt = <2000000>;
 502                                         regulator-max-microvolt = <2750000>;
 503                                         regulator-always-on;
 504                                         anatop-reg-offset = <0x130>;
 505                                         anatop-vol-bit-shift = <8>;
 506                                         anatop-vol-bit-width = <5>;
 507                                         anatop-min-bit-val = <0>;
 508                                         anatop-min-voltage = <2000000>;
 509                                         anatop-max-voltage = <2750000>;
 510                                 };
 511
 512                                 reg_arm: regulator-vddcore@140 {
 513                                         compatible = "fsl,anatop-regulator";
 514                                         regulator-name = "cpu";
 515                                         regulator-min-microvolt = <725000>;
 516                                         regulator-max-microvolt = <1450000>;
 517                                         regulator-always-on;
 518                                         anatop-reg-offset = <0x140>;
 519                                         anatop-vol-bit-shift = <0>;
 520                                         anatop-vol-bit-width = <5>;
 521                                         anatop-delay-reg-offset = <0x170>;
 522                                         anatop-delay-bit-shift = <24>;
 523                                         anatop-delay-bit-width = <2>;
 524                                         anatop-min-bit-val = <1>;
 525                                         anatop-min-voltage = <725000>;
 526                                         anatop-max-voltage = <1450000>;
 527                                 };
 528
 529                                 reg_pu: regulator-vddpu@140 {
 530                                         compatible = "fsl,anatop-regulator";
 531                                         regulator-name = "vddpu";
 532                                         regulator-min-microvolt = <725000>;
 533                                         regulator-max-microvolt = <1450000>;
 534                                         regulator-always-on;
 535                                         anatop-reg-offset = <0x140>;
 536                                         anatop-vol-bit-shift = <9>;
 537                                         anatop-vol-bit-width = <5>;
 538                                         anatop-delay-reg-offset = <0x170>;
 539                                         anatop-delay-bit-shift = <26>;
 540                                         anatop-delay-bit-width = <2>;
 541                                         anatop-min-bit-val = <1>;
 542                                         anatop-min-voltage = <725000>;
 543                                         anatop-max-voltage = <1450000>;
 544                                 };
 545
 546                                 reg_soc: regulator-vddsoc@140 {
 547                                         compatible = "fsl,anatop-regulator";
 548                                         regulator-name = "vddsoc";
 549                                         regulator-min-microvolt = <725000>;
 550                                         regulator-max-microvolt = <1450000>;
 551                                         regulator-always-on;
 552                                         anatop-reg-offset = <0x140>;
 553                                         anatop-vol-bit-shift = <18>;
 554                                         anatop-vol-bit-width = <5>;
 555                                         anatop-delay-reg-offset = <0x170>;
 556                                         anatop-delay-bit-shift = <28>;
 557                                         anatop-delay-bit-width = <2>;
 558                                         anatop-min-bit-val = <1>;
 559                                         anatop-min-voltage = <725000>;
 560                                         anatop-max-voltage = <1450000>;
 561                                 };
 562                         };
 563
 564                         tempmon: tempmon {
 565                                 compatible = "fsl,imx6q-tempmon";
 566                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 567                                 fsl,tempmon = <&anatop>;
 568                                 fsl,tempmon-data = <&ocotp>;
 569                         };
 570
 571                         usbphy1: usbphy@020c9000 {
 572                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 573                                 reg = <0x020c9000 0x1000>;
 574                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 575                                 clocks = <&clks 182>;
 576                         };
 577
 578                         usbphy2: usbphy@020ca000 {
 579                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 580                                 reg = <0x020ca000 0x1000>;
 581                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 582                                 clocks = <&clks 183>;
 583                         };
 584
 585                         snvs@020cc000 {
 586                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 587                                 #address-cells = <1>;
 588                                 #size-cells = <1>;
 589                                 ranges = <0 0x020cc000 0x4000>;
 590
 591                                 snvs-rtc-lp@34 {
 592                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 593                                         reg = <0x34 0x58>;
 594                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 595                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 596                                 };
 597                         };
 598
 599                         epit1: epit@020d0000 { /* EPIT1 */
 600                                 reg = <0x020d0000 0x4000>;
 601                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 602                         };
 603
 604                         epit2: epit@020d4000 { /* EPIT2 */
 605                                 reg = <0x020d4000 0x4000>;
 606                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 607                         };
 608
 609                         src: src@020d8000 {
 610                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 611                                 reg = <0x020d8000 0x4000>;
 612                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 613                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 614                                 #reset-cells = <1>;
 615                         };
 616
 617                         gpc: gpc@020dc000 {
 618                                 compatible = "fsl,imx6q-gpc";
 619                                 reg = <0x020dc000 0x4000>;
 620                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 621                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 622                         };
 623
 624                         gpr: iomuxc-gpr@020e0000 {
 625                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 626                                 reg = <0x020e0000 0x38>;
 627                         };
 628
 629                         iomuxc: iomuxc@020e0000 {
 630                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 631                                 reg = <0x020e0000 0x4000>;
 632                         };
 633
 634                         ldb: ldb@020e0008 {
 635                                 #address-cells = <1>;
 636                                 #size-cells = <0>;
 637                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 638                                 gpr = <&gpr>;
 639                                 status = "disabled";
 640
 641                                 lvds-channel@0 {
 642                                         reg = <0>;
 643                                         status = "disabled";
 644                                 };
 645
 646                                 lvds-channel@1 {
 647                                         reg = <1>;
 648                                         status = "disabled";
 649                                 };
 650                         };
 651
 652                         dcic1: dcic@020e4000 {
 653                                 reg = <0x020e4000 0x4000>;
 654                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         dcic2: dcic@020e8000 {
 658                                 reg = <0x020e8000 0x4000>;
 659                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         sdma: sdma@020ec000 {
 663                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 664                                 reg = <0x020ec000 0x4000>;
 665                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 666                                 clocks = <&clks 155>, <&clks 155>;
 667                                 clock-names = "ipg", "ahb";
 668                                 #dma-cells = <3>;
 669                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 670                         };
 671                 };
 672
 673                 aips-bus@02100000 { /* AIPS2 */
 674                         compatible = "fsl,aips-bus", "simple-bus";
 675                         #address-cells = <1>;
 676                         #size-cells = <1>;
 677                         reg = <0x02100000 0x100000>;
 678                         ranges;
 679
 680                         caam@02100000 {
 681                                 reg = <0x02100000 0x40000>;
 682                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 683                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 684                         };
 685
 686                         aipstz@0217c000 { /* AIPSTZ2 */
 687                                 reg = <0x0217c000 0x4000>;
 688                         };
 689
 690                         usbotg: usb@02184000 {
 691                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 692                                 reg = <0x02184000 0x200>;
 693                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks 162>;
 695                                 fsl,usbphy = <&usbphy1>;
 696                                 fsl,usbmisc = <&usbmisc 0>;
 697                                 status = "disabled";
 698                         };
 699
 700                         usbh1: usb@02184200 {
 701                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 702                                 reg = <0x02184200 0x200>;
 703                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks 162>;
 705                                 fsl,usbphy = <&usbphy2>;
 706                                 fsl,usbmisc = <&usbmisc 1>;
 707                                 status = "disabled";
 708                         };
 709
 710                         usbh2: usb@02184400 {
 711                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 712                                 reg = <0x02184400 0x200>;
 713                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks 162>;
 715                                 fsl,usbmisc = <&usbmisc 2>;
 716                                 status = "disabled";
 717                         };
 718
 719                         usbh3: usb@02184600 {
 720                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 721                                 reg = <0x02184600 0x200>;
 722                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 723                                 clocks = <&clks 162>;
 724                                 fsl,usbmisc = <&usbmisc 3>;
 725                                 status = "disabled";
 726                         };
 727
 728                         usbmisc: usbmisc@02184800 {
 729                                 #index-cells = <1>;
 730                                 compatible = "fsl,imx6q-usbmisc";
 731                                 reg = <0x02184800 0x200>;
 732                                 clocks = <&clks 162>;
 733                         };
 734
 735                         fec: ethernet@02188000 {
 736                                 compatible = "fsl,imx6q-fec";
 737                                 reg = <0x02188000 0x4000>;
 738                                 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
 739                                              <0 119 IRQ_TYPE_LEVEL_HIGH>;
 740                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 741                                 clock-names = "ipg", "ahb", "ptp";
 742                                 status = "disabled";
 743                         };
 744
 745                         mlb@0218c000 {
 746                                 reg = <0x0218c000 0x4000>;
 747                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 748                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 749                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 750                         };
 751
 752                         usdhc1: usdhc@02190000 {
 753                                 compatible = "fsl,imx6q-usdhc";
 754                                 reg = <0x02190000 0x4000>;
 755                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 757                                 clock-names = "ipg", "ahb", "per";
 758                                 bus-width = <4>;
 759                                 status = "disabled";
 760                         };
 761
 762                         usdhc2: usdhc@02194000 {
 763                                 compatible = "fsl,imx6q-usdhc";
 764                                 reg = <0x02194000 0x4000>;
 765                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 766                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 767                                 clock-names = "ipg", "ahb", "per";
 768                                 bus-width = <4>;
 769                                 status = "disabled";
 770                         };
 771
 772                         usdhc3: usdhc@02198000 {
 773                                 compatible = "fsl,imx6q-usdhc";
 774                                 reg = <0x02198000 0x4000>;
 775                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 776                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 777                                 clock-names = "ipg", "ahb", "per";
 778                                 bus-width = <4>;
 779                                 status = "disabled";
 780                         };
 781
 782                         usdhc4: usdhc@0219c000 {
 783                                 compatible = "fsl,imx6q-usdhc";
 784                                 reg = <0x0219c000 0x4000>;
 785                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 787                                 clock-names = "ipg", "ahb", "per";
 788                                 bus-width = <4>;
 789                                 status = "disabled";
 790                         };
 791
 792                         i2c1: i2c@021a0000 {
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 796                                 reg = <0x021a0000 0x4000>;
 797                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 798                                 clocks = <&clks 125>;
 799                                 status = "disabled";
 800                         };
 801
 802                         i2c2: i2c@021a4000 {
 803                                 #address-cells = <1>;
 804                                 #size-cells = <0>;
 805                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 806                                 reg = <0x021a4000 0x4000>;
 807                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 808                                 clocks = <&clks 126>;
 809                                 status = "disabled";
 810                         };
 811
 812                         i2c3: i2c@021a8000 {
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 816                                 reg = <0x021a8000 0x4000>;
 817                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 818                                 clocks = <&clks 127>;
 819                                 status = "disabled";
 820                         };
 821
 822                         romcp@021ac000 {
 823                                 reg = <0x021ac000 0x4000>;
 824                         };
 825
 826                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 827                                 compatible = "fsl,imx6q-mmdc";
 828                                 reg = <0x021b0000 0x4000>;
 829                         };
 830
 831                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 832                                 reg = <0x021b4000 0x4000>;
 833                         };
 834
 835                         weim: weim@021b8000 {
 836                                 compatible = "fsl,imx6q-weim";
 837                                 reg = <0x021b8000 0x4000>;
 838                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clks 196>;
 840                         };
 841
 842                         ocotp: ocotp@021bc000 {
 843                                 compatible = "fsl,imx6q-ocotp", "syscon";
 844                                 reg = <0x021bc000 0x4000>;
 845                         };
 846
 847                         tzasc@021d0000 { /* TZASC1 */
 848                                 reg = <0x021d0000 0x4000>;
 849                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 850                         };
 851
 852                         tzasc@021d4000 { /* TZASC2 */
 853                                 reg = <0x021d4000 0x4000>;
 854                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 855                         };
 856
 857                         audmux: audmux@021d8000 {
 858                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 859                                 reg = <0x021d8000 0x4000>;
 860                                 status = "disabled";
 861                         };
 862
 863                         mipi_csi: mipi@021dc000 {
 864                                 reg = <0x021dc000 0x4000>;
 865                         };
 866
 867                         mipi@021e0000 { /* MIPI-DSI */
 868                                 reg = <0x021e0000 0x4000>;
 869                         };
 870
 871                         vdoa@021e4000 {
 872                                 reg = <0x021e4000 0x4000>;
 873                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 874                         };
 875
 876                         uart2: serial@021e8000 {
 877                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 878                                 reg = <0x021e8000 0x4000>;
 879                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 880                                 clocks = <&clks 160>, <&clks 161>;
 881                                 clock-names = "ipg", "per";
 882                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 883                                 dma-names = "rx", "tx";
 884                                 status = "disabled";
 885                         };
 886
 887                         uart3: serial@021ec000 {
 888                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 889                                 reg = <0x021ec000 0x4000>;
 890                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 891                                 clocks = <&clks 160>, <&clks 161>;
 892                                 clock-names = "ipg", "per";
 893                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 894                                 dma-names = "rx", "tx";
 895                                 status = "disabled";
 896                         };
 897
 898                         uart4: serial@021f0000 {
 899                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 900                                 reg = <0x021f0000 0x4000>;
 901                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 902                                 clocks = <&clks 160>, <&clks 161>;
 903                                 clock-names = "ipg", "per";
 904                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 905                                 dma-names = "rx", "tx";
 906                                 status = "disabled";
 907                         };
 908
 909                         uart5: serial@021f4000 {
 910                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 911                                 reg = <0x021f4000 0x4000>;
 912                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 913                                 clocks = <&clks 160>, <&clks 161>;
 914                                 clock-names = "ipg", "per";
 915                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 916                                 dma-names = "rx", "tx";
 917                                 status = "disabled";
 918                         };
 919                 };
 920
 921                 ipu1: ipu@02400000 {
 922                         #crtc-cells = <1>;
 923                         compatible = "fsl,imx6q-ipu";
 924                         reg = <0x02400000 0x400000>;
 925                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
 927                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 928                         clock-names = "bus", "di0", "di1";
 929                         resets = <&src 2>;
 930                 };
 931         };
 932 };