arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 gpio5 = &gpio6;
  26                 gpio6 = &gpio7;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 ipu0 = &ipu1;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39                 spi3 = &ecspi4;
  40                 usbphy0 = &usbphy1;
  41                 usbphy1 = &usbphy2;
  42         };
  43
  44         intc: interrupt-controller@00a01000 {
  45                 compatible = "arm,cortex-a9-gic";
  46                 #interrupt-cells = <3>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 interrupt-controller;
  50                 reg = <0x00a01000 0x1000>,
  51                       <0x00a00100 0x100>;
  52         };
  53
  54         clocks {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 ckil {
  59                         compatible = "fsl,imx-ckil", "fixed-clock";
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 ckih1 {
  64                         compatible = "fsl,imx-ckih1", "fixed-clock";
  65                         clock-frequency = <0>;
  66                 };
  67
  68                 osc {
  69                         compatible = "fsl,imx-osc", "fixed-clock";
  70                         clock-frequency = <24000000>;
  71                 };
  72         };
  73
  74         soc {
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 compatible = "simple-bus";
  78                 interrupt-parent = <&intc>;
  79                 ranges;
  80
  81                 dma_apbh: dma-apbh@00110000 {
  82                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  83                         reg = <0x00110000 0x2000>;
  84                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  88                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  89                         #dma-cells = <1>;
  90                         dma-channels = <4>;
  91                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  92                 };
  93
  94                 gpmi: gpmi-nand@00112000 {
  95                         compatible = "fsl,imx6q-gpmi-nand";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  99                         reg-names = "gpmi-nand", "bch";
 100                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 101                         interrupt-names = "bch";
 102                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 103                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 104                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 105                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 106                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 107                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 108                                       "gpmi_bch_apb", "per1_bch";
 109                         dmas = <&dma_apbh 0>;
 110                         dma-names = "rx-tx";
 111                         status = "disabled";
 112                 };
 113
 114                 timer@00a00600 {
 115                         compatible = "arm,cortex-a9-twd-timer";
 116                         reg = <0x00a00600 0x20>;
 117                         interrupts = <1 13 0xf01>;
 118                         clocks = <&clks IMX6QDL_CLK_TWD>;
 119                 };
 120
 121                 L2: l2-cache@00a02000 {
 122                         compatible = "arm,pl310-cache";
 123                         reg = <0x00a02000 0x1000>;
 124                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 125                         cache-unified;
 126                         cache-level = <2>;
 127                         arm,tag-latency = <4 2 3>;
 128                         arm,data-latency = <4 2 3>;
 129                 };
 130
 131                 pcie: pcie@0x01000000 {
 132                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 133                         reg = <0x01ffc000 0x4000>; /* DBI */
 134                         #address-cells = <3>;
 135                         #size-cells = <2>;
 136                         device_type = "pci";
 137                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 138                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 139                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 140                         num-lanes = <1>;
 141                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 142                         clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_CLK_SATA_REF_100M>,
 143                                  <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
 144                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 145                         status = "disabled";
 146                 };
 147
 148                 pmu {
 149                         compatible = "arm,cortex-a9-pmu";
 150                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 151                 };
 152
 153                 hdmi_core: hdmi_core@00120000 {
 154                         compatible = "fsl,imx6q-hdmi-core";
 155                         reg = <0x00120000 0x9000>;
 156                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 157                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 158                                         <&clks IMX6QDL_CLK_HSI_TX>;
 159                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 160                         status = "disabled";
 161                 };
 162
 163                 hdmi_video: hdmi_video@020e0000 {
 164                         compatible = "fsl,imx6q-hdmi-video";
 165                         reg = <0x020e0000 0x1000>;
 166                         reg-names = "hdmi_gpr";
 167                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 169                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 170                                         <&clks IMX6QDL_CLK_HSI_TX>;
 171                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 172                         status = "disabled";
 173                 };
 174
 175                 hdmi_audio: hdmi_audio@00120000 {
 176                         compatible = "fsl,imx6q-hdmi-audio";
 177                         clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
 178                                         <&clks IMX6QDL_CLK_HDMI_IAHB>,
 179                                         <&clks IMX6QDL_CLK_HSI_TX>;
 180                         clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
 181                         dmas = <&sdma 2 22 0>;
 182                         dma-names = "tx";
 183                         status = "disabled";
 184                 };
 185
 186                 hdmi_cec: hdmi_cec@00120000 {
 187                         compatible = "fsl,imx6q-hdmi-cec";
 188                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 189                         status = "disabled";
 190                 };
 191
 192                 aips-bus@02000000 { /* AIPS1 */
 193                         compatible = "fsl,aips-bus", "simple-bus";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         reg = <0x02000000 0x100000>;
 197                         ranges;
 198
 199                         spba-bus@02000000 {
 200                                 compatible = "fsl,spba-bus", "simple-bus";
 201                                 #address-cells = <1>;
 202                                 #size-cells = <1>;
 203                                 reg = <0x02000000 0x40000>;
 204                                 ranges;
 205
 206                                 spdif: spdif@02004000 {
 207                                         compatible = "fsl,imx35-spdif";
 208                                         reg = <0x02004000 0x4000>;
 209                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 210                                         dmas = <&sdma 14 18 0>,
 211                                                <&sdma 15 18 0>;
 212                                         dma-names = "rx", "tx";
 213                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 214                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 215                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI>,
 216                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_MLB>,
 217                                                  <&clks IMX6QDL_CLK_DUMMY>;
 218                                         clock-names = "core",  "rxtx0",
 219                                                       "rxtx1", "rxtx2",
 220                                                       "rxtx3", "rxtx4",
 221                                                       "rxtx5", "rxtx6",
 222                                                       "rxtx7";
 223                                         status = "disabled";
 224                                 };
 225
 226                                 ecspi1: ecspi@02008000 {
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 230                                         reg = <0x02008000 0x4000>;
 231                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 232                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 233                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 234                                         clock-names = "ipg", "per";
 235                                         status = "disabled";
 236                                 };
 237
 238                                 ecspi2: ecspi@0200c000 {
 239                                         #address-cells = <1>;
 240                                         #size-cells = <0>;
 241                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 242                                         reg = <0x0200c000 0x4000>;
 243                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 245                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 246                                         clock-names = "ipg", "per";
 247                                         status = "disabled";
 248                                 };
 249
 250                                 ecspi3: ecspi@02010000 {
 251                                         #address-cells = <1>;
 252                                         #size-cells = <0>;
 253                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 254                                         reg = <0x02010000 0x4000>;
 255                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 256                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 257                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 258                                         clock-names = "ipg", "per";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 ecspi4: ecspi@02014000 {
 263                                         #address-cells = <1>;
 264                                         #size-cells = <0>;
 265                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 266                                         reg = <0x02014000 0x4000>;
 267                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 269                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 270                                         clock-names = "ipg", "per";
 271                                         status = "disabled";
 272                                 };
 273
 274                                 uart1: serial@02020000 {
 275                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 276                                         reg = <0x02020000 0x4000>;
 277                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 278                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 279                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 280                                         clock-names = "ipg", "per";
 281                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 282                                         dma-names = "rx", "tx";
 283                                         status = "disabled";
 284                                 };
 285
 286                                 esai: esai@02024000 {
 287                                         reg = <0x02024000 0x4000>;
 288                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 289                                 };
 290
 291                                 ssi1: ssi@02028000 {
 292                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 293                                         reg = <0x02028000 0x4000>;
 294                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 295                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
 296                                         dmas = <&sdma 37 1 0>,
 297                                                <&sdma 38 1 0>;
 298                                         dma-names = "rx", "tx";
 299                                         fsl,fifo-depth = <15>;
 300                                         fsl,ssi-dma-events = <38 37>;
 301                                         status = "disabled";
 302                                 };
 303
 304                                 ssi2: ssi@0202c000 {
 305                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 306                                         reg = <0x0202c000 0x4000>;
 307                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 308                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
 309                                         dmas = <&sdma 41 1 0>,
 310                                                <&sdma 42 1 0>;
 311                                         dma-names = "rx", "tx";
 312                                         fsl,fifo-depth = <15>;
 313                                         fsl,ssi-dma-events = <42 41>;
 314                                         status = "disabled";
 315                                 };
 316
 317                                 ssi3: ssi@02030000 {
 318                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 319                                         reg = <0x02030000 0x4000>;
 320                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
 322                                         dmas = <&sdma 45 1 0>,
 323                                                <&sdma 46 1 0>;
 324                                         dma-names = "rx", "tx";
 325                                         fsl,fifo-depth = <15>;
 326                                         fsl,ssi-dma-events = <46 45>;
 327                                         status = "disabled";
 328                                 };
 329
 330                                 asrc: asrc@02034000 {
 331                                         reg = <0x02034000 0x4000>;
 332                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 333                                 };
 334
 335                                 spba@0203c000 {
 336                                         reg = <0x0203c000 0x4000>;
 337                                 };
 338                         };
 339
 340                         vpu: vpu@02040000 {
 341                                 compatible = "fsl,imx6-vpu";
 342                                 reg = <0x02040000 0x3c000>;
 343                                 reg-names = "vpu_regs";
 344                                 interrupts = <0 3 IRQ_TYPE_EDGE_RISING>,
 345                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 346                                 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
 347                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 348                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
 349                                          <&clks IMX6QDL_CLK_OCRAM>;
 350                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 351                                 iramsize = <0x21000>;
 352                                 iram = <&ocram>;
 353                                 resets = <&src 1>;
 354                                 power-domains = <&gpc 1>;
 355                         };
 356
 357                         aipstz@0207c000 { /* AIPSTZ1 */
 358                                 reg = <0x0207c000 0x4000>;
 359                         };
 360
 361                         pwm1: pwm@02080000 {
 362                                 #pwm-cells = <2>;
 363                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 364                                 reg = <0x02080000 0x4000>;
 365                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 366                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 367                                          <&clks IMX6QDL_CLK_PWM1>;
 368                                 clock-names = "ipg", "per";
 369                         };
 370
 371                         pwm2: pwm@02084000 {
 372                                 #pwm-cells = <2>;
 373                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 374                                 reg = <0x02084000 0x4000>;
 375                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 377                                          <&clks IMX6QDL_CLK_PWM2>;
 378                                 clock-names = "ipg", "per";
 379                         };
 380
 381                         pwm3: pwm@02088000 {
 382                                 #pwm-cells = <2>;
 383                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 384                                 reg = <0x02088000 0x4000>;
 385                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 387                                          <&clks IMX6QDL_CLK_PWM3>;
 388                                 clock-names = "ipg", "per";
 389                         };
 390
 391                         pwm4: pwm@0208c000 {
 392                                 #pwm-cells = <2>;
 393                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 394                                 reg = <0x0208c000 0x4000>;
 395                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 396                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 397                                          <&clks IMX6QDL_CLK_PWM4>;
 398                                 clock-names = "ipg", "per";
 399                         };
 400
 401                         can1: flexcan@02090000 {
 402                                 compatible = "fsl,imx6q-flexcan";
 403                                 reg = <0x02090000 0x4000>;
 404                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 406                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 407                                 clock-names = "ipg", "per";
 408                                 status = "disabled";
 409                         };
 410
 411                         can2: flexcan@02094000 {
 412                                 compatible = "fsl,imx6q-flexcan";
 413                                 reg = <0x02094000 0x4000>;
 414                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 415                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 416                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 417                                 clock-names = "ipg", "per";
 418                                 status = "disabled";
 419                         };
 420
 421                         gpt: gpt@02098000 {
 422                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 423                                 reg = <0x02098000 0x4000>;
 424                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 425                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 426                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 427                                 clock-names = "ipg", "per";
 428                         };
 429
 430                         gpio1: gpio@0209c000 {
 431                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x0209c000 0x4000>;
 433                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 435                                 gpio-controller;
 436                                 #gpio-cells = <2>;
 437                                 interrupt-controller;
 438                                 #interrupt-cells = <2>;
 439                         };
 440
 441                         gpio2: gpio@020a0000 {
 442                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 443                                 reg = <0x020a0000 0x4000>;
 444                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 445                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 interrupt-controller;
 449                                 #interrupt-cells = <2>;
 450                         };
 451
 452                         gpio3: gpio@020a4000 {
 453                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x020a4000 0x4000>;
 455                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                         };
 462
 463                         gpio4: gpio@020a8000 {
 464                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020a8000 0x4000>;
 466                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                         };
 473
 474                         gpio5: gpio@020ac000 {
 475                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 476                                 reg = <0x020ac000 0x4000>;
 477                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 478                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 479                                 gpio-controller;
 480                                 #gpio-cells = <2>;
 481                                 interrupt-controller;
 482                                 #interrupt-cells = <2>;
 483                         };
 484
 485                         gpio6: gpio@020b0000 {
 486                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 487                                 reg = <0x020b0000 0x4000>;
 488                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 489                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 490                                 gpio-controller;
 491                                 #gpio-cells = <2>;
 492                                 interrupt-controller;
 493                                 #interrupt-cells = <2>;
 494                         };
 495
 496                         gpio7: gpio@020b4000 {
 497                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 498                                 reg = <0x020b4000 0x4000>;
 499                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 500                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 501                                 gpio-controller;
 502                                 #gpio-cells = <2>;
 503                                 interrupt-controller;
 504                                 #interrupt-cells = <2>;
 505                         };
 506
 507                         kpp: kpp@020b8000 {
 508                                 reg = <0x020b8000 0x4000>;
 509                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 510                         };
 511
 512                         wdog1: wdog@020bc000 {
 513                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 514                                 reg = <0x020bc000 0x4000>;
 515                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 516                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 517                         };
 518
 519                         wdog2: wdog@020c0000 {
 520                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 521                                 reg = <0x020c0000 0x4000>;
 522                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 523                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 524                                 status = "disabled";
 525                         };
 526
 527                         clks: ccm@020c4000 {
 528                                 compatible = "fsl,imx6q-ccm";
 529                                 reg = <0x020c4000 0x4000>;
 530                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 531                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 532                                 #clock-cells = <1>;
 533                         };
 534
 535                         anatop: anatop@020c8000 {
 536                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 537                                 reg = <0x020c8000 0x1000>;
 538                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 539                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 541
 542                                 regulator-1p1@110 {
 543                                         compatible = "fsl,anatop-regulator";
 544                                         regulator-name = "vdd1p1";
 545                                         regulator-min-microvolt = <800000>;
 546                                         regulator-max-microvolt = <1375000>;
 547                                         regulator-always-on;
 548                                         anatop-reg-offset = <0x110>;
 549                                         anatop-vol-bit-shift = <8>;
 550                                         anatop-vol-bit-width = <5>;
 551                                         anatop-min-bit-val = <4>;
 552                                         anatop-min-voltage = <800000>;
 553                                         anatop-max-voltage = <1375000>;
 554                                 };
 555
 556                                 regulator-3p0@120 {
 557                                         compatible = "fsl,anatop-regulator";
 558                                         regulator-name = "vdd3p0";
 559                                         regulator-min-microvolt = <2800000>;
 560                                         regulator-max-microvolt = <3150000>;
 561                                         regulator-always-on;
 562                                         anatop-reg-offset = <0x120>;
 563                                         anatop-vol-bit-shift = <8>;
 564                                         anatop-vol-bit-width = <5>;
 565                                         anatop-min-bit-val = <0>;
 566                                         anatop-min-voltage = <2625000>;
 567                                         anatop-max-voltage = <3400000>;
 568                                 };
 569
 570                                 regulator-2p5@130 {
 571                                         compatible = "fsl,anatop-regulator";
 572                                         regulator-name = "vdd2p5";
 573                                         regulator-min-microvolt = <2000000>;
 574                                         regulator-max-microvolt = <2750000>;
 575                                         regulator-always-on;
 576                                         anatop-reg-offset = <0x130>;
 577                                         anatop-vol-bit-shift = <8>;
 578                                         anatop-vol-bit-width = <5>;
 579                                         anatop-min-bit-val = <0>;
 580                                         anatop-min-voltage = <2000000>;
 581                                         anatop-max-voltage = <2750000>;
 582                                 };
 583
 584                                 reg_arm: regulator-vddcore@140 {
 585                                         compatible = "fsl,anatop-regulator";
 586                                         regulator-name = "vddarm";
 587                                         regulator-min-microvolt = <725000>;
 588                                         regulator-max-microvolt = <1450000>;
 589                                         regulator-always-on;
 590                                         anatop-reg-offset = <0x140>;
 591                                         anatop-vol-bit-shift = <0>;
 592                                         anatop-vol-bit-width = <5>;
 593                                         anatop-delay-reg-offset = <0x170>;
 594                                         anatop-delay-bit-shift = <24>;
 595                                         anatop-delay-bit-width = <2>;
 596                                         anatop-min-bit-val = <1>;
 597                                         anatop-min-voltage = <725000>;
 598                                         anatop-max-voltage = <1450000>;
 599                                 };
 600
 601                                 reg_pu: regulator-vddpu@140 {
 602                                         compatible = "fsl,anatop-regulator";
 603                                         regulator-name = "vddpu";
 604                                         regulator-min-microvolt = <725000>;
 605                                         regulator-max-microvolt = <1450000>;
 606                                         regulator-enable-ramp-delay = <150>;
 607                                         regulator-boot-on;
 608                                         anatop-reg-offset = <0x140>;
 609                                         anatop-vol-bit-shift = <9>;
 610                                         anatop-vol-bit-width = <5>;
 611                                         anatop-delay-reg-offset = <0x170>;
 612                                         anatop-delay-bit-shift = <26>;
 613                                         anatop-delay-bit-width = <2>;
 614                                         anatop-min-bit-val = <1>;
 615                                         anatop-min-voltage = <725000>;
 616                                         anatop-max-voltage = <1450000>;
 617                                 };
 618
 619                                 reg_soc: regulator-vddsoc@140 {
 620                                         compatible = "fsl,anatop-regulator";
 621                                         regulator-name = "vddsoc";
 622                                         regulator-min-microvolt = <725000>;
 623                                         regulator-max-microvolt = <1450000>;
 624                                         regulator-always-on;
 625                                         anatop-reg-offset = <0x140>;
 626                                         anatop-vol-bit-shift = <18>;
 627                                         anatop-vol-bit-width = <5>;
 628                                         anatop-delay-reg-offset = <0x170>;
 629                                         anatop-delay-bit-shift = <28>;
 630                                         anatop-delay-bit-width = <2>;
 631                                         anatop-min-bit-val = <1>;
 632                                         anatop-min-voltage = <725000>;
 633                                         anatop-max-voltage = <1450000>;
 634                                 };
 635                         };
 636
 637                         tempmon: tempmon {
 638                                 compatible = "fsl,imx6q-tempmon";
 639                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 640                                 fsl,tempmon = <&anatop>;
 641                                 fsl,tempmon-data = <&ocotp>;
 642                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 643                         };
 644
 645                         usbphy1: usbphy@020c9000 {
 646                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 647                                 reg = <0x020c9000 0x1000>;
 648                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 649                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 650                                 fsl,anatop = <&anatop>;
 651                         };
 652
 653                         usbphy2: usbphy@020ca000 {
 654                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 655                                 reg = <0x020ca000 0x1000>;
 656                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 658                                 fsl,anatop = <&anatop>;
 659                         };
 660
 661                         snvs@020cc000 {
 662                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 663                                 #address-cells = <1>;
 664                                 #size-cells = <1>;
 665                                 ranges = <0 0x020cc000 0x4000>;
 666
 667                                 snvs-rtc-lp@34 {
 668                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 669                                         reg = <0x34 0x58>;
 670                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 671                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 672                                 };
 673                         };
 674
 675                         epit1: epit@020d0000 { /* EPIT1 */
 676                                 reg = <0x020d0000 0x4000>;
 677                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         epit2: epit@020d4000 { /* EPIT2 */
 681                                 reg = <0x020d4000 0x4000>;
 682                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 683                         };
 684
 685                         src: src@020d8000 {
 686                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 687                                 reg = <0x020d8000 0x4000>;
 688                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 689                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 690                                 #reset-cells = <1>;
 691                         };
 692
 693                         gpc: gpc@020dc000 {
 694                                 compatible = "fsl,imx6q-gpc";
 695                                 reg = <0x020dc000 0x4000>;
 696                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 697                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 698                                 pu-supply = <&reg_pu>;
 699                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 700                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 701                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 702                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 703                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 704                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 705                                 #power-domain-cells = <1>;
 706                         };
 707
 708                         gpr: iomuxc-gpr@020e0000 {
 709                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 710                                 reg = <0x020e0000 0x38>;
 711                         };
 712
 713                         iomuxc: iomuxc@020e0000 {
 714                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 715                                 reg = <0x020e0000 0x4000>;
 716                         };
 717
 718                         ldb: ldb@020e0008 {
 719                                 #address-cells = <1>;
 720                                 #size-cells = <0>;
 721                                 gpr = <&gpr>;
 722                                 status = "disabled";
 723
 724                                 lvds-channel@0 {
 725                                         reg = <0>;
 726                                         status = "disabled";
 727                                 };
 728
 729                                 lvds-channel@1 {
 730                                         reg = <1>;
 731                                         status = "disabled";
 732                                 };
 733                         };
 734
 735                         dcic1: dcic@020e4000 {
 736                                 compatible = "fsl,imx6q-dcic";
 737                                 reg = <0x020e4000 0x4000>;
 738                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 739                                 clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
 740                                 clock-names = "dcic", "disp-axi";
 741                                 gpr = <&gpr>;
 742                                 status = "disabled";
 743                         };
 744
 745                         dcic2: dcic@020e8000 {
 746                                 compatible = "fsl,imx6q-dcic";
 747                                 reg = <0x020e8000 0x4000>;
 748                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 749                                 clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
 750                                 clock-names = "dcic", "disp-axi";
 751                                 gpr = <&gpr>;
 752                                 status = "disabled";
 753                         };
 754
 755                         sdma: sdma@020ec000 {
 756                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 757                                 reg = <0x020ec000 0x4000>;
 758                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 759                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 760                                          <&clks IMX6QDL_CLK_SDMA>;
 761                                 clock-names = "ipg", "ahb";
 762                                 #dma-cells = <3>;
 763                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 764                         };
 765                 };
 766
 767                 aips-bus@02100000 { /* AIPS2 */
 768                         compatible = "fsl,aips-bus", "simple-bus";
 769                         #address-cells = <1>;
 770                         #size-cells = <1>;
 771                         reg = <0x02100000 0x100000>;
 772                         ranges;
 773
 774                         caam@02100000 {
 775                                 reg = <0x02100000 0x40000>;
 776                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 777                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 778                         };
 779
 780                         aipstz@0217c000 { /* AIPSTZ2 */
 781                                 reg = <0x0217c000 0x4000>;
 782                         };
 783
 784                         usbotg: usb@02184000 {
 785                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 786                                 reg = <0x02184000 0x200>;
 787                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 788                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 789                                 fsl,usbphy = <&usbphy1>;
 790                                 fsl,usbmisc = <&usbmisc 0>;
 791                                 status = "disabled";
 792                         };
 793
 794                         usbh1: usb@02184200 {
 795                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 796                                 reg = <0x02184200 0x200>;
 797                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 798                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 799                                 fsl,usbphy = <&usbphy2>;
 800                                 fsl,usbmisc = <&usbmisc 1>;
 801                                 status = "disabled";
 802                         };
 803
 804                         usbh2: usb@02184400 {
 805                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 806                                 reg = <0x02184400 0x200>;
 807                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 808                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 809                                 fsl,usbmisc = <&usbmisc 2>;
 810                                 status = "disabled";
 811                         };
 812
 813                         usbh3: usb@02184600 {
 814                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 815                                 reg = <0x02184600 0x200>;
 816                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 818                                 fsl,usbmisc = <&usbmisc 3>;
 819                                 status = "disabled";
 820                         };
 821
 822                         usbmisc: usbmisc@02184800 {
 823                                 #index-cells = <1>;
 824                                 compatible = "fsl,imx6q-usbmisc";
 825                                 reg = <0x02184800 0x200>;
 826                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 827                         };
 828
 829                         fec: ethernet@02188000 {
 830                                 compatible = "fsl,imx6q-fec";
 831                                 reg = <0x02188000 0x4000>;
 832                                 interrupts-extended =
 833                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 834                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 835                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 836                                          <&clks IMX6QDL_CLK_ENET>,
 837                                          <&clks IMX6QDL_CLK_ENET_REF>;
 838                                 clock-names = "ipg", "ahb", "ptp";
 839                                 status = "disabled";
 840                         };
 841
 842                         mlb@0218c000 {
 843                                 reg = <0x0218c000 0x4000>;
 844                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 845                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 846                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 847                         };
 848
 849                         usdhc1: usdhc@02190000 {
 850                                 compatible = "fsl,imx6q-usdhc";
 851                                 reg = <0x02190000 0x4000>;
 852                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 854                                          <&clks IMX6QDL_CLK_USDHC1>,
 855                                          <&clks IMX6QDL_CLK_USDHC1>;
 856                                 clock-names = "ipg", "ahb", "per";
 857                                 bus-width = <4>;
 858                                 status = "disabled";
 859                         };
 860
 861                         usdhc2: usdhc@02194000 {
 862                                 compatible = "fsl,imx6q-usdhc";
 863                                 reg = <0x02194000 0x4000>;
 864                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 866                                          <&clks IMX6QDL_CLK_USDHC2>,
 867                                          <&clks IMX6QDL_CLK_USDHC2>;
 868                                 clock-names = "ipg", "ahb", "per";
 869                                 bus-width = <4>;
 870                                 status = "disabled";
 871                         };
 872
 873                         usdhc3: usdhc@02198000 {
 874                                 compatible = "fsl,imx6q-usdhc";
 875                                 reg = <0x02198000 0x4000>;
 876                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 878                                          <&clks IMX6QDL_CLK_USDHC3>,
 879                                          <&clks IMX6QDL_CLK_USDHC3>;
 880                                 clock-names = "ipg", "ahb", "per";
 881                                 bus-width = <4>;
 882                                 status = "disabled";
 883                         };
 884
 885                         usdhc4: usdhc@0219c000 {
 886                                 compatible = "fsl,imx6q-usdhc";
 887                                 reg = <0x0219c000 0x4000>;
 888                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 890                                          <&clks IMX6QDL_CLK_USDHC4>,
 891                                          <&clks IMX6QDL_CLK_USDHC4>;
 892                                 clock-names = "ipg", "ahb", "per";
 893                                 bus-width = <4>;
 894                                 status = "disabled";
 895                         };
 896
 897                         i2c1: i2c@021a0000 {
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 901                                 reg = <0x021a0000 0x4000>;
 902                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 903                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 904                                 status = "disabled";
 905                         };
 906
 907                         i2c2: i2c@021a4000 {
 908                                 #address-cells = <1>;
 909                                 #size-cells = <0>;
 910                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 911                                 reg = <0x021a4000 0x4000>;
 912                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 913                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 914                                 status = "disabled";
 915                         };
 916
 917                         i2c3: i2c@021a8000 {
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 921                                 reg = <0x021a8000 0x4000>;
 922                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 923                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 924                                 status = "disabled";
 925                         };
 926
 927                         romcp@021ac000 {
 928                                 reg = <0x021ac000 0x4000>;
 929                         };
 930
 931                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 932                                 compatible = "fsl,imx6q-mmdc";
 933                                 reg = <0x021b0000 0x4000>;
 934                         };
 935
 936                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 937                                 reg = <0x021b4000 0x4000>;
 938                         };
 939
 940                         weim: weim@021b8000 {
 941                                 compatible = "fsl,imx6q-weim";
 942                                 reg = <0x021b8000 0x4000>;
 943                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 944                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 945                         };
 946
 947                         ocotp: ocotp@021bc000 {
 948                                 compatible = "fsl,imx6q-ocotp", "syscon";
 949                                 reg = <0x021bc000 0x4000>;
 950                         };
 951
 952                         tzasc@021d0000 { /* TZASC1 */
 953                                 reg = <0x021d0000 0x4000>;
 954                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 955                         };
 956
 957                         tzasc@021d4000 { /* TZASC2 */
 958                                 reg = <0x021d4000 0x4000>;
 959                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 960                         };
 961
 962                         audmux: audmux@021d8000 {
 963                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 964                                 reg = <0x021d8000 0x4000>;
 965                                 status = "disabled";
 966                         };
 967
 968                         mipi@021dc000 { /* MIPI-CSI */
 969                                 reg = <0x021dc000 0x4000>;
 970                         };
 971
 972                         mipi@021e0000 { /* MIPI-DSI */
 973                                 reg = <0x021e0000 0x4000>;
 974                         };
 975
 976                         vdoa@021e4000 {
 977                                 reg = <0x021e4000 0x4000>;
 978                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 979                         };
 980
 981                         uart2: serial@021e8000 {
 982                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 983                                 reg = <0x021e8000 0x4000>;
 984                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 985                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 986                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 987                                 clock-names = "ipg", "per";
 988                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 989                                 dma-names = "rx", "tx";
 990                                 status = "disabled";
 991                         };
 992
 993                         uart3: serial@021ec000 {
 994                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 995                                 reg = <0x021ec000 0x4000>;
 996                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 997                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 998                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 999                                 clock-names = "ipg", "per";
1000                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1001                                 dma-names = "rx", "tx";
1002                                 status = "disabled";
1003                         };
1004
1005                         uart4: serial@021f0000 {
1006                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1007                                 reg = <0x021f0000 0x4000>;
1008                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1010                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1011                                 clock-names = "ipg", "per";
1012                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1013                                 dma-names = "rx", "tx";
1014                                 status = "disabled";
1015                         };
1016
1017                         uart5: serial@021f4000 {
1018                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1019                                 reg = <0x021f4000 0x4000>;
1020                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1021                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1022                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1023                                 clock-names = "ipg", "per";
1024                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1025                                 dma-names = "rx", "tx";
1026                                 status = "disabled";
1027                         };
1028                 };
1029
1030                 ipu1: ipu@02400000 {
1031                         compatible = "fsl,imx6q-ipu";
1032                         reg = <0x02400000 0x400000>;
1033                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1034                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1035                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1036                                  <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
1037                                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
1038                                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
1039                         clock-names = "bus",
1040                                       "di0", "di1",
1041                                       "di0_sel", "di1_sel",
1042                                       "ldb_di0", "ldb_di1";
1043                         resets = <&src 2>;
1044                         bypass_reset = <0>;
1045                 };
1046         };
1047 };