arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 ckih1 {
  69                         compatible = "fsl,imx-ckih1", "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <24000000>;
  78                 };
  79         };
  80
  81         soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "simple-bus";
  85                 interrupt-parent = <&intc>;
  86                 ranges;
  87
  88                 dma_apbh: dma-apbh@00110000 {
  89                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  90                         reg = <0x00110000 0x2000>;
  91                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  95                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  96                         #dma-cells = <1>;
  97                         dma-channels = <4>;
  98                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  99                 };
 100
 101                 gpmi: gpmi-nand@00112000 {
 102                         compatible = "fsl,imx6q-gpmi-nand";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 106                         reg-names = "gpmi-nand", "bch";
 107                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 108                         interrupt-names = "bch";
 109                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 110                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 111                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 112                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 113                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 114                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 115                                       "gpmi_bch_apb", "per1_bch";
 116                         dmas = <&dma_apbh 0>;
 117                         dma-names = "rx-tx";
 118                         status = "disabled";
 119                 };
 120
 121                 timer@00a00600 {
 122                         compatible = "arm,cortex-a9-twd-timer";
 123                         reg = <0x00a00600 0x20>;
 124                         interrupts = <1 13 0xf01>;
 125                         clocks = <&clks IMX6QDL_CLK_TWD>;
 126                 };
 127
 128                 L2: l2-cache@00a02000 {
 129                         compatible = "arm,pl310-cache";
 130                         reg = <0x00a02000 0x1000>;
 131                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 132                         cache-unified;
 133                         cache-level = <2>;
 134                         arm,tag-latency = <4 2 3>;
 135                         arm,data-latency = <4 2 3>;
 136                 };
 137
 138                 pcie: pcie@0x01000000 {
 139                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 140                         reg = <0x01ffc000 0x04000>,
 141                               <0x01f00000 0x80000>;
 142                         reg-names = "dbi", "config";
 143                         #address-cells = <3>;
 144                         #size-cells = <2>;
 145                         device_type = "pci";
 146                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 147                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 148                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 149                         num-lanes = <1>;
 150                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "msi";
 152                         #interrupt-cells = <1>;
 153                         interrupt-map-mask = <0 0 0 0x7>;
 154                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 155                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 156                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 157                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 159                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 160                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 161                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 162                         status = "disabled";
 163                 };
 164
 165                 pmu {
 166                         compatible = "arm,cortex-a9-pmu";
 167                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 168                 };
 169
 170                 aips-bus@02000000 { /* AIPS1 */
 171                         compatible = "fsl,aips-bus", "simple-bus";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         reg = <0x02000000 0x100000>;
 175                         ranges;
 176
 177                         spba-bus@02000000 {
 178                                 compatible = "fsl,spba-bus", "simple-bus";
 179                                 #address-cells = <1>;
 180                                 #size-cells = <1>;
 181                                 reg = <0x02000000 0x40000>;
 182                                 ranges;
 183
 184                                 spdif: spdif@02004000 {
 185                                         compatible = "fsl,imx35-spdif";
 186                                         reg = <0x02004000 0x4000>;
 187                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 188                                         dmas = <&sdma 14 18 0>,
 189                                                <&sdma 15 18 0>;
 190                                         dma-names = "rx", "tx";
 191                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 192                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
 193                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 194                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 195                                                  <&clks IMX6QDL_CLK_DUMMY>;
 196                                         clock-names = "core",  "rxtx0",
 197                                                       "rxtx1", "rxtx2",
 198                                                       "rxtx3", "rxtx4",
 199                                                       "rxtx5", "rxtx6",
 200                                                       "rxtx7";
 201                                         status = "disabled";
 202                                 };
 203
 204                                 ecspi1: ecspi@02008000 {
 205                                         #address-cells = <1>;
 206                                         #size-cells = <0>;
 207                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 208                                         reg = <0x02008000 0x4000>;
 209                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 210                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 211                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 212                                         clock-names = "ipg", "per";
 213                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 214                                         dma-names = "rx", "tx";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ecspi2: ecspi@0200c000 {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 222                                         reg = <0x0200c000 0x4000>;
 223                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 224                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 225                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 226                                         clock-names = "ipg", "per";
 227                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 228                                         dma-names = "rx", "tx";
 229                                         status = "disabled";
 230                                 };
 231
 232                                 ecspi3: ecspi@02010000 {
 233                                         #address-cells = <1>;
 234                                         #size-cells = <0>;
 235                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 236                                         reg = <0x02010000 0x4000>;
 237                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 238                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 239                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 240                                         clock-names = "ipg", "per";
 241                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 242                                         dma-names = "rx", "tx";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 ecspi4: ecspi@02014000 {
 247                                         #address-cells = <1>;
 248                                         #size-cells = <0>;
 249                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 250                                         reg = <0x02014000 0x4000>;
 251                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 252                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 253                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 254                                         clock-names = "ipg", "per";
 255                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 256                                         dma-names = "rx", "tx";
 257                                         status = "disabled";
 258                                 };
 259
 260                                 uart1: serial@02020000 {
 261                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 262                                         reg = <0x02020000 0x4000>;
 263                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 264                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 265                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 266                                         clock-names = "ipg", "per";
 267                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 268                                         dma-names = "rx", "tx";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 esai: esai@02024000 {
 273                                         reg = <0x02024000 0x4000>;
 274                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 275                                 };
 276
 277                                 ssi1: ssi@02028000 {
 278                                         #sound-dai-cells = <0>;
 279                                         compatible = "fsl,imx6q-ssi",
 280                                                         "fsl,imx51-ssi";
 281                                         reg = <0x02028000 0x4000>;
 282                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 283                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
 284                                         dmas = <&sdma 37 1 0>,
 285                                                <&sdma 38 1 0>;
 286                                         dma-names = "rx", "tx";
 287                                         fsl,fifo-depth = <15>;
 288                                         status = "disabled";
 289                                 };
 290
 291                                 ssi2: ssi@0202c000 {
 292                                         #sound-dai-cells = <0>;
 293                                         compatible = "fsl,imx6q-ssi",
 294                                                         "fsl,imx51-ssi";
 295                                         reg = <0x0202c000 0x4000>;
 296                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 297                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
 298                                         dmas = <&sdma 41 1 0>,
 299                                                <&sdma 42 1 0>;
 300                                         dma-names = "rx", "tx";
 301                                         fsl,fifo-depth = <15>;
 302                                         status = "disabled";
 303                                 };
 304
 305                                 ssi3: ssi@02030000 {
 306                                         #sound-dai-cells = <0>;
 307                                         compatible = "fsl,imx6q-ssi",
 308                                                         "fsl,imx51-ssi";
 309                                         reg = <0x02030000 0x4000>;
 310                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 311                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
 312                                         dmas = <&sdma 45 1 0>,
 313                                                <&sdma 46 1 0>;
 314                                         dma-names = "rx", "tx";
 315                                         fsl,fifo-depth = <15>;
 316                                         status = "disabled";
 317                                 };
 318
 319                                 asrc: asrc@02034000 {
 320                                         reg = <0x02034000 0x4000>;
 321                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 322                                 };
 323
 324                                 spba@0203c000 {
 325                                         reg = <0x0203c000 0x4000>;
 326                                 };
 327                         };
 328
 329                         vpu: vpu@02040000 {
 330                                 reg = <0x02040000 0x3c000>;
 331                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 332                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 333                         };
 334
 335                         aipstz@0207c000 { /* AIPSTZ1 */
 336                                 reg = <0x0207c000 0x4000>;
 337                         };
 338
 339                         pwm1: pwm@02080000 {
 340                                 #pwm-cells = <2>;
 341                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 342                                 reg = <0x02080000 0x4000>;
 343                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 344                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 345                                          <&clks IMX6QDL_CLK_PWM1>;
 346                                 clock-names = "ipg", "per";
 347                         };
 348
 349                         pwm2: pwm@02084000 {
 350                                 #pwm-cells = <2>;
 351                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 352                                 reg = <0x02084000 0x4000>;
 353                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 354                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 355                                          <&clks IMX6QDL_CLK_PWM2>;
 356                                 clock-names = "ipg", "per";
 357                         };
 358
 359                         pwm3: pwm@02088000 {
 360                                 #pwm-cells = <2>;
 361                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 362                                 reg = <0x02088000 0x4000>;
 363                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 365                                          <&clks IMX6QDL_CLK_PWM3>;
 366                                 clock-names = "ipg", "per";
 367                         };
 368
 369                         pwm4: pwm@0208c000 {
 370                                 #pwm-cells = <2>;
 371                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 372                                 reg = <0x0208c000 0x4000>;
 373                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 375                                          <&clks IMX6QDL_CLK_PWM4>;
 376                                 clock-names = "ipg", "per";
 377                         };
 378
 379                         can1: flexcan@02090000 {
 380                                 compatible = "fsl,imx6q-flexcan";
 381                                 reg = <0x02090000 0x4000>;
 382                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 383                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 384                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 385                                 clock-names = "ipg", "per";
 386                                 status = "disabled";
 387                         };
 388
 389                         can2: flexcan@02094000 {
 390                                 compatible = "fsl,imx6q-flexcan";
 391                                 reg = <0x02094000 0x4000>;
 392                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 393                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 394                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 395                                 clock-names = "ipg", "per";
 396                                 status = "disabled";
 397                         };
 398
 399                         gpt: gpt@02098000 {
 400                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 401                                 reg = <0x02098000 0x4000>;
 402                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 403                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 404                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 405                                 clock-names = "ipg", "per";
 406                         };
 407
 408                         gpio1: gpio@0209c000 {
 409                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 410                                 reg = <0x0209c000 0x4000>;
 411                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 412                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 413                                 gpio-controller;
 414                                 #gpio-cells = <2>;
 415                                 interrupt-controller;
 416                                 #interrupt-cells = <2>;
 417                         };
 418
 419                         gpio2: gpio@020a0000 {
 420                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 421                                 reg = <0x020a0000 0x4000>;
 422                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 423                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 424                                 gpio-controller;
 425                                 #gpio-cells = <2>;
 426                                 interrupt-controller;
 427                                 #interrupt-cells = <2>;
 428                         };
 429
 430                         gpio3: gpio@020a4000 {
 431                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x020a4000 0x4000>;
 433                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 435                                 gpio-controller;
 436                                 #gpio-cells = <2>;
 437                                 interrupt-controller;
 438                                 #interrupt-cells = <2>;
 439                         };
 440
 441                         gpio4: gpio@020a8000 {
 442                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 443                                 reg = <0x020a8000 0x4000>;
 444                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 445                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 interrupt-controller;
 449                                 #interrupt-cells = <2>;
 450                         };
 451
 452                         gpio5: gpio@020ac000 {
 453                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x020ac000 0x4000>;
 455                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                         };
 462
 463                         gpio6: gpio@020b0000 {
 464                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020b0000 0x4000>;
 466                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                         };
 473
 474                         gpio7: gpio@020b4000 {
 475                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 476                                 reg = <0x020b4000 0x4000>;
 477                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 478                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 479                                 gpio-controller;
 480                                 #gpio-cells = <2>;
 481                                 interrupt-controller;
 482                                 #interrupt-cells = <2>;
 483                         };
 484
 485                         kpp: kpp@020b8000 {
 486                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 487                                 reg = <0x020b8000 0x4000>;
 488                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 489                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 490                                 status = "disabled";
 491                         };
 492
 493                         wdog1: wdog@020bc000 {
 494                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 495                                 reg = <0x020bc000 0x4000>;
 496                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 497                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 498                         };
 499
 500                         wdog2: wdog@020c0000 {
 501                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 502                                 reg = <0x020c0000 0x4000>;
 503                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 504                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 505                                 status = "disabled";
 506                         };
 507
 508                         clks: ccm@020c4000 {
 509                                 compatible = "fsl,imx6q-ccm";
 510                                 reg = <0x020c4000 0x4000>;
 511                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 512                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 513                                 #clock-cells = <1>;
 514                         };
 515
 516                         anatop: anatop@020c8000 {
 517                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 518                                 reg = <0x020c8000 0x1000>;
 519                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 520                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 521                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 522
 523                                 regulator-1p1@110 {
 524                                         compatible = "fsl,anatop-regulator";
 525                                         regulator-name = "vdd1p1";
 526                                         regulator-min-microvolt = <800000>;
 527                                         regulator-max-microvolt = <1375000>;
 528                                         regulator-always-on;
 529                                         anatop-reg-offset = <0x110>;
 530                                         anatop-vol-bit-shift = <8>;
 531                                         anatop-vol-bit-width = <5>;
 532                                         anatop-min-bit-val = <4>;
 533                                         anatop-min-voltage = <800000>;
 534                                         anatop-max-voltage = <1375000>;
 535                                 };
 536
 537                                 regulator-3p0@120 {
 538                                         compatible = "fsl,anatop-regulator";
 539                                         regulator-name = "vdd3p0";
 540                                         regulator-min-microvolt = <2800000>;
 541                                         regulator-max-microvolt = <3150000>;
 542                                         regulator-always-on;
 543                                         anatop-reg-offset = <0x120>;
 544                                         anatop-vol-bit-shift = <8>;
 545                                         anatop-vol-bit-width = <5>;
 546                                         anatop-min-bit-val = <0>;
 547                                         anatop-min-voltage = <2625000>;
 548                                         anatop-max-voltage = <3400000>;
 549                                 };
 550
 551                                 regulator-2p5@130 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vdd2p5";
 554                                         regulator-min-microvolt = <2000000>;
 555                                         regulator-max-microvolt = <2750000>;
 556                                         regulator-always-on;
 557                                         anatop-reg-offset = <0x130>;
 558                                         anatop-vol-bit-shift = <8>;
 559                                         anatop-vol-bit-width = <5>;
 560                                         anatop-min-bit-val = <0>;
 561                                         anatop-min-voltage = <2000000>;
 562                                         anatop-max-voltage = <2750000>;
 563                                 };
 564
 565                                 reg_arm: regulator-vddcore@140 {
 566                                         compatible = "fsl,anatop-regulator";
 567                                         regulator-name = "vddarm";
 568                                         regulator-min-microvolt = <725000>;
 569                                         regulator-max-microvolt = <1450000>;
 570                                         regulator-always-on;
 571                                         anatop-reg-offset = <0x140>;
 572                                         anatop-vol-bit-shift = <0>;
 573                                         anatop-vol-bit-width = <5>;
 574                                         anatop-delay-reg-offset = <0x170>;
 575                                         anatop-delay-bit-shift = <24>;
 576                                         anatop-delay-bit-width = <2>;
 577                                         anatop-min-bit-val = <1>;
 578                                         anatop-min-voltage = <725000>;
 579                                         anatop-max-voltage = <1450000>;
 580                                 };
 581
 582                                 reg_pu: regulator-vddpu@140 {
 583                                         compatible = "fsl,anatop-regulator";
 584                                         regulator-name = "vddpu";
 585                                         regulator-min-microvolt = <725000>;
 586                                         regulator-max-microvolt = <1450000>;
 587                                         regulator-always-on;
 588                                         anatop-reg-offset = <0x140>;
 589                                         anatop-vol-bit-shift = <9>;
 590                                         anatop-vol-bit-width = <5>;
 591                                         anatop-delay-reg-offset = <0x170>;
 592                                         anatop-delay-bit-shift = <26>;
 593                                         anatop-delay-bit-width = <2>;
 594                                         anatop-min-bit-val = <1>;
 595                                         anatop-min-voltage = <725000>;
 596                                         anatop-max-voltage = <1450000>;
 597                                 };
 598
 599                                 reg_soc: regulator-vddsoc@140 {
 600                                         compatible = "fsl,anatop-regulator";
 601                                         regulator-name = "vddsoc";
 602                                         regulator-min-microvolt = <725000>;
 603                                         regulator-max-microvolt = <1450000>;
 604                                         regulator-always-on;
 605                                         anatop-reg-offset = <0x140>;
 606                                         anatop-vol-bit-shift = <18>;
 607                                         anatop-vol-bit-width = <5>;
 608                                         anatop-delay-reg-offset = <0x170>;
 609                                         anatop-delay-bit-shift = <28>;
 610                                         anatop-delay-bit-width = <2>;
 611                                         anatop-min-bit-val = <1>;
 612                                         anatop-min-voltage = <725000>;
 613                                         anatop-max-voltage = <1450000>;
 614                                 };
 615                         };
 616
 617                         tempmon: tempmon {
 618                                 compatible = "fsl,imx6q-tempmon";
 619                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 620                                 fsl,tempmon = <&anatop>;
 621                                 fsl,tempmon-data = <&ocotp>;
 622                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 623                         };
 624
 625                         usbphy1: usbphy@020c9000 {
 626                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 627                                 reg = <0x020c9000 0x1000>;
 628                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 629                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 630                                 fsl,anatop = <&anatop>;
 631                         };
 632
 633                         usbphy2: usbphy@020ca000 {
 634                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 635                                 reg = <0x020ca000 0x1000>;
 636                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 638                                 fsl,anatop = <&anatop>;
 639                         };
 640
 641                         snvs@020cc000 {
 642                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 643                                 #address-cells = <1>;
 644                                 #size-cells = <1>;
 645                                 ranges = <0 0x020cc000 0x4000>;
 646
 647                                 snvs-rtc-lp@34 {
 648                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 649                                         reg = <0x34 0x58>;
 650                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 651                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 652                                 };
 653                         };
 654
 655                         epit1: epit@020d0000 { /* EPIT1 */
 656                                 reg = <0x020d0000 0x4000>;
 657                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 658                         };
 659
 660                         epit2: epit@020d4000 { /* EPIT2 */
 661                                 reg = <0x020d4000 0x4000>;
 662                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 663                         };
 664
 665                         src: src@020d8000 {
 666                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 667                                 reg = <0x020d8000 0x4000>;
 668                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 669                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 670                                 #reset-cells = <1>;
 671                         };
 672
 673                         gpc: gpc@020dc000 {
 674                                 compatible = "fsl,imx6q-gpc";
 675                                 reg = <0x020dc000 0x4000>;
 676                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 677                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         gpr: iomuxc-gpr@020e0000 {
 681                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 682                                 reg = <0x020e0000 0x38>;
 683                         };
 684
 685                         iomuxc: iomuxc@020e0000 {
 686                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 687                                 reg = <0x020e0000 0x4000>;
 688                         };
 689
 690                         ldb: ldb@020e0008 {
 691                                 #address-cells = <1>;
 692                                 #size-cells = <0>;
 693                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 694                                 gpr = <&gpr>;
 695                                 status = "disabled";
 696
 697                                 lvds-channel@0 {
 698                                         #address-cells = <1>;
 699                                         #size-cells = <0>;
 700                                         reg = <0>;
 701                                         status = "disabled";
 702
 703                                         port@0 {
 704                                                 reg = <0>;
 705
 706                                                 lvds0_mux_0: endpoint {
 707                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 708                                                 };
 709                                         };
 710
 711                                         port@1 {
 712                                                 reg = <1>;
 713
 714                                                 lvds0_mux_1: endpoint {
 715                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 716                                                 };
 717                                         };
 718                                 };
 719
 720                                 lvds-channel@1 {
 721                                         #address-cells = <1>;
 722                                         #size-cells = <0>;
 723                                         reg = <1>;
 724                                         status = "disabled";
 725
 726                                         port@0 {
 727                                                 reg = <0>;
 728
 729                                                 lvds1_mux_0: endpoint {
 730                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 731                                                 };
 732                                         };
 733
 734                                         port@1 {
 735                                                 reg = <1>;
 736
 737                                                 lvds1_mux_1: endpoint {
 738                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 739                                                 };
 740                                         };
 741                                 };
 742                         };
 743
 744                         hdmi: hdmi@0120000 {
 745                                 #address-cells = <1>;
 746                                 #size-cells = <0>;
 747                                 reg = <0x00120000 0x9000>;
 748                                 interrupts = <0 115 0x04>;
 749                                 gpr = <&gpr>;
 750                                 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 751                                          <&clks IMX6QDL_CLK_HDMI_ISFR>;
 752                                 clock-names = "iahb", "isfr";
 753                                 status = "disabled";
 754
 755                                 port@0 {
 756                                         reg = <0>;
 757
 758                                         hdmi_mux_0: endpoint {
 759                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 760                                         };
 761                                 };
 762
 763                                 port@1 {
 764                                         reg = <1>;
 765
 766                                         hdmi_mux_1: endpoint {
 767                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 768                                         };
 769                                 };
 770                         };
 771
 772                         dcic1: dcic@020e4000 {
 773                                 reg = <0x020e4000 0x4000>;
 774                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 775                         };
 776
 777                         dcic2: dcic@020e8000 {
 778                                 reg = <0x020e8000 0x4000>;
 779                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 780                         };
 781
 782                         sdma: sdma@020ec000 {
 783                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 784                                 reg = <0x020ec000 0x4000>;
 785                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 787                                          <&clks IMX6QDL_CLK_SDMA>;
 788                                 clock-names = "ipg", "ahb";
 789                                 #dma-cells = <3>;
 790                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 791                         };
 792                 };
 793
 794                 aips-bus@02100000 { /* AIPS2 */
 795                         compatible = "fsl,aips-bus", "simple-bus";
 796                         #address-cells = <1>;
 797                         #size-cells = <1>;
 798                         reg = <0x02100000 0x100000>;
 799                         ranges;
 800
 801                         caam@02100000 {
 802                                 reg = <0x02100000 0x40000>;
 803                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 804                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 805                         };
 806
 807                         aipstz@0217c000 { /* AIPSTZ2 */
 808                                 reg = <0x0217c000 0x4000>;
 809                         };
 810
 811                         usbotg: usb@02184000 {
 812                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 813                                 reg = <0x02184000 0x200>;
 814                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 816                                 fsl,usbphy = <&usbphy1>;
 817                                 fsl,usbmisc = <&usbmisc 0>;
 818                                 status = "disabled";
 819                         };
 820
 821                         usbh1: usb@02184200 {
 822                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 823                                 reg = <0x02184200 0x200>;
 824                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 825                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 826                                 fsl,usbphy = <&usbphy2>;
 827                                 fsl,usbmisc = <&usbmisc 1>;
 828                                 status = "disabled";
 829                         };
 830
 831                         usbh2: usb@02184400 {
 832                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 833                                 reg = <0x02184400 0x200>;
 834                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 835                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 836                                 fsl,usbmisc = <&usbmisc 2>;
 837                                 status = "disabled";
 838                         };
 839
 840                         usbh3: usb@02184600 {
 841                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 842                                 reg = <0x02184600 0x200>;
 843                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 845                                 fsl,usbmisc = <&usbmisc 3>;
 846                                 status = "disabled";
 847                         };
 848
 849                         usbmisc: usbmisc@02184800 {
 850                                 #index-cells = <1>;
 851                                 compatible = "fsl,imx6q-usbmisc";
 852                                 reg = <0x02184800 0x200>;
 853                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 854                         };
 855
 856                         fec: ethernet@02188000 {
 857                                 compatible = "fsl,imx6q-fec";
 858                                 reg = <0x02188000 0x4000>;
 859                                 interrupts-extended =
 860                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 861                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 863                                          <&clks IMX6QDL_CLK_ENET>,
 864                                          <&clks IMX6QDL_CLK_ENET_REF>;
 865                                 clock-names = "ipg", "ahb", "ptp";
 866                                 status = "disabled";
 867                         };
 868
 869                         mlb@0218c000 {
 870                                 reg = <0x0218c000 0x4000>;
 871                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 872                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 873                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 874                         };
 875
 876                         usdhc1: usdhc@02190000 {
 877                                 compatible = "fsl,imx6q-usdhc";
 878                                 reg = <0x02190000 0x4000>;
 879                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 880                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 881                                          <&clks IMX6QDL_CLK_USDHC1>,
 882                                          <&clks IMX6QDL_CLK_USDHC1>;
 883                                 clock-names = "ipg", "ahb", "per";
 884                                 bus-width = <4>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usdhc2: usdhc@02194000 {
 889                                 compatible = "fsl,imx6q-usdhc";
 890                                 reg = <0x02194000 0x4000>;
 891                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 893                                          <&clks IMX6QDL_CLK_USDHC2>,
 894                                          <&clks IMX6QDL_CLK_USDHC2>;
 895                                 clock-names = "ipg", "ahb", "per";
 896                                 bus-width = <4>;
 897                                 status = "disabled";
 898                         };
 899
 900                         usdhc3: usdhc@02198000 {
 901                                 compatible = "fsl,imx6q-usdhc";
 902                                 reg = <0x02198000 0x4000>;
 903                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 904                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 905                                          <&clks IMX6QDL_CLK_USDHC3>,
 906                                          <&clks IMX6QDL_CLK_USDHC3>;
 907                                 clock-names = "ipg", "ahb", "per";
 908                                 bus-width = <4>;
 909                                 status = "disabled";
 910                         };
 911
 912                         usdhc4: usdhc@0219c000 {
 913                                 compatible = "fsl,imx6q-usdhc";
 914                                 reg = <0x0219c000 0x4000>;
 915                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 917                                          <&clks IMX6QDL_CLK_USDHC4>,
 918                                          <&clks IMX6QDL_CLK_USDHC4>;
 919                                 clock-names = "ipg", "ahb", "per";
 920                                 bus-width = <4>;
 921                                 status = "disabled";
 922                         };
 923
 924                         i2c1: i2c@021a0000 {
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 928                                 reg = <0x021a0000 0x4000>;
 929                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 931                                 status = "disabled";
 932                         };
 933
 934                         i2c2: i2c@021a4000 {
 935                                 #address-cells = <1>;
 936                                 #size-cells = <0>;
 937                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 938                                 reg = <0x021a4000 0x4000>;
 939                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 940                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 941                                 status = "disabled";
 942                         };
 943
 944                         i2c3: i2c@021a8000 {
 945                                 #address-cells = <1>;
 946                                 #size-cells = <0>;
 947                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 948                                 reg = <0x021a8000 0x4000>;
 949                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 951                                 status = "disabled";
 952                         };
 953
 954                         romcp@021ac000 {
 955                                 reg = <0x021ac000 0x4000>;
 956                         };
 957
 958                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 959                                 compatible = "fsl,imx6q-mmdc";
 960                                 reg = <0x021b0000 0x4000>;
 961                         };
 962
 963                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 964                                 reg = <0x021b4000 0x4000>;
 965                         };
 966
 967                         weim: weim@021b8000 {
 968                                 compatible = "fsl,imx6q-weim";
 969                                 reg = <0x021b8000 0x4000>;
 970                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 971                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 972                         };
 973
 974                         ocotp: ocotp@021bc000 {
 975                                 compatible = "fsl,imx6q-ocotp", "syscon";
 976                                 reg = <0x021bc000 0x4000>;
 977                         };
 978
 979                         tzasc@021d0000 { /* TZASC1 */
 980                                 reg = <0x021d0000 0x4000>;
 981                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 982                         };
 983
 984                         tzasc@021d4000 { /* TZASC2 */
 985                                 reg = <0x021d4000 0x4000>;
 986                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 987                         };
 988
 989                         audmux: audmux@021d8000 {
 990                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 991                                 reg = <0x021d8000 0x4000>;
 992                                 status = "disabled";
 993                         };
 994
 995                         mipi_csi: mipi@021dc000 {
 996                                 reg = <0x021dc000 0x4000>;
 997                         };
 998
 999                         mipi_dsi: mipi@021e0000 {
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002                                 reg = <0x021e0000 0x4000>;
1003                                 status = "disabled";
1004
1005                                 port@0 {
1006                                         reg = <0>;
1007
1008                                         mipi_mux_0: endpoint {
1009                                                 remote-endpoint = <&ipu1_di0_mipi>;
1010                                         };
1011                                 };
1012
1013                                 port@1 {
1014                                         reg = <1>;
1015
1016                                         mipi_mux_1: endpoint {
1017                                                 remote-endpoint = <&ipu1_di1_mipi>;
1018                                         };
1019                                 };
1020                         };
1021
1022                         vdoa@021e4000 {
1023                                 reg = <0x021e4000 0x4000>;
1024                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1025                         };
1026
1027                         uart2: serial@021e8000 {
1028                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1029                                 reg = <0x021e8000 0x4000>;
1030                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1031                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1032                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1033                                 clock-names = "ipg", "per";
1034                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1035                                 dma-names = "rx", "tx";
1036                                 status = "disabled";
1037                         };
1038
1039                         uart3: serial@021ec000 {
1040                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1041                                 reg = <0x021ec000 0x4000>;
1042                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1043                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1044                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1045                                 clock-names = "ipg", "per";
1046                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1047                                 dma-names = "rx", "tx";
1048                                 status = "disabled";
1049                         };
1050
1051                         uart4: serial@021f0000 {
1052                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1053                                 reg = <0x021f0000 0x4000>;
1054                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1055                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1056                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1057                                 clock-names = "ipg", "per";
1058                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1059                                 dma-names = "rx", "tx";
1060                                 status = "disabled";
1061                         };
1062
1063                         uart5: serial@021f4000 {
1064                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1065                                 reg = <0x021f4000 0x4000>;
1066                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1067                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1068                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1069                                 clock-names = "ipg", "per";
1070                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1071                                 dma-names = "rx", "tx";
1072                                 status = "disabled";
1073                         };
1074                 };
1075
1076                 ipu1: ipu@02400000 {
1077                         #address-cells = <1>;
1078                         #size-cells = <0>;
1079                         compatible = "fsl,imx6q-ipu";
1080                         reg = <0x02400000 0x400000>;
1081                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1082                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1083                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1084                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1085                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1086                         clock-names = "bus", "di0", "di1";
1087                         resets = <&src 2>;
1088
1089                         ipu1_csi0: port@0 {
1090                                 reg = <0>;
1091                         };
1092
1093                         ipu1_csi1: port@1 {
1094                                 reg = <1>;
1095                         };
1096
1097                         ipu1_di0: port@2 {
1098                                 #address-cells = <1>;
1099                                 #size-cells = <0>;
1100                                 reg = <2>;
1101
1102                                 ipu1_di0_disp0: endpoint@0 {
1103                                 };
1104
1105                                 ipu1_di0_hdmi: endpoint@1 {
1106                                         remote-endpoint = <&hdmi_mux_0>;
1107                                 };
1108
1109                                 ipu1_di0_mipi: endpoint@2 {
1110                                         remote-endpoint = <&mipi_mux_0>;
1111                                 };
1112
1113                                 ipu1_di0_lvds0: endpoint@3 {
1114                                         remote-endpoint = <&lvds0_mux_0>;
1115                                 };
1116
1117                                 ipu1_di0_lvds1: endpoint@4 {
1118                                         remote-endpoint = <&lvds1_mux_0>;
1119                                 };
1120                         };
1121
1122                         ipu1_di1: port@3 {
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 reg = <3>;
1126
1127                                 ipu1_di0_disp1: endpoint@0 {
1128                                 };
1129
1130                                 ipu1_di1_hdmi: endpoint@1 {
1131                                         remote-endpoint = <&hdmi_mux_1>;
1132                                 };
1133
1134                                 ipu1_di1_mipi: endpoint@2 {
1135                                         remote-endpoint = <&mipi_mux_1>;
1136                                 };
1137
1138                                 ipu1_di1_lvds0: endpoint@3 {
1139                                         remote-endpoint = <&lvds0_mux_1>;
1140                                 };
1141
1142                                 ipu1_di1_lvds1: endpoint@4 {
1143                                         remote-endpoint = <&lvds1_mux_1>;
1144                                 };
1145                         };
1146                 };
1147         };
1148 };