arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "skeleton.dtsi"
  12 #include "imx6sl-pinfunc.h"
  13 #include <dt-bindings/clock/imx6sl-clock.h>
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 serial0 = &uart1;
  23                 serial1 = &uart2;
  24                 serial2 = &uart3;
  25                 serial3 = &uart4;
  26                 serial4 = &uart5;
  27                 spi0 = &ecspi1;
  28                 spi1 = &ecspi2;
  29                 spi2 = &ecspi3;
  30                 spi3 = &ecspi4;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a9";
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         next-level-cache = <&L2>;
  42                         operating-points = <
  43                                 /* kHz    uV */
  44                                 996000  1275000
  45                                 792000  1175000
  46                                 396000  975000
  47                         >;
  48                         fsl,soc-operating-points = <
  49                                 /* ARM kHz      SOC-PU uV */
  50                                 996000          1225000
  51                                 792000          1175000
  52                                 396000          1175000
  53                         >;
  54                         clock-latency = <61036>; /* two CLK32 periods */
  55                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  56                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  57                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  58                         clock-names = "arm", "pll2_pfd2_396m", "step",
  59                                       "pll1_sw", "pll1_sys";
  60                         arm-supply = <&reg_arm>;
  61                         pu-supply = <&reg_pu>;
  62                         soc-supply = <&reg_soc>;
  63                 };
  64         };
  65
  66         intc: interrupt-controller@00a01000 {
  67                 compatible = "arm,cortex-a9-gic";
  68                 #interrupt-cells = <3>;
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 interrupt-controller;
  72                 reg = <0x00a01000 0x1000>,
  73                       <0x00a00100 0x100>;
  74         };
  75
  76         clocks {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 ckil {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                 };
  84
  85                 osc {
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <24000000>;
  88                 };
  89         };
  90
  91         soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 compatible = "simple-bus";
  95                 interrupt-parent = <&intc>;
  96                 ranges;
  97
  98                 L2: l2-cache@00a02000 {
  99                         compatible = "arm,pl310-cache";
 100                         reg = <0x00a02000 0x1000>;
 101                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 102                         cache-unified;
 103                         cache-level = <2>;
 104                         arm,tag-latency = <4 2 3>;
 105                         arm,data-latency = <4 2 3>;
 106                 };
 107
 108                 pmu {
 109                         compatible = "arm,cortex-a9-pmu";
 110                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 111                 };
 112
 113                 aips1: aips-bus@02000000 {
 114                         compatible = "fsl,aips-bus", "simple-bus";
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         reg = <0x02000000 0x100000>;
 118                         ranges;
 119
 120                         spba: spba-bus@02000000 {
 121                                 compatible = "fsl,spba-bus", "simple-bus";
 122                                 #address-cells = <1>;
 123                                 #size-cells = <1>;
 124                                 reg = <0x02000000 0x40000>;
 125                                 ranges;
 126
 127                                 spdif: spdif@02004000 {
 128                                         reg = <0x02004000 0x4000>;
 129                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 130                                 };
 131
 132                                 ecspi1: ecspi@02008000 {
 133                                         #address-cells = <1>;
 134                                         #size-cells = <0>;
 135                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 136                                         reg = <0x02008000 0x4000>;
 137                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 138                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 139                                                  <&clks IMX6SL_CLK_ECSPI1>;
 140                                         clock-names = "ipg", "per";
 141                                         status = "disabled";
 142                                 };
 143
 144                                 ecspi2: ecspi@0200c000 {
 145                                         #address-cells = <1>;
 146                                         #size-cells = <0>;
 147                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 148                                         reg = <0x0200c000 0x4000>;
 149                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 150                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 151                                                  <&clks IMX6SL_CLK_ECSPI2>;
 152                                         clock-names = "ipg", "per";
 153                                         status = "disabled";
 154                                 };
 155
 156                                 ecspi3: ecspi@02010000 {
 157                                         #address-cells = <1>;
 158                                         #size-cells = <0>;
 159                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 160                                         reg = <0x02010000 0x4000>;
 161                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 162                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 163                                                  <&clks IMX6SL_CLK_ECSPI3>;
 164                                         clock-names = "ipg", "per";
 165                                         status = "disabled";
 166                                 };
 167
 168                                 ecspi4: ecspi@02014000 {
 169                                         #address-cells = <1>;
 170                                         #size-cells = <0>;
 171                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 172                                         reg = <0x02014000 0x4000>;
 173                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 174                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 175                                                  <&clks IMX6SL_CLK_ECSPI4>;
 176                                         clock-names = "ipg", "per";
 177                                         status = "disabled";
 178                                 };
 179
 180                                 uart5: serial@02018000 {
 181                                         compatible = "fsl,imx6sl-uart",
 182                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 183                                         reg = <0x02018000 0x4000>;
 184                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 185                                         clocks = <&clks IMX6SL_CLK_UART>,
 186                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 187                                         clock-names = "ipg", "per";
 188                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 189                                         dma-names = "rx", "tx";
 190                                         status = "disabled";
 191                                 };
 192
 193                                 uart1: serial@02020000 {
 194                                         compatible = "fsl,imx6sl-uart",
 195                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 196                                         reg = <0x02020000 0x4000>;
 197                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 198                                         clocks = <&clks IMX6SL_CLK_UART>,
 199                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 200                                         clock-names = "ipg", "per";
 201                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 202                                         dma-names = "rx", "tx";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 uart2: serial@02024000 {
 207                                         compatible = "fsl,imx6sl-uart",
 208                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 209                                         reg = <0x02024000 0x4000>;
 210                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 211                                         clocks = <&clks IMX6SL_CLK_UART>,
 212                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 213                                         clock-names = "ipg", "per";
 214                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 215                                         dma-names = "rx", "tx";
 216                                         status = "disabled";
 217                                 };
 218
 219                                 ssi1: ssi@02028000 {
 220                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 221                                         reg = <0x02028000 0x4000>;
 222                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 223                                         clocks = <&clks IMX6SL_CLK_SSI1>;
 224                                         dmas = <&sdma 37 1 0>,
 225                                                <&sdma 38 1 0>;
 226                                         dma-names = "rx", "tx";
 227                                         fsl,fifo-depth = <15>;
 228                                         status = "disabled";
 229                                 };
 230
 231                                 ssi2: ssi@0202c000 {
 232                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 233                                         reg = <0x0202c000 0x4000>;
 234                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 235                                         clocks = <&clks IMX6SL_CLK_SSI2>;
 236                                         dmas = <&sdma 41 1 0>,
 237                                                <&sdma 42 1 0>;
 238                                         dma-names = "rx", "tx";
 239                                         fsl,fifo-depth = <15>;
 240                                         status = "disabled";
 241                                 };
 242
 243                                 ssi3: ssi@02030000 {
 244                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 245                                         reg = <0x02030000 0x4000>;
 246                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6SL_CLK_SSI3>;
 248                                         dmas = <&sdma 45 1 0>,
 249                                                <&sdma 46 1 0>;
 250                                         dma-names = "rx", "tx";
 251                                         fsl,fifo-depth = <15>;
 252                                         status = "disabled";
 253                                 };
 254
 255                                 uart3: serial@02034000 {
 256                                         compatible = "fsl,imx6sl-uart",
 257                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 258                                         reg = <0x02034000 0x4000>;
 259                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 260                                         clocks = <&clks IMX6SL_CLK_UART>,
 261                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 262                                         clock-names = "ipg", "per";
 263                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 264                                         dma-names = "rx", "tx";
 265                                         status = "disabled";
 266                                 };
 267
 268                                 uart4: serial@02038000 {
 269                                         compatible = "fsl,imx6sl-uart",
 270                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 271                                         reg = <0x02038000 0x4000>;
 272                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 273                                         clocks = <&clks IMX6SL_CLK_UART>,
 274                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 275                                         clock-names = "ipg", "per";
 276                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 277                                         dma-names = "rx", "tx";
 278                                         status = "disabled";
 279                                 };
 280                         };
 281
 282                         pwm1: pwm@02080000 {
 283                                 #pwm-cells = <2>;
 284                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 285                                 reg = <0x02080000 0x4000>;
 286                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 287                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 288                                          <&clks IMX6SL_CLK_PWM1>;
 289                                 clock-names = "ipg", "per";
 290                         };
 291
 292                         pwm2: pwm@02084000 {
 293                                 #pwm-cells = <2>;
 294                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 295                                 reg = <0x02084000 0x4000>;
 296                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 297                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 298                                          <&clks IMX6SL_CLK_PWM2>;
 299                                 clock-names = "ipg", "per";
 300                         };
 301
 302                         pwm3: pwm@02088000 {
 303                                 #pwm-cells = <2>;
 304                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 305                                 reg = <0x02088000 0x4000>;
 306                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 307                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 308                                          <&clks IMX6SL_CLK_PWM3>;
 309                                 clock-names = "ipg", "per";
 310                         };
 311
 312                         pwm4: pwm@0208c000 {
 313                                 #pwm-cells = <2>;
 314                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 315                                 reg = <0x0208c000 0x4000>;
 316                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 317                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 318                                          <&clks IMX6SL_CLK_PWM4>;
 319                                 clock-names = "ipg", "per";
 320                         };
 321
 322                         gpt: gpt@02098000 {
 323                                 compatible = "fsl,imx6sl-gpt";
 324                                 reg = <0x02098000 0x4000>;
 325                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 326                                 clocks = <&clks IMX6SL_CLK_GPT>,
 327                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 328                                 clock-names = "ipg", "per";
 329                         };
 330
 331                         gpio1: gpio@0209c000 {
 332                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 333                                 reg = <0x0209c000 0x4000>;
 334                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 335                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 336                                 gpio-controller;
 337                                 #gpio-cells = <2>;
 338                                 interrupt-controller;
 339                                 #interrupt-cells = <2>;
 340                         };
 341
 342                         gpio2: gpio@020a0000 {
 343                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 344                                 reg = <0x020a0000 0x4000>;
 345                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 346                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 347                                 gpio-controller;
 348                                 #gpio-cells = <2>;
 349                                 interrupt-controller;
 350                                 #interrupt-cells = <2>;
 351                         };
 352
 353                         gpio3: gpio@020a4000 {
 354                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 355                                 reg = <0x020a4000 0x4000>;
 356                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 357                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 358                                 gpio-controller;
 359                                 #gpio-cells = <2>;
 360                                 interrupt-controller;
 361                                 #interrupt-cells = <2>;
 362                         };
 363
 364                         gpio4: gpio@020a8000 {
 365                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 366                                 reg = <0x020a8000 0x4000>;
 367                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 368                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 369                                 gpio-controller;
 370                                 #gpio-cells = <2>;
 371                                 interrupt-controller;
 372                                 #interrupt-cells = <2>;
 373                         };
 374
 375                         gpio5: gpio@020ac000 {
 376                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 377                                 reg = <0x020ac000 0x4000>;
 378                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 379                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 380                                 gpio-controller;
 381                                 #gpio-cells = <2>;
 382                                 interrupt-controller;
 383                                 #interrupt-cells = <2>;
 384                         };
 385
 386                         kpp: kpp@020b8000 {
 387                                 reg = <0x020b8000 0x4000>;
 388                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 389                         };
 390
 391                         wdog1: wdog@020bc000 {
 392                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 393                                 reg = <0x020bc000 0x4000>;
 394                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 395                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 396                         };
 397
 398                         wdog2: wdog@020c0000 {
 399                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 400                                 reg = <0x020c0000 0x4000>;
 401                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 403                                 status = "disabled";
 404                         };
 405
 406                         clks: ccm@020c4000 {
 407                                 compatible = "fsl,imx6sl-ccm";
 408                                 reg = <0x020c4000 0x4000>;
 409                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 411                                 #clock-cells = <1>;
 412                         };
 413
 414                         anatop: anatop@020c8000 {
 415                                 compatible = "fsl,imx6sl-anatop",
 416                                              "fsl,imx6q-anatop",
 417                                              "syscon", "simple-bus";
 418                                 reg = <0x020c8000 0x1000>;
 419                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 420                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 422
 423                                 regulator-1p1@110 {
 424                                         compatible = "fsl,anatop-regulator";
 425                                         regulator-name = "vdd1p1";
 426                                         regulator-min-microvolt = <800000>;
 427                                         regulator-max-microvolt = <1375000>;
 428                                         regulator-always-on;
 429                                         anatop-reg-offset = <0x110>;
 430                                         anatop-vol-bit-shift = <8>;
 431                                         anatop-vol-bit-width = <5>;
 432                                         anatop-min-bit-val = <4>;
 433                                         anatop-min-voltage = <800000>;
 434                                         anatop-max-voltage = <1375000>;
 435                                 };
 436
 437                                 regulator-3p0@120 {
 438                                         compatible = "fsl,anatop-regulator";
 439                                         regulator-name = "vdd3p0";
 440                                         regulator-min-microvolt = <2800000>;
 441                                         regulator-max-microvolt = <3150000>;
 442                                         regulator-always-on;
 443                                         anatop-reg-offset = <0x120>;
 444                                         anatop-vol-bit-shift = <8>;
 445                                         anatop-vol-bit-width = <5>;
 446                                         anatop-min-bit-val = <0>;
 447                                         anatop-min-voltage = <2625000>;
 448                                         anatop-max-voltage = <3400000>;
 449                                 };
 450
 451                                 regulator-2p5@130 {
 452                                         compatible = "fsl,anatop-regulator";
 453                                         regulator-name = "vdd2p5";
 454                                         regulator-min-microvolt = <2100000>;
 455                                         regulator-max-microvolt = <2850000>;
 456                                         regulator-always-on;
 457                                         anatop-reg-offset = <0x130>;
 458                                         anatop-vol-bit-shift = <8>;
 459                                         anatop-vol-bit-width = <5>;
 460                                         anatop-min-bit-val = <0>;
 461                                         anatop-min-voltage = <2100000>;
 462                                         anatop-max-voltage = <2850000>;
 463                                 };
 464
 465                                 reg_arm: regulator-vddcore@140 {
 466                                         compatible = "fsl,anatop-regulator";
 467                                         regulator-name = "vddarm";
 468                                         regulator-min-microvolt = <725000>;
 469                                         regulator-max-microvolt = <1450000>;
 470                                         regulator-always-on;
 471                                         anatop-reg-offset = <0x140>;
 472                                         anatop-vol-bit-shift = <0>;
 473                                         anatop-vol-bit-width = <5>;
 474                                         anatop-delay-reg-offset = <0x170>;
 475                                         anatop-delay-bit-shift = <24>;
 476                                         anatop-delay-bit-width = <2>;
 477                                         anatop-min-bit-val = <1>;
 478                                         anatop-min-voltage = <725000>;
 479                                         anatop-max-voltage = <1450000>;
 480                                 };
 481
 482                                 reg_pu: regulator-vddpu@140 {
 483                                         compatible = "fsl,anatop-regulator";
 484                                         regulator-name = "vddpu";
 485                                         regulator-min-microvolt = <725000>;
 486                                         regulator-max-microvolt = <1450000>;
 487                                         regulator-always-on;
 488                                         anatop-reg-offset = <0x140>;
 489                                         anatop-vol-bit-shift = <9>;
 490                                         anatop-vol-bit-width = <5>;
 491                                         anatop-delay-reg-offset = <0x170>;
 492                                         anatop-delay-bit-shift = <26>;
 493                                         anatop-delay-bit-width = <2>;
 494                                         anatop-min-bit-val = <1>;
 495                                         anatop-min-voltage = <725000>;
 496                                         anatop-max-voltage = <1450000>;
 497                                 };
 498
 499                                 reg_soc: regulator-vddsoc@140 {
 500                                         compatible = "fsl,anatop-regulator";
 501                                         regulator-name = "vddsoc";
 502                                         regulator-min-microvolt = <725000>;
 503                                         regulator-max-microvolt = <1450000>;
 504                                         regulator-always-on;
 505                                         anatop-reg-offset = <0x140>;
 506                                         anatop-vol-bit-shift = <18>;
 507                                         anatop-vol-bit-width = <5>;
 508                                         anatop-delay-reg-offset = <0x170>;
 509                                         anatop-delay-bit-shift = <28>;
 510                                         anatop-delay-bit-width = <2>;
 511                                         anatop-min-bit-val = <1>;
 512                                         anatop-min-voltage = <725000>;
 513                                         anatop-max-voltage = <1450000>;
 514                                 };
 515                         };
 516
 517                         usbphy1: usbphy@020c9000 {
 518                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 519                                 reg = <0x020c9000 0x1000>;
 520                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 521                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 522                                 fsl,anatop = <&anatop>;
 523                         };
 524
 525                         usbphy2: usbphy@020ca000 {
 526                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 527                                 reg = <0x020ca000 0x1000>;
 528                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 529                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 530                                 fsl,anatop = <&anatop>;
 531                         };
 532
 533                         snvs@020cc000 {
 534                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 535                                 #address-cells = <1>;
 536                                 #size-cells = <1>;
 537                                 ranges = <0 0x020cc000 0x4000>;
 538
 539                                 snvs-rtc-lp@34 {
 540                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 541                                         reg = <0x34 0x58>;
 542                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 543                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 544                                 };
 545                         };
 546
 547                         epit1: epit@020d0000 {
 548                                 reg = <0x020d0000 0x4000>;
 549                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 550                         };
 551
 552                         epit2: epit@020d4000 {
 553                                 reg = <0x020d4000 0x4000>;
 554                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 555                         };
 556
 557                         src: src@020d8000 {
 558                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 559                                 reg = <0x020d8000 0x4000>;
 560                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 561                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 562                                 #reset-cells = <1>;
 563                         };
 564
 565                         gpc: gpc@020dc000 {
 566                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 567                                 reg = <0x020dc000 0x4000>;
 568                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 569                         };
 570
 571                         gpr: iomuxc-gpr@020e0000 {
 572                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 573                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 574                                 reg = <0x020e0000 0x38>;
 575                         };
 576
 577                         iomuxc: iomuxc@020e0000 {
 578                                 compatible = "fsl,imx6sl-iomuxc";
 579                                 reg = <0x020e0000 0x4000>;
 580                         };
 581
 582                         csi: csi@020e4000 {
 583                                 reg = <0x020e4000 0x4000>;
 584                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 585                         };
 586
 587                         spdc: spdc@020e8000 {
 588                                 reg = <0x020e8000 0x4000>;
 589                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 590                         };
 591
 592                         sdma: sdma@020ec000 {
 593                                 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
 594                                 reg = <0x020ec000 0x4000>;
 595                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 596                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 597                                          <&clks IMX6SL_CLK_SDMA>;
 598                                 clock-names = "ipg", "ahb";
 599                                 #dma-cells = <3>;
 600                                 /* imx6sl reuses imx6q sdma firmware */
 601                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 602                         };
 603
 604                         pxp: pxp@020f0000 {
 605                                 reg = <0x020f0000 0x4000>;
 606                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 607                         };
 608
 609                         epdc: epdc@020f4000 {
 610                                 reg = <0x020f4000 0x4000>;
 611                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 612                         };
 613
 614                         lcdif: lcdif@020f8000 {
 615                                 reg = <0x020f8000 0x4000>;
 616                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 617                         };
 618
 619                         dcp: dcp@020fc000 {
 620                                 reg = <0x020fc000 0x4000>;
 621                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 622                         };
 623                 };
 624
 625                 aips2: aips-bus@02100000 {
 626                         compatible = "fsl,aips-bus", "simple-bus";
 627                         #address-cells = <1>;
 628                         #size-cells = <1>;
 629                         reg = <0x02100000 0x100000>;
 630                         ranges;
 631
 632                         usbotg1: usb@02184000 {
 633                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 634                                 reg = <0x02184000 0x200>;
 635                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 637                                 fsl,usbphy = <&usbphy1>;
 638                                 fsl,usbmisc = <&usbmisc 0>;
 639                                 status = "disabled";
 640                         };
 641
 642                         usbotg2: usb@02184200 {
 643                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 644                                 reg = <0x02184200 0x200>;
 645                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 646                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 647                                 fsl,usbphy = <&usbphy2>;
 648                                 fsl,usbmisc = <&usbmisc 1>;
 649                                 status = "disabled";
 650                         };
 651
 652                         usbh: usb@02184400 {
 653                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 654                                 reg = <0x02184400 0x200>;
 655                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 656                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 657                                 fsl,usbmisc = <&usbmisc 2>;
 658                                 status = "disabled";
 659                         };
 660
 661                         usbmisc: usbmisc@02184800 {
 662                                 #index-cells = <1>;
 663                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 664                                 reg = <0x02184800 0x200>;
 665                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 666                         };
 667
 668                         fec: ethernet@02188000 {
 669                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 670                                 reg = <0x02188000 0x4000>;
 671                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 672                                 clocks = <&clks IMX6SL_CLK_ENET_REF>,
 673                                          <&clks IMX6SL_CLK_ENET_REF>;
 674                                 clock-names = "ipg", "ahb";
 675                                 status = "disabled";
 676                         };
 677
 678                         usdhc1: usdhc@02190000 {
 679                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 680                                 reg = <0x02190000 0x4000>;
 681                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 682                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 683                                          <&clks IMX6SL_CLK_USDHC1>,
 684                                          <&clks IMX6SL_CLK_USDHC1>;
 685                                 clock-names = "ipg", "ahb", "per";
 686                                 bus-width = <4>;
 687                                 status = "disabled";
 688                         };
 689
 690                         usdhc2: usdhc@02194000 {
 691                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 692                                 reg = <0x02194000 0x4000>;
 693                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 695                                          <&clks IMX6SL_CLK_USDHC2>,
 696                                          <&clks IMX6SL_CLK_USDHC2>;
 697                                 clock-names = "ipg", "ahb", "per";
 698                                 bus-width = <4>;
 699                                 status = "disabled";
 700                         };
 701
 702                         usdhc3: usdhc@02198000 {
 703                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 704                                 reg = <0x02198000 0x4000>;
 705                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 706                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 707                                          <&clks IMX6SL_CLK_USDHC3>,
 708                                          <&clks IMX6SL_CLK_USDHC3>;
 709                                 clock-names = "ipg", "ahb", "per";
 710                                 bus-width = <4>;
 711                                 status = "disabled";
 712                         };
 713
 714                         usdhc4: usdhc@0219c000 {
 715                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 716                                 reg = <0x0219c000 0x4000>;
 717                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 718                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 719                                          <&clks IMX6SL_CLK_USDHC4>,
 720                                          <&clks IMX6SL_CLK_USDHC4>;
 721                                 clock-names = "ipg", "ahb", "per";
 722                                 bus-width = <4>;
 723                                 status = "disabled";
 724                         };
 725
 726                         i2c1: i2c@021a0000 {
 727                                 #address-cells = <1>;
 728                                 #size-cells = <0>;
 729                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 730                                 reg = <0x021a0000 0x4000>;
 731                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 732                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 733                                 status = "disabled";
 734                         };
 735
 736                         i2c2: i2c@021a4000 {
 737                                 #address-cells = <1>;
 738                                 #size-cells = <0>;
 739                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 740                                 reg = <0x021a4000 0x4000>;
 741                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 743                                 status = "disabled";
 744                         };
 745
 746                         i2c3: i2c@021a8000 {
 747                                 #address-cells = <1>;
 748                                 #size-cells = <0>;
 749                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 750                                 reg = <0x021a8000 0x4000>;
 751                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 753                                 status = "disabled";
 754                         };
 755
 756                         mmdc: mmdc@021b0000 {
 757                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 758                                 reg = <0x021b0000 0x4000>;
 759                         };
 760
 761                         rngb: rngb@021b4000 {
 762                                 reg = <0x021b4000 0x4000>;
 763                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 764                         };
 765
 766                         weim: weim@021b8000 {
 767                                 reg = <0x021b8000 0x4000>;
 768                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 769                         };
 770
 771                         ocotp: ocotp@021bc000 {
 772                                 compatible = "fsl,imx6sl-ocotp";
 773                                 reg = <0x021bc000 0x4000>;
 774                         };
 775
 776                         audmux: audmux@021d8000 {
 777                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 778                                 reg = <0x021d8000 0x4000>;
 779                                 status = "disabled";
 780                         };
 781                 };
 782         };
 783 };