2 * Copyright 2016 Toradex AG
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 compatible = "pwm-backlight";
46 pwms = <&pwm1 0 5000000 0>;
49 reg_module_3v3: regulator-module-3v3 {
50 compatible = "regulator-fixed";
51 regulator-name = "+V3.3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
56 reg_module_3v3_avdd: regulator-module-3v3-avdd {
57 compatible = "regulator-fixed";
58 regulator-name = "+V3.3_AVDD_AUDIO";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
64 compatible = "simple-audio-card";
65 simple-audio-card,name = "imx7-sgtl5000";
66 simple-audio-card,format = "i2s";
67 simple-audio-card,bitclock-master = <&dailink_master>;
68 simple-audio-card,frame-master = <&dailink_master>;
69 simple-audio-card,cpu {
73 dailink_master: simple-audio-card,codec {
75 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
81 vref-supply = <®_DCDC3>;
85 vref-supply = <®_DCDC3>;
89 arm-supply = <®_DCDC2>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_enet1>;
95 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
96 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
97 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
98 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
99 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
100 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
101 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
102 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
103 assigned-clock-rates = <0>, <100000000>;
105 phy-supply = <®_LDO1>;
110 clock-frequency = <100000>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
116 compatible = "fsl,sgtl5000";
117 #sound-dai-cells = <0>;
119 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_sai1_mclk>;
122 VDDA-supply = <®_module_3v3_avdd>;
123 VDDIO-supply = <®_module_3v3>;
124 VDDD-supply = <®_DCDC3>;
128 compatible = "adi,ad7879-1";
130 interrupt-parent = <&gpio1>;
131 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
132 touchscreen-max-pressure = <4096>;
133 adi,resistance-plate-x = <120>;
134 adi,first-conversion-delay = /bits/ 8 <3>;
135 adi,acquisition-time = /bits/ 8 <1>;
136 adi,median-filter-size = /bits/ 8 <2>;
137 adi,averaging = /bits/ 8 <1>;
138 adi,conversion-interval = /bits/ 8 <255>;
142 compatible = "ricoh,rn5t567";
146 reg_DCDC1: DCDC1 { /* V1.0_SOC */
147 regulator-min-microvolt = <1000000>;
148 regulator-max-microvolt = <1100000>;
153 reg_DCDC2: DCDC2 { /* V1.1_ARM */
154 regulator-min-microvolt = <975000>;
155 regulator-max-microvolt = <1100000>;
160 reg_DCDC3: DCDC3 { /* V1.8 */
161 regulator-min-microvolt = <1800000>;
162 regulator-max-microvolt = <1800000>;
167 reg_DCDC4: DCDC4 { /* V1.35_DRAM */
168 regulator-min-microvolt = <1350000>;
169 regulator-max-microvolt = <1350000>;
174 reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <3300000>;
180 reg_LDO2: LDO2 { /* +V1.8_SD */
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <3300000>;
187 reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
188 regulator-min-microvolt = <3300000>;
189 regulator-max-microvolt = <3300000>;
194 reg_LDO4: LDO4 { /* V1.8_LPSR */
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <1800000>;
201 reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
202 regulator-min-microvolt = <3300000>;
203 regulator-max-microvolt = <3300000>;
212 clock-frequency = <100000>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c4>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_lcdif_dat
220 &pinctrl_lcdif_ctrl>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_pwm1>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_pwm2>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_pwm3>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_pwm4>;
244 vin-supply = <®_DCDC3>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_sai1>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
260 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
261 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart2>;
269 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
270 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_uart3>;
278 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
291 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
299 pinctrl_gpio1: gpio1-grp {
301 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
302 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
303 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
304 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */
305 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
306 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */
307 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
308 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
309 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
310 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */
311 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */
312 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
313 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
314 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
315 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
316 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
317 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
318 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
319 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
320 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
321 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
322 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
323 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
324 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
325 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
326 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
327 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */
328 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
329 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
330 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
331 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
332 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
333 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
334 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
335 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
336 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
337 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
338 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
339 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
340 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
341 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
342 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
343 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
344 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
348 pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
350 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
351 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */
352 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
353 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
354 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
355 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
356 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
357 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
358 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
359 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
360 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
361 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
362 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
366 pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
368 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
369 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
370 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
371 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
372 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */
373 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */
377 pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
379 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
380 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
384 pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
386 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
390 pinctrl_enet1: enet1grp {
392 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
393 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
394 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
395 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
396 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
398 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
399 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
400 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
401 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
402 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
403 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
407 pinctrl_ecspi3_cs: ecspi3-cs-grp {
409 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
413 pinctrl_ecspi3: ecspi3-grp {
415 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
416 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
417 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
421 pinctrl_flexcan2: flexcan2-grp {
423 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
424 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
428 pinctrl_gpmi_nand: gpmi-nand-grp {
430 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
431 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
432 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
433 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
434 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
435 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
436 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
437 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
438 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
439 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
440 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
441 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
442 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
443 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
444 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
448 pinctrl_i2c4: i2c4-grp {
450 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
451 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
455 pinctrl_lcdif_dat: lcdif-dat-grp {
457 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
458 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
459 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
460 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
461 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
462 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
463 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
464 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
465 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
466 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
467 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
468 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
469 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
470 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
471 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
472 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
473 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
474 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
478 pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
480 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
481 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
482 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
483 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
484 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
485 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
489 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
491 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
492 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
493 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
494 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
498 pinctrl_pwm1: pwm1-grp {
500 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
504 pinctrl_pwm2: pwm2-grp {
506 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
510 pinctrl_pwm3: pwm3-grp {
512 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
516 pinctrl_pwm4: pwm4-grp {
518 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
522 pinctrl_uart1: uart1-grp {
524 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
525 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
526 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
527 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
531 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
533 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
534 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
538 pinctrl_uart2: uart2-grp {
540 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
541 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
542 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
543 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
546 pinctrl_uart3: uart3-grp {
548 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
549 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
553 pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
555 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
559 pinctrl_usdhc1: usdhc1-grp {
561 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
562 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
563 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
564 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
565 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
566 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
570 pinctrl_sai1: sai1-grp {
572 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
573 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
574 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
575 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
579 pinctrl_sai1_mclk: sai1grp_mclk {
581 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
587 pinctrl-names = "default";
588 pinctrl-0 = <&pinctrl_gpio_lpsr>;
590 pinctrl_gpio_lpsr: gpio1-grp {
592 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
593 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
594 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
598 pinctrl_i2c1: i2c1-grp {
600 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
601 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
605 pinctrl_cd_usdhc1: usdhc1-cd-grp {
607 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
611 pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
613 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
614 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */