2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/power/imx7-power.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include "imx7d-pinfunc.h"
55 * The decompressor and also some bootloaders rely on a
56 * pre-existing /chosen node to be available to insert the
57 * command line and merge other ATAGS info.
58 * Also for U-Boot there must be a pre-existing /memory node.
61 memory { device_type = "memory"; reg = <0 0>; };
96 compatible = "arm,cortex-a7";
99 clock-frequency = <792000000>;
100 clock-latency = <61036>; /* two CLK32 periods */
101 clocks = <&clks IMX7D_CLK_ARM>;
106 compatible = "fixed-clock";
108 clock-frequency = <32768>;
109 clock-output-names = "ckil";
113 compatible = "fixed-clock";
115 clock-frequency = <24000000>;
116 clock-output-names = "osc";
120 #address-cells = <1>;
122 compatible = "simple-bus";
123 interrupt-parent = <&gpc>;
127 compatible = "arm,coresight-funnel", "arm,primecell";
128 reg = <0x30041000 0x1000>;
129 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
130 clock-names = "apb_pclk";
132 ca_funnel_ports: ports {
133 #address-cells = <1>;
136 /* funnel input ports */
139 ca_funnel_in_port0: endpoint {
141 remote-endpoint = <&etm0_out_port>;
145 /* funnel output port */
148 ca_funnel_out_port0: endpoint {
149 remote-endpoint = <&hugo_funnel_in_port0>;
153 /* the other input ports are not connect to anything */
158 compatible = "arm,coresight-etm3x", "arm,primecell";
159 reg = <0x3007c000 0x1000>;
161 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
162 clock-names = "apb_pclk";
165 etm0_out_port: endpoint {
166 remote-endpoint = <&ca_funnel_in_port0>;
172 compatible = "arm,coresight-funnel", "arm,primecell";
173 reg = <0x30083000 0x1000>;
174 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
175 clock-names = "apb_pclk";
178 #address-cells = <1>;
181 /* funnel input ports */
184 hugo_funnel_in_port0: endpoint {
186 remote-endpoint = <&ca_funnel_out_port0>;
192 hugo_funnel_in_port1: endpoint {
193 slave-mode; /* M4 input */
199 hugo_funnel_out_port0: endpoint {
200 remote-endpoint = <&etf_in_port>;
204 /* the other input ports are not connect to anything */
209 compatible = "arm,coresight-tmc", "arm,primecell";
210 reg = <0x30084000 0x1000>;
211 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
212 clock-names = "apb_pclk";
215 #address-cells = <1>;
220 etf_in_port: endpoint {
222 remote-endpoint = <&hugo_funnel_out_port0>;
228 etf_out_port: endpoint {
229 remote-endpoint = <&replicator_in_port0>;
236 compatible = "arm,coresight-tmc", "arm,primecell";
237 reg = <0x30086000 0x1000>;
238 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
239 clock-names = "apb_pclk";
242 etr_in_port: endpoint {
244 remote-endpoint = <&replicator_out_port1>;
250 compatible = "arm,coresight-tpiu", "arm,primecell";
251 reg = <0x30087000 0x1000>;
252 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
253 clock-names = "apb_pclk";
256 tpiu_in_port: endpoint {
258 remote-endpoint = <&replicator_out_port1>;
265 * non-configurable replicators don't show up on the
266 * AMBA bus. As such no need to add "arm,primecell"
268 compatible = "arm,coresight-replicator";
271 #address-cells = <1>;
274 /* replicator output ports */
277 replicator_out_port0: endpoint {
278 remote-endpoint = <&tpiu_in_port>;
284 replicator_out_port1: endpoint {
285 remote-endpoint = <&etr_in_port>;
289 /* replicator input port */
292 replicator_in_port0: endpoint {
294 remote-endpoint = <&etf_out_port>;
300 intc: interrupt-controller@31001000 {
301 compatible = "arm,cortex-a7-gic";
302 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
303 #interrupt-cells = <3>;
304 interrupt-controller;
305 interrupt-parent = <&intc>;
306 reg = <0x31001000 0x1000>,
313 compatible = "arm,armv7-timer";
314 interrupt-parent = <&intc>;
315 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
316 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
317 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
318 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
321 aips1: aips-bus@30000000 {
322 compatible = "fsl,aips-bus", "simple-bus";
323 #address-cells = <1>;
325 reg = <0x30000000 0x400000>;
328 gpio1: gpio@30200000 {
329 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
330 reg = <0x30200000 0x10000>;
331 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
332 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
340 gpio2: gpio@30210000 {
341 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
342 reg = <0x30210000 0x10000>;
343 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 gpio-ranges = <&iomuxc 0 13 32>;
352 gpio3: gpio@30220000 {
353 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
354 reg = <0x30220000 0x10000>;
355 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 gpio-ranges = <&iomuxc 0 45 29>;
364 gpio4: gpio@30230000 {
365 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
366 reg = <0x30230000 0x10000>;
367 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 gpio-ranges = <&iomuxc 0 74 24>;
376 gpio5: gpio@30240000 {
377 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
378 reg = <0x30240000 0x10000>;
379 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
385 gpio-ranges = <&iomuxc 0 98 18>;
388 gpio6: gpio@30250000 {
389 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
390 reg = <0x30250000 0x10000>;
391 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 gpio-ranges = <&iomuxc 0 116 23>;
400 gpio7: gpio@30260000 {
401 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
402 reg = <0x30260000 0x10000>;
403 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 gpio-ranges = <&iomuxc 0 139 16>;
412 wdog1: wdog@30280000 {
413 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
414 reg = <0x30280000 0x10000>;
415 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
419 wdog2: wdog@30290000 {
420 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
421 reg = <0x30290000 0x10000>;
422 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
427 wdog3: wdog@302a0000 {
428 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
429 reg = <0x302a0000 0x10000>;
430 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
435 wdog4: wdog@302b0000 {
436 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
437 reg = <0x302b0000 0x10000>;
438 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
443 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
444 compatible = "fsl,imx7d-iomuxc-lpsr";
445 reg = <0x302c0000 0x10000>;
446 fsl,input-sel = <&iomuxc>;
450 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
451 reg = <0x302d0000 0x10000>;
452 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX7D_CLK_DUMMY>,
454 <&clks IMX7D_GPT1_ROOT_CLK>;
455 clock-names = "ipg", "per";
459 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
460 reg = <0x302e0000 0x10000>;
461 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX7D_CLK_DUMMY>,
463 <&clks IMX7D_GPT2_ROOT_CLK>;
464 clock-names = "ipg", "per";
469 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
470 reg = <0x302f0000 0x10000>;
471 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clks IMX7D_CLK_DUMMY>,
473 <&clks IMX7D_GPT3_ROOT_CLK>;
474 clock-names = "ipg", "per";
479 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
480 reg = <0x30300000 0x10000>;
481 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clks IMX7D_CLK_DUMMY>,
483 <&clks IMX7D_GPT4_ROOT_CLK>;
484 clock-names = "ipg", "per";
488 iomuxc: iomuxc@30330000 {
489 compatible = "fsl,imx7d-iomuxc";
490 reg = <0x30330000 0x10000>;
493 gpr: iomuxc-gpr@30340000 {
494 compatible = "fsl,imx7d-iomuxc-gpr",
495 "fsl,imx6q-iomuxc-gpr", "syscon";
496 reg = <0x30340000 0x10000>;
499 ocotp: ocotp-ctrl@30350000 {
500 compatible = "fsl,imx7d-ocotp", "syscon";
501 reg = <0x30350000 0x10000>;
502 clocks = <&clks IMX7D_OCOTP_CLK>;
505 anatop: anatop@30360000 {
506 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
507 "syscon", "simple-bus";
508 reg = <0x30360000 0x10000>;
509 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
512 reg_1p0d: regulator-vdd1p0d {
513 compatible = "fsl,anatop-regulator";
514 regulator-name = "vdd1p0d";
515 regulator-min-microvolt = <800000>;
516 regulator-max-microvolt = <1200000>;
517 anatop-reg-offset = <0x210>;
518 anatop-vol-bit-shift = <8>;
519 anatop-vol-bit-width = <5>;
520 anatop-min-bit-val = <8>;
521 anatop-min-voltage = <800000>;
522 anatop-max-voltage = <1200000>;
523 anatop-enable-bit = <0>;
527 snvs: snvs@30370000 {
528 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
529 reg = <0x30370000 0x10000>;
531 snvs_rtc: snvs-rtc-lp {
532 compatible = "fsl,sec-v4.0-mon-rtc-lp";
535 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
539 snvs_poweroff: snvs-poweroff {
540 compatible = "syscon-poweroff";
546 snvs_pwrkey: snvs-powerkey {
547 compatible = "fsl,sec-v4.0-pwrkey";
549 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
550 linux,keycode = <KEY_POWER>;
556 compatible = "fsl,imx7d-ccm";
557 reg = <0x30380000 0x10000>;
558 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ckil>, <&osc>;
562 clock-names = "ckil", "osc";
566 compatible = "fsl,imx7d-src", "syscon";
567 reg = <0x30390000 0x10000>;
568 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
573 compatible = "fsl,imx7d-gpc";
574 reg = <0x303a0000 0x10000>;
575 interrupt-controller;
576 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
577 #interrupt-cells = <3>;
578 interrupt-parent = <&intc>;
579 #power-domain-cells = <1>;
582 #address-cells = <1>;
585 pgc_pcie_phy: pgc-power-domain@IMX7_POWER_DOMAIN_PCIE_PHY {
586 #power-domain-cells = <0>;
587 reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
588 power-supply = <®_1p0d>;
594 aips2: aips-bus@30400000 {
595 compatible = "fsl,aips-bus", "simple-bus";
596 #address-cells = <1>;
598 reg = <0x30400000 0x400000>;
602 compatible = "fsl,imx7d-adc";
603 reg = <0x30610000 0x10000>;
604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
611 compatible = "fsl,imx7d-adc";
612 reg = <0x30620000 0x10000>;
613 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
619 ecspi4: ecspi@30630000 {
620 #address-cells = <1>;
622 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
623 reg = <0x30630000 0x10000>;
624 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
626 <&clks IMX7D_ECSPI4_ROOT_CLK>;
627 clock-names = "ipg", "per";
632 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
633 reg = <0x30660000 0x10000>;
634 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
636 <&clks IMX7D_PWM1_ROOT_CLK>;
637 clock-names = "ipg", "per";
643 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
644 reg = <0x30670000 0x10000>;
645 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
647 <&clks IMX7D_PWM2_ROOT_CLK>;
648 clock-names = "ipg", "per";
654 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
655 reg = <0x30680000 0x10000>;
656 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
658 <&clks IMX7D_PWM3_ROOT_CLK>;
659 clock-names = "ipg", "per";
665 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
666 reg = <0x30690000 0x10000>;
667 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
669 <&clks IMX7D_PWM4_ROOT_CLK>;
670 clock-names = "ipg", "per";
675 lcdif: lcdif@30730000 {
676 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
677 reg = <0x30730000 0x10000>;
678 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
680 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
681 clock-names = "pix", "axi";
686 aips3: aips-bus@30800000 {
687 compatible = "fsl,aips-bus", "simple-bus";
688 #address-cells = <1>;
690 reg = <0x30800000 0x400000>;
693 ecspi1: ecspi@30820000 {
694 #address-cells = <1>;
696 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
697 reg = <0x30820000 0x10000>;
698 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
700 <&clks IMX7D_ECSPI1_ROOT_CLK>;
701 clock-names = "ipg", "per";
705 ecspi2: ecspi@30830000 {
706 #address-cells = <1>;
708 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
709 reg = <0x30830000 0x10000>;
710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
712 <&clks IMX7D_ECSPI2_ROOT_CLK>;
713 clock-names = "ipg", "per";
717 ecspi3: ecspi@30840000 {
718 #address-cells = <1>;
720 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
721 reg = <0x30840000 0x10000>;
722 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
724 <&clks IMX7D_ECSPI3_ROOT_CLK>;
725 clock-names = "ipg", "per";
729 uart1: serial@30860000 {
730 compatible = "fsl,imx7d-uart",
732 reg = <0x30860000 0x10000>;
733 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
735 <&clks IMX7D_UART1_ROOT_CLK>;
736 clock-names = "ipg", "per";
740 uart2: serial@30890000 {
741 compatible = "fsl,imx7d-uart",
743 reg = <0x30890000 0x10000>;
744 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
746 <&clks IMX7D_UART2_ROOT_CLK>;
747 clock-names = "ipg", "per";
751 uart3: serial@30880000 {
752 compatible = "fsl,imx7d-uart",
754 reg = <0x30880000 0x10000>;
755 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
757 <&clks IMX7D_UART3_ROOT_CLK>;
758 clock-names = "ipg", "per";
763 #sound-dai-cells = <0>;
764 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
765 reg = <0x308a0000 0x10000>;
766 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
768 <&clks IMX7D_SAI1_ROOT_CLK>,
769 <&clks IMX7D_CLK_DUMMY>,
770 <&clks IMX7D_CLK_DUMMY>;
771 clock-names = "bus", "mclk1", "mclk2", "mclk3";
772 dma-names = "rx", "tx";
773 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
778 #sound-dai-cells = <0>;
779 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
780 reg = <0x308b0000 0x10000>;
781 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
783 <&clks IMX7D_SAI2_ROOT_CLK>,
784 <&clks IMX7D_CLK_DUMMY>,
785 <&clks IMX7D_CLK_DUMMY>;
786 clock-names = "bus", "mclk1", "mclk2", "mclk3";
787 dma-names = "rx", "tx";
788 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
793 #sound-dai-cells = <0>;
794 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
795 reg = <0x308c0000 0x10000>;
796 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
798 <&clks IMX7D_SAI3_ROOT_CLK>,
799 <&clks IMX7D_CLK_DUMMY>,
800 <&clks IMX7D_CLK_DUMMY>;
801 clock-names = "bus", "mclk1", "mclk2", "mclk3";
802 dma-names = "rx", "tx";
803 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
807 flexcan1: can@30a00000 {
808 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
809 reg = <0x30a00000 0x10000>;
810 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX7D_CLK_DUMMY>,
812 <&clks IMX7D_CAN1_ROOT_CLK>;
813 clock-names = "ipg", "per";
817 flexcan2: can@30a10000 {
818 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
819 reg = <0x30a10000 0x10000>;
820 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&clks IMX7D_CLK_DUMMY>,
822 <&clks IMX7D_CAN2_ROOT_CLK>;
823 clock-names = "ipg", "per";
828 #address-cells = <1>;
830 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
831 reg = <0x30a20000 0x10000>;
832 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
838 #address-cells = <1>;
840 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
841 reg = <0x30a30000 0x10000>;
842 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
848 #address-cells = <1>;
850 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
851 reg = <0x30a40000 0x10000>;
852 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
858 #address-cells = <1>;
860 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
861 reg = <0x30a50000 0x10000>;
862 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
867 uart4: serial@30a60000 {
868 compatible = "fsl,imx7d-uart",
870 reg = <0x30a60000 0x10000>;
871 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
873 <&clks IMX7D_UART4_ROOT_CLK>;
874 clock-names = "ipg", "per";
878 uart5: serial@30a70000 {
879 compatible = "fsl,imx7d-uart",
881 reg = <0x30a70000 0x10000>;
882 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
884 <&clks IMX7D_UART5_ROOT_CLK>;
885 clock-names = "ipg", "per";
889 uart6: serial@30a80000 {
890 compatible = "fsl,imx7d-uart",
892 reg = <0x30a80000 0x10000>;
893 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
895 <&clks IMX7D_UART6_ROOT_CLK>;
896 clock-names = "ipg", "per";
900 uart7: serial@30a90000 {
901 compatible = "fsl,imx7d-uart",
903 reg = <0x30a90000 0x10000>;
904 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
906 <&clks IMX7D_UART7_ROOT_CLK>;
907 clock-names = "ipg", "per";
911 usbotg1: usb@30b10000 {
912 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
913 reg = <0x30b10000 0x200>;
914 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&clks IMX7D_USB_CTRL_CLK>;
916 fsl,usbphy = <&usbphynop1>;
917 fsl,usbmisc = <&usbmisc1 0>;
918 phy-clkgate-delay-us = <400>;
923 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
924 reg = <0x30b30000 0x200>;
925 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX7D_USB_CTRL_CLK>;
927 fsl,usbphy = <&usbphynop3>;
928 fsl,usbmisc = <&usbmisc3 0>;
931 phy-clkgate-delay-us = <400>;
935 usbmisc1: usbmisc@30b10200 {
937 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
938 reg = <0x30b10200 0x200>;
941 usbmisc3: usbmisc@30b30200 {
943 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
944 reg = <0x30b30200 0x200>;
947 usbphynop1: usbphynop1 {
948 compatible = "usb-nop-xceiv";
949 clocks = <&clks IMX7D_USB_PHY1_CLK>;
950 clock-names = "main_clk";
953 usbphynop3: usbphynop3 {
954 compatible = "usb-nop-xceiv";
955 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
956 clock-names = "main_clk";
959 usdhc1: usdhc@30b40000 {
960 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
961 reg = <0x30b40000 0x10000>;
962 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
964 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
965 <&clks IMX7D_USDHC1_ROOT_CLK>;
966 clock-names = "ipg", "ahb", "per";
971 usdhc2: usdhc@30b50000 {
972 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
973 reg = <0x30b50000 0x10000>;
974 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
976 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
977 <&clks IMX7D_USDHC2_ROOT_CLK>;
978 clock-names = "ipg", "ahb", "per";
983 usdhc3: usdhc@30b60000 {
984 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
985 reg = <0x30b60000 0x10000>;
986 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
988 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
989 <&clks IMX7D_USDHC3_ROOT_CLK>;
990 clock-names = "ipg", "ahb", "per";
995 sdma: sdma@30bd0000 {
996 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
997 reg = <0x30bd0000 0x10000>;
998 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1000 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1001 clock-names = "ipg", "ahb";
1003 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1006 fec1: ethernet@30be0000 {
1007 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1008 reg = <0x30be0000 0x10000>;
1009 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1013 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1014 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1015 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1016 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1017 clock-names = "ipg", "ahb", "ptp",
1018 "enet_clk_ref", "enet_out";
1019 fsl,num-tx-queues=<3>;
1020 fsl,num-rx-queues=<3>;
1021 status = "disabled";