arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&wakeupgen>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,cortex-a15-pmu";
  87                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  89         };
  90
  91         gic: interrupt-controller@48211000 {
  92                 compatible = "arm,cortex-a15-gic";
  93                 interrupt-controller;
  94                 #interrupt-cells = <3>;
  95                 reg = <0x48211000 0x1000>,
  96                       <0x48212000 0x1000>,
  97                       <0x48214000 0x2000>,
  98                       <0x48216000 0x2000>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         wakeupgen: interrupt-controller@48281000 {
 103                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0x48281000 0x1000>;
 107                 interrupt-parent = <&gic>;
 108         };
 109
 110         /*
 111          * The soc node represents the soc top level view. It is used for IPs
 112          * that are not memory mapped in the MPU view or for the MPU itself.
 113          */
 114         soc {
 115                 compatible = "ti,omap-infra";
 116                 mpu {
 117                         compatible = "ti,omap4-mpu";
 118                         ti,hwmods = "mpu";
 119                         sram = <&ocmcram>;
 120                 };
 121         };
 122
 123         /*
 124          * XXX: Use a flat representation of the OMAP3 interconnect.
 125          * The real OMAP interconnect network is quite complex.
 126          * Since it will not bring real advantage to represent that in DT for
 127          * the moment, just use a fake OCP bus entry to represent the whole bus
 128          * hierarchy.
 129          */
 130         ocp {
 131                 compatible = "ti,omap4-l3-noc", "simple-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 136                 reg = <0x44000000 0x2000>,
 137                       <0x44800000 0x3000>,
 138                       <0x45000000 0x4000>;
 139                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 141
 142                 prm: prm@4ae06000 {
 143                         compatible = "ti,omap5-prm";
 144                         reg = <0x4ae06000 0x3000>;
 145                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 146
 147                         prm_clocks: clocks {
 148                                 #address-cells = <1>;
 149                                 #size-cells = <0>;
 150                         };
 151
 152                         prm_clockdomains: clockdomains {
 153                         };
 154                 };
 155
 156                 cm_core_aon: cm_core_aon@4a004000 {
 157                         compatible = "ti,omap5-cm-core-aon";
 158                         reg = <0x4a004000 0x2000>;
 159
 160                         cm_core_aon_clocks: clocks {
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                         };
 164
 165                         cm_core_aon_clockdomains: clockdomains {
 166                         };
 167                 };
 168
 169                 scrm: scrm@4ae0a000 {
 170                         compatible = "ti,omap5-scrm";
 171                         reg = <0x4ae0a000 0x2000>;
 172
 173                         scrm_clocks: clocks {
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176                         };
 177
 178                         scrm_clockdomains: clockdomains {
 179                         };
 180                 };
 181
 182                 cm_core: cm_core@4a008000 {
 183                         compatible = "ti,omap5-cm-core";
 184                         reg = <0x4a008000 0x3000>;
 185
 186                         cm_core_clocks: clocks {
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189                         };
 190
 191                         cm_core_clockdomains: clockdomains {
 192                         };
 193                 };
 194
 195                 counter32k: counter@4ae04000 {
 196                         compatible = "ti,omap-counter32k";
 197                         reg = <0x4ae04000 0x40>;
 198                         ti,hwmods = "counter_32k";
 199                 };
 200
 201                 omap5_pmx_core: pinmux@4a002840 {
 202                         compatible = "ti,omap5-padconf", "pinctrl-single";
 203                         reg = <0x4a002840 0x01b6>;
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         #interrupt-cells = <1>;
 207                         interrupt-controller;
 208                         pinctrl-single,register-width = <16>;
 209                         pinctrl-single,function-mask = <0x7fff>;
 210                 };
 211                 omap5_pmx_wkup: pinmux@4ae0c840 {
 212                         compatible = "ti,omap5-padconf", "pinctrl-single";
 213                         reg = <0x4ae0c840 0x0038>;
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         #interrupt-cells = <1>;
 217                         interrupt-controller;
 218                         pinctrl-single,register-width = <16>;
 219                         pinctrl-single,function-mask = <0x7fff>;
 220                 };
 221
 222                 omap5_padconf_global: tisyscon@4a002da0 {
 223                         compatible = "syscon";
 224                         reg = <0x4A002da0 0xec>;
 225                 };
 226
 227                 pbias_regulator: pbias_regulator {
 228                         compatible = "ti,pbias-omap";
 229                         reg = <0x60 0x4>;
 230                         syscon = <&omap5_padconf_global>;
 231                         pbias_mmc_reg: pbias_mmc_omap5 {
 232                                 regulator-name = "pbias_mmc_omap5";
 233                                 regulator-min-microvolt = <1800000>;
 234                                 regulator-max-microvolt = <3000000>;
 235                         };
 236                 };
 237
 238                 ocmcram: ocmcram@40300000 {
 239                         compatible = "mmio-sram";
 240                         reg = <0x40300000 0x20000>; /* 128k */
 241                 };
 242
 243                 sdma: dma-controller@4a056000 {
 244                         compatible = "ti,omap4430-sdma";
 245                         reg = <0x4a056000 0x1000>;
 246                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 250                         #dma-cells = <1>;
 251                         dma-channels = <32>;
 252                         dma-requests = <127>;
 253                 };
 254
 255                 gpio1: gpio@4ae10000 {
 256                         compatible = "ti,omap4-gpio";
 257                         reg = <0x4ae10000 0x200>;
 258                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 259                         ti,hwmods = "gpio1";
 260                         ti,gpio-always-on;
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <2>;
 265                 };
 266
 267                 gpio2: gpio@48055000 {
 268                         compatible = "ti,omap4-gpio";
 269                         reg = <0x48055000 0x200>;
 270                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 271                         ti,hwmods = "gpio2";
 272                         gpio-controller;
 273                         #gpio-cells = <2>;
 274                         interrupt-controller;
 275                         #interrupt-cells = <2>;
 276                 };
 277
 278                 gpio3: gpio@48057000 {
 279                         compatible = "ti,omap4-gpio";
 280                         reg = <0x48057000 0x200>;
 281                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 282                         ti,hwmods = "gpio3";
 283                         gpio-controller;
 284                         #gpio-cells = <2>;
 285                         interrupt-controller;
 286                         #interrupt-cells = <2>;
 287                 };
 288
 289                 gpio4: gpio@48059000 {
 290                         compatible = "ti,omap4-gpio";
 291                         reg = <0x48059000 0x200>;
 292                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 293                         ti,hwmods = "gpio4";
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296                         interrupt-controller;
 297                         #interrupt-cells = <2>;
 298                 };
 299
 300                 gpio5: gpio@4805b000 {
 301                         compatible = "ti,omap4-gpio";
 302                         reg = <0x4805b000 0x200>;
 303                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 304                         ti,hwmods = "gpio5";
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                         interrupt-controller;
 308                         #interrupt-cells = <2>;
 309                 };
 310
 311                 gpio6: gpio@4805d000 {
 312                         compatible = "ti,omap4-gpio";
 313                         reg = <0x4805d000 0x200>;
 314                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 315                         ti,hwmods = "gpio6";
 316                         gpio-controller;
 317                         #gpio-cells = <2>;
 318                         interrupt-controller;
 319                         #interrupt-cells = <2>;
 320                 };
 321
 322                 gpio7: gpio@48051000 {
 323                         compatible = "ti,omap4-gpio";
 324                         reg = <0x48051000 0x200>;
 325                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 326                         ti,hwmods = "gpio7";
 327                         gpio-controller;
 328                         #gpio-cells = <2>;
 329                         interrupt-controller;
 330                         #interrupt-cells = <2>;
 331                 };
 332
 333                 gpio8: gpio@48053000 {
 334                         compatible = "ti,omap4-gpio";
 335                         reg = <0x48053000 0x200>;
 336                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 337                         ti,hwmods = "gpio8";
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343
 344                 gpmc: gpmc@50000000 {
 345                         compatible = "ti,omap4430-gpmc";
 346                         reg = <0x50000000 0x1000>;
 347                         #address-cells = <2>;
 348                         #size-cells = <1>;
 349                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 350                         gpmc,num-cs = <8>;
 351                         gpmc,num-waitpins = <4>;
 352                         ti,hwmods = "gpmc";
 353                         clocks = <&l3_iclk_div>;
 354                         clock-names = "fck";
 355                 };
 356
 357                 i2c1: i2c@48070000 {
 358                         compatible = "ti,omap4-i2c";
 359                         reg = <0x48070000 0x100>;
 360                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         ti,hwmods = "i2c1";
 364                 };
 365
 366                 i2c2: i2c@48072000 {
 367                         compatible = "ti,omap4-i2c";
 368                         reg = <0x48072000 0x100>;
 369                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         ti,hwmods = "i2c2";
 373                 };
 374
 375                 i2c3: i2c@48060000 {
 376                         compatible = "ti,omap4-i2c";
 377                         reg = <0x48060000 0x100>;
 378                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         ti,hwmods = "i2c3";
 382                 };
 383
 384                 i2c4: i2c@4807a000 {
 385                         compatible = "ti,omap4-i2c";
 386                         reg = <0x4807a000 0x100>;
 387                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         ti,hwmods = "i2c4";
 391                 };
 392
 393                 i2c5: i2c@4807c000 {
 394                         compatible = "ti,omap4-i2c";
 395                         reg = <0x4807c000 0x100>;
 396                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         ti,hwmods = "i2c5";
 400                 };
 401
 402                 hwspinlock: spinlock@4a0f6000 {
 403                         compatible = "ti,omap4-hwspinlock";
 404                         reg = <0x4a0f6000 0x1000>;
 405                         ti,hwmods = "spinlock";
 406                         #hwlock-cells = <1>;
 407                 };
 408
 409                 mcspi1: spi@48098000 {
 410                         compatible = "ti,omap4-mcspi";
 411                         reg = <0x48098000 0x200>;
 412                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         ti,hwmods = "mcspi1";
 416                         ti,spi-num-cs = <4>;
 417                         dmas = <&sdma 35>,
 418                                <&sdma 36>,
 419                                <&sdma 37>,
 420                                <&sdma 38>,
 421                                <&sdma 39>,
 422                                <&sdma 40>,
 423                                <&sdma 41>,
 424                                <&sdma 42>;
 425                         dma-names = "tx0", "rx0", "tx1", "rx1",
 426                                     "tx2", "rx2", "tx3", "rx3";
 427                 };
 428
 429                 mcspi2: spi@4809a000 {
 430                         compatible = "ti,omap4-mcspi";
 431                         reg = <0x4809a000 0x200>;
 432                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         ti,hwmods = "mcspi2";
 436                         ti,spi-num-cs = <2>;
 437                         dmas = <&sdma 43>,
 438                                <&sdma 44>,
 439                                <&sdma 45>,
 440                                <&sdma 46>;
 441                         dma-names = "tx0", "rx0", "tx1", "rx1";
 442                 };
 443
 444                 mcspi3: spi@480b8000 {
 445                         compatible = "ti,omap4-mcspi";
 446                         reg = <0x480b8000 0x200>;
 447                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         ti,hwmods = "mcspi3";
 451                         ti,spi-num-cs = <2>;
 452                         dmas = <&sdma 15>, <&sdma 16>;
 453                         dma-names = "tx0", "rx0";
 454                 };
 455
 456                 mcspi4: spi@480ba000 {
 457                         compatible = "ti,omap4-mcspi";
 458                         reg = <0x480ba000 0x200>;
 459                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         ti,hwmods = "mcspi4";
 463                         ti,spi-num-cs = <1>;
 464                         dmas = <&sdma 70>, <&sdma 71>;
 465                         dma-names = "tx0", "rx0";
 466                 };
 467
 468                 uart1: serial@4806a000 {
 469                         compatible = "ti,omap4-uart";
 470                         reg = <0x4806a000 0x100>;
 471                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 472                         ti,hwmods = "uart1";
 473                         clock-frequency = <48000000>;
 474                 };
 475
 476                 uart2: serial@4806c000 {
 477                         compatible = "ti,omap4-uart";
 478                         reg = <0x4806c000 0x100>;
 479                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 480                         ti,hwmods = "uart2";
 481                         clock-frequency = <48000000>;
 482                 };
 483
 484                 uart3: serial@48020000 {
 485                         compatible = "ti,omap4-uart";
 486                         reg = <0x48020000 0x100>;
 487                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 488                         ti,hwmods = "uart3";
 489                         clock-frequency = <48000000>;
 490                 };
 491
 492                 uart4: serial@4806e000 {
 493                         compatible = "ti,omap4-uart";
 494                         reg = <0x4806e000 0x100>;
 495                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 496                         ti,hwmods = "uart4";
 497                         clock-frequency = <48000000>;
 498                 };
 499
 500                 uart5: serial@48066000 {
 501                         compatible = "ti,omap4-uart";
 502                         reg = <0x48066000 0x100>;
 503                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 504                         ti,hwmods = "uart5";
 505                         clock-frequency = <48000000>;
 506                 };
 507
 508                 uart6: serial@48068000 {
 509                         compatible = "ti,omap4-uart";
 510                         reg = <0x48068000 0x100>;
 511                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 512                         ti,hwmods = "uart6";
 513                         clock-frequency = <48000000>;
 514                 };
 515
 516                 mmc1: mmc@4809c000 {
 517                         compatible = "ti,omap4-hsmmc";
 518                         reg = <0x4809c000 0x400>;
 519                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mmc1";
 521                         ti,dual-volt;
 522                         ti,needs-special-reset;
 523                         dmas = <&sdma 61>, <&sdma 62>;
 524                         dma-names = "tx", "rx";
 525                         pbias-supply = <&pbias_mmc_reg>;
 526                 };
 527
 528                 mmc2: mmc@480b4000 {
 529                         compatible = "ti,omap4-hsmmc";
 530                         reg = <0x480b4000 0x400>;
 531                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 532                         ti,hwmods = "mmc2";
 533                         ti,needs-special-reset;
 534                         dmas = <&sdma 47>, <&sdma 48>;
 535                         dma-names = "tx", "rx";
 536                 };
 537
 538                 mmc3: mmc@480ad000 {
 539                         compatible = "ti,omap4-hsmmc";
 540                         reg = <0x480ad000 0x400>;
 541                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 542                         ti,hwmods = "mmc3";
 543                         ti,needs-special-reset;
 544                         dmas = <&sdma 77>, <&sdma 78>;
 545                         dma-names = "tx", "rx";
 546                 };
 547
 548                 mmc4: mmc@480d1000 {
 549                         compatible = "ti,omap4-hsmmc";
 550                         reg = <0x480d1000 0x400>;
 551                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 552                         ti,hwmods = "mmc4";
 553                         ti,needs-special-reset;
 554                         dmas = <&sdma 57>, <&sdma 58>;
 555                         dma-names = "tx", "rx";
 556                 };
 557
 558                 mmc5: mmc@480d5000 {
 559                         compatible = "ti,omap4-hsmmc";
 560                         reg = <0x480d5000 0x400>;
 561                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "mmc5";
 563                         ti,needs-special-reset;
 564                         dmas = <&sdma 59>, <&sdma 60>;
 565                         dma-names = "tx", "rx";
 566                 };
 567
 568                 mmu_dsp: mmu@4a066000 {
 569                         compatible = "ti,omap4-iommu";
 570                         reg = <0x4a066000 0x100>;
 571                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 572                         ti,hwmods = "mmu_dsp";
 573                 };
 574
 575                 mmu_ipu: mmu@55082000 {
 576                         compatible = "ti,omap4-iommu";
 577                         reg = <0x55082000 0x100>;
 578                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 579                         ti,hwmods = "mmu_ipu";
 580                         ti,iommu-bus-err-back;
 581                 };
 582
 583                 keypad: keypad@4ae1c000 {
 584                         compatible = "ti,omap4-keypad";
 585                         reg = <0x4ae1c000 0x400>;
 586                         ti,hwmods = "kbd";
 587                 };
 588
 589                 mcpdm: mcpdm@40132000 {
 590                         compatible = "ti,omap4-mcpdm";
 591                         reg = <0x40132000 0x7f>, /* MPU private access */
 592                               <0x49032000 0x7f>; /* L3 Interconnect */
 593                         reg-names = "mpu", "dma";
 594                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 595                         ti,hwmods = "mcpdm";
 596                         dmas = <&sdma 65>,
 597                                <&sdma 66>;
 598                         dma-names = "up_link", "dn_link";
 599                         status = "disabled";
 600                 };
 601
 602                 dmic: dmic@4012e000 {
 603                         compatible = "ti,omap4-dmic";
 604                         reg = <0x4012e000 0x7f>, /* MPU private access */
 605                               <0x4902e000 0x7f>; /* L3 Interconnect */
 606                         reg-names = "mpu", "dma";
 607                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 608                         ti,hwmods = "dmic";
 609                         dmas = <&sdma 67>;
 610                         dma-names = "up_link";
 611                         status = "disabled";
 612                 };
 613
 614                 mcbsp1: mcbsp@40122000 {
 615                         compatible = "ti,omap4-mcbsp";
 616                         reg = <0x40122000 0xff>, /* MPU private access */
 617                               <0x49022000 0xff>; /* L3 Interconnect */
 618                         reg-names = "mpu", "dma";
 619                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 620                         interrupt-names = "common";
 621                         ti,buffer-size = <128>;
 622                         ti,hwmods = "mcbsp1";
 623                         dmas = <&sdma 33>,
 624                                <&sdma 34>;
 625                         dma-names = "tx", "rx";
 626                         status = "disabled";
 627                 };
 628
 629                 mcbsp2: mcbsp@40124000 {
 630                         compatible = "ti,omap4-mcbsp";
 631                         reg = <0x40124000 0xff>, /* MPU private access */
 632                               <0x49024000 0xff>; /* L3 Interconnect */
 633                         reg-names = "mpu", "dma";
 634                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 635                         interrupt-names = "common";
 636                         ti,buffer-size = <128>;
 637                         ti,hwmods = "mcbsp2";
 638                         dmas = <&sdma 17>,
 639                                <&sdma 18>;
 640                         dma-names = "tx", "rx";
 641                         status = "disabled";
 642                 };
 643
 644                 mcbsp3: mcbsp@40126000 {
 645                         compatible = "ti,omap4-mcbsp";
 646                         reg = <0x40126000 0xff>, /* MPU private access */
 647                               <0x49026000 0xff>; /* L3 Interconnect */
 648                         reg-names = "mpu", "dma";
 649                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 650                         interrupt-names = "common";
 651                         ti,buffer-size = <128>;
 652                         ti,hwmods = "mcbsp3";
 653                         dmas = <&sdma 19>,
 654                                <&sdma 20>;
 655                         dma-names = "tx", "rx";
 656                         status = "disabled";
 657                 };
 658
 659                 mailbox: mailbox@4a0f4000 {
 660                         compatible = "ti,omap4-mailbox";
 661                         reg = <0x4a0f4000 0x200>;
 662                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 663                         ti,hwmods = "mailbox";
 664                         #mbox-cells = <1>;
 665                         ti,mbox-num-users = <3>;
 666                         ti,mbox-num-fifos = <8>;
 667                         mbox_ipu: mbox_ipu {
 668                                 ti,mbox-tx = <0 0 0>;
 669                                 ti,mbox-rx = <1 0 0>;
 670                         };
 671                         mbox_dsp: mbox_dsp {
 672                                 ti,mbox-tx = <3 0 0>;
 673                                 ti,mbox-rx = <2 0 0>;
 674                         };
 675                 };
 676
 677                 timer1: timer@4ae18000 {
 678                         compatible = "ti,omap5430-timer";
 679                         reg = <0x4ae18000 0x80>;
 680                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 681                         ti,hwmods = "timer1";
 682                         ti,timer-alwon;
 683                 };
 684
 685                 timer2: timer@48032000 {
 686                         compatible = "ti,omap5430-timer";
 687                         reg = <0x48032000 0x80>;
 688                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 689                         ti,hwmods = "timer2";
 690                 };
 691
 692                 timer3: timer@48034000 {
 693                         compatible = "ti,omap5430-timer";
 694                         reg = <0x48034000 0x80>;
 695                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 696                         ti,hwmods = "timer3";
 697                 };
 698
 699                 timer4: timer@48036000 {
 700                         compatible = "ti,omap5430-timer";
 701                         reg = <0x48036000 0x80>;
 702                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 703                         ti,hwmods = "timer4";
 704                 };
 705
 706                 timer5: timer@40138000 {
 707                         compatible = "ti,omap5430-timer";
 708                         reg = <0x40138000 0x80>,
 709                               <0x49038000 0x80>;
 710                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 711                         ti,hwmods = "timer5";
 712                         ti,timer-dsp;
 713                         ti,timer-pwm;
 714                 };
 715
 716                 timer6: timer@4013a000 {
 717                         compatible = "ti,omap5430-timer";
 718                         reg = <0x4013a000 0x80>,
 719                               <0x4903a000 0x80>;
 720                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 721                         ti,hwmods = "timer6";
 722                         ti,timer-dsp;
 723                         ti,timer-pwm;
 724                 };
 725
 726                 timer7: timer@4013c000 {
 727                         compatible = "ti,omap5430-timer";
 728                         reg = <0x4013c000 0x80>,
 729                               <0x4903c000 0x80>;
 730                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 731                         ti,hwmods = "timer7";
 732                         ti,timer-dsp;
 733                 };
 734
 735                 timer8: timer@4013e000 {
 736                         compatible = "ti,omap5430-timer";
 737                         reg = <0x4013e000 0x80>,
 738                               <0x4903e000 0x80>;
 739                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 740                         ti,hwmods = "timer8";
 741                         ti,timer-dsp;
 742                         ti,timer-pwm;
 743                 };
 744
 745                 timer9: timer@4803e000 {
 746                         compatible = "ti,omap5430-timer";
 747                         reg = <0x4803e000 0x80>;
 748                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 749                         ti,hwmods = "timer9";
 750                         ti,timer-pwm;
 751                 };
 752
 753                 timer10: timer@48086000 {
 754                         compatible = "ti,omap5430-timer";
 755                         reg = <0x48086000 0x80>;
 756                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 757                         ti,hwmods = "timer10";
 758                         ti,timer-pwm;
 759                 };
 760
 761                 timer11: timer@48088000 {
 762                         compatible = "ti,omap5430-timer";
 763                         reg = <0x48088000 0x80>;
 764                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 765                         ti,hwmods = "timer11";
 766                         ti,timer-pwm;
 767                 };
 768
 769                 wdt2: wdt@4ae14000 {
 770                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 771                         reg = <0x4ae14000 0x80>;
 772                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 773                         ti,hwmods = "wd_timer2";
 774                 };
 775
 776                 dmm@4e000000 {
 777                         compatible = "ti,omap5-dmm";
 778                         reg = <0x4e000000 0x800>;
 779                         interrupts = <0 113 0x4>;
 780                         ti,hwmods = "dmm";
 781                 };
 782
 783                 emif1: emif@4c000000 {
 784                         compatible      = "ti,emif-4d5";
 785                         ti,hwmods       = "emif1";
 786                         ti,no-idle-on-init;
 787                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 788                         reg = <0x4c000000 0x400>;
 789                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 790                         hw-caps-read-idle-ctrl;
 791                         hw-caps-ll-interface;
 792                         hw-caps-temp-alert;
 793                 };
 794
 795                 emif2: emif@4d000000 {
 796                         compatible      = "ti,emif-4d5";
 797                         ti,hwmods       = "emif2";
 798                         ti,no-idle-on-init;
 799                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 800                         reg = <0x4d000000 0x400>;
 801                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 802                         hw-caps-read-idle-ctrl;
 803                         hw-caps-ll-interface;
 804                         hw-caps-temp-alert;
 805                 };
 806
 807                 omap_control_usb2phy: control-phy@4a002300 {
 808                         compatible = "ti,control-phy-usb2";
 809                         reg = <0x4a002300 0x4>;
 810                         reg-names = "power";
 811                 };
 812
 813                 omap_control_usb3phy: control-phy@4a002370 {
 814                         compatible = "ti,control-phy-pipe3";
 815                         reg = <0x4a002370 0x4>;
 816                         reg-names = "power";
 817                 };
 818
 819                 usb3: omap_dwc3@4a020000 {
 820                         compatible = "ti,dwc3";
 821                         ti,hwmods = "usb_otg_ss";
 822                         reg = <0x4a020000 0x10000>;
 823                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 824                         #address-cells = <1>;
 825                         #size-cells = <1>;
 826                         utmi-mode = <2>;
 827                         ranges;
 828                         dwc3@4a030000 {
 829                                 compatible = "snps,dwc3";
 830                                 reg = <0x4a030000 0x10000>;
 831                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 832                                 phys = <&usb2_phy>, <&usb3_phy>;
 833                                 phy-names = "usb2-phy", "usb3-phy";
 834                                 dr_mode = "peripheral";
 835                                 tx-fifo-resize;
 836                         };
 837                 };
 838
 839                 ocp2scp@4a080000 {
 840                         compatible = "ti,omap-ocp2scp";
 841                         #address-cells = <1>;
 842                         #size-cells = <1>;
 843                         reg = <0x4a080000 0x20>;
 844                         ranges;
 845                         ti,hwmods = "ocp2scp1";
 846                         usb2_phy: usb2phy@4a084000 {
 847                                 compatible = "ti,omap-usb2";
 848                                 reg = <0x4a084000 0x7c>;
 849                                 ctrl-module = <&omap_control_usb2phy>;
 850                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 851                                 clock-names = "wkupclk", "refclk";
 852                                 #phy-cells = <0>;
 853                         };
 854
 855                         usb3_phy: usb3phy@4a084400 {
 856                                 compatible = "ti,omap-usb3";
 857                                 reg = <0x4a084400 0x80>,
 858                                       <0x4a084800 0x64>,
 859                                       <0x4a084c00 0x40>;
 860                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 861                                 ctrl-module = <&omap_control_usb3phy>;
 862                                 clocks = <&usb_phy_cm_clk32k>,
 863                                          <&sys_clkin>,
 864                                          <&usb_otg_ss_refclk960m>;
 865                                 clock-names =   "wkupclk",
 866                                                 "sysclk",
 867                                                 "refclk";
 868                                 #phy-cells = <0>;
 869                         };
 870                 };
 871
 872                 usbhstll: usbhstll@4a062000 {
 873                         compatible = "ti,usbhs-tll";
 874                         reg = <0x4a062000 0x1000>;
 875                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 876                         ti,hwmods = "usb_tll_hs";
 877                 };
 878
 879                 usbhshost: usbhshost@4a064000 {
 880                         compatible = "ti,usbhs-host";
 881                         reg = <0x4a064000 0x800>;
 882                         ti,hwmods = "usb_host_hs";
 883                         #address-cells = <1>;
 884                         #size-cells = <1>;
 885                         ranges;
 886                         clocks = <&l3init_60m_fclk>,
 887                                  <&xclk60mhsp1_ck>,
 888                                  <&xclk60mhsp2_ck>;
 889                         clock-names = "refclk_60m_int",
 890                                       "refclk_60m_ext_p1",
 891                                       "refclk_60m_ext_p2";
 892
 893                         usbhsohci: ohci@4a064800 {
 894                                 compatible = "ti,ohci-omap3";
 895                                 reg = <0x4a064800 0x400>;
 896                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 897                         };
 898
 899                         usbhsehci: ehci@4a064c00 {
 900                                 compatible = "ti,ehci-omap";
 901                                 reg = <0x4a064c00 0x400>;
 902                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 903                         };
 904                 };
 905
 906                 bandgap: bandgap@4a0021e0 {
 907                         reg = <0x4a0021e0 0xc
 908                                0x4a00232c 0xc
 909                                0x4a002380 0x2c
 910                                0x4a0023C0 0x3c>;
 911                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 912                         compatible = "ti,omap5430-bandgap";
 913
 914                         #thermal-sensor-cells = <1>;
 915                 };
 916
 917                 omap_control_sata: control-phy@4a002374 {
 918                         compatible = "ti,control-phy-pipe3";
 919                         reg = <0x4a002374 0x4>;
 920                         reg-names = "power";
 921                         clocks = <&sys_clkin>;
 922                         clock-names = "sysclk";
 923                 };
 924
 925                 /* OCP2SCP3 */
 926                 ocp2scp@4a090000 {
 927                         compatible = "ti,omap-ocp2scp";
 928                         #address-cells = <1>;
 929                         #size-cells = <1>;
 930                         reg = <0x4a090000 0x20>;
 931                         ranges;
 932                         ti,hwmods = "ocp2scp3";
 933                         sata_phy: phy@4a096000 {
 934                                 compatible = "ti,phy-pipe3-sata";
 935                                 reg = <0x4A096000 0x80>, /* phy_rx */
 936                                       <0x4A096400 0x64>, /* phy_tx */
 937                                       <0x4A096800 0x40>; /* pll_ctrl */
 938                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 939                                 ctrl-module = <&omap_control_sata>;
 940                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 941                                 clock-names = "sysclk", "refclk";
 942                                 #phy-cells = <0>;
 943                         };
 944                 };
 945
 946                 sata: sata@4a141100 {
 947                         compatible = "snps,dwc-ahci";
 948                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 949                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 950                         phys = <&sata_phy>;
 951                         phy-names = "sata-phy";
 952                         clocks = <&sata_ref_clk>;
 953                         ti,hwmods = "sata";
 954                 };
 955
 956                 dss: dss@58000000 {
 957                         compatible = "ti,omap5-dss";
 958                         reg = <0x58000000 0x80>;
 959                         status = "disabled";
 960                         ti,hwmods = "dss_core";
 961                         clocks = <&dss_dss_clk>;
 962                         clock-names = "fck";
 963                         #address-cells = <1>;
 964                         #size-cells = <1>;
 965                         ranges;
 966
 967                         dispc@58001000 {
 968                                 compatible = "ti,omap5-dispc";
 969                                 reg = <0x58001000 0x1000>;
 970                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 971                                 ti,hwmods = "dss_dispc";
 972                                 clocks = <&dss_dss_clk>;
 973                                 clock-names = "fck";
 974                         };
 975
 976                         rfbi: encoder@58002000  {
 977                                 compatible = "ti,omap5-rfbi";
 978                                 reg = <0x58002000 0x100>;
 979                                 status = "disabled";
 980                                 ti,hwmods = "dss_rfbi";
 981                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
 982                                 clock-names = "fck", "ick";
 983                         };
 984
 985                         dsi1: encoder@58004000 {
 986                                 compatible = "ti,omap5-dsi";
 987                                 reg = <0x58004000 0x200>,
 988                                       <0x58004200 0x40>,
 989                                       <0x58004300 0x40>;
 990                                 reg-names = "proto", "phy", "pll";
 991                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 992                                 status = "disabled";
 993                                 ti,hwmods = "dss_dsi1";
 994                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 995                                 clock-names = "fck", "sys_clk";
 996                         };
 997
 998                         dsi2: encoder@58005000 {
 999                                 compatible = "ti,omap5-dsi";
1000                                 reg = <0x58009000 0x200>,
1001                                       <0x58009200 0x40>,
1002                                       <0x58009300 0x40>;
1003                                 reg-names = "proto", "phy", "pll";
1004                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1005                                 status = "disabled";
1006                                 ti,hwmods = "dss_dsi2";
1007                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1008                                 clock-names = "fck", "sys_clk";
1009                         };
1010
1011                         hdmi: encoder@58060000 {
1012                                 compatible = "ti,omap5-hdmi";
1013                                 reg = <0x58040000 0x200>,
1014                                       <0x58040200 0x80>,
1015                                       <0x58040300 0x80>,
1016                                       <0x58060000 0x19000>;
1017                                 reg-names = "wp", "pll", "phy", "core";
1018                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1019                                 status = "disabled";
1020                                 ti,hwmods = "dss_hdmi";
1021                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1022                                 clock-names = "fck", "sys_clk";
1023                                 dmas = <&sdma 76>;
1024                                 dma-names = "audio_tx";
1025                         };
1026                 };
1027
1028                 abb_mpu: regulator-abb-mpu {
1029                         compatible = "ti,abb-v2";
1030                         regulator-name = "abb_mpu";
1031                         #address-cells = <0>;
1032                         #size-cells = <0>;
1033                         clocks = <&sys_clkin>;
1034                         ti,settling-time = <50>;
1035                         ti,clock-cycles = <16>;
1036
1037                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1038                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1039                         reg-names = "base-address", "int-address",
1040                                     "efuse-address", "ldo-address";
1041                         ti,tranxdone-status-mask = <0x80>;
1042                         /* LDOVBBMPU_MUX_CTRL */
1043                         ti,ldovbb-override-mask = <0x400>;
1044                         /* LDOVBBMPU_VSET_OUT */
1045                         ti,ldovbb-vset-mask = <0x1F>;
1046
1047                         /*
1048                          * NOTE: only FBB mode used but actual vset will
1049                          * determine final biasing
1050                          */
1051                         ti,abb_info = <
1052                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1053                         1060000         0       0x0     0 0x02000000 0x01F00000
1054                         1250000         0       0x4     0 0x02000000 0x01F00000
1055                         >;
1056                 };
1057
1058                 abb_mm: regulator-abb-mm {
1059                         compatible = "ti,abb-v2";
1060                         regulator-name = "abb_mm";
1061                         #address-cells = <0>;
1062                         #size-cells = <0>;
1063                         clocks = <&sys_clkin>;
1064                         ti,settling-time = <50>;
1065                         ti,clock-cycles = <16>;
1066
1067                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1068                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1069                         reg-names = "base-address", "int-address",
1070                                     "efuse-address", "ldo-address";
1071                         ti,tranxdone-status-mask = <0x80000000>;
1072                         /* LDOVBBMM_MUX_CTRL */
1073                         ti,ldovbb-override-mask = <0x400>;
1074                         /* LDOVBBMM_VSET_OUT */
1075                         ti,ldovbb-vset-mask = <0x1F>;
1076
1077                         /*
1078                          * NOTE: only FBB mode used but actual vset will
1079                          * determine final biasing
1080                          */
1081                         ti,abb_info = <
1082                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1083                         1025000         0       0x0     0 0x02000000 0x01F00000
1084                         1120000         0       0x4     0 0x02000000 0x01F00000
1085                         >;
1086                 };
1087         };
1088 };
1089
1090 &cpu_thermal {
1091         polling-delay = <500>; /* milliseconds */
1092 };
1093
1094 /include/ "omap54xx-clocks.dtsi"