arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 500000  880000
  49                                 1000000 1060000
  50                                 1500000 1250000
  51                         >;
  52                         /* cooling options */
  53                         cooling-min-level = <0>;
  54                         cooling-max-level = <2>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57                 cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x1>;
  61                 };
  62         };
  63
  64         thermal-zones {
  65                 #include "omap4-cpu-thermal.dtsi"
  66                 #include "omap5-gpu-thermal.dtsi"
  67                 #include "omap5-core-thermal.dtsi"
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 /* PPI secure/nonsecure IRQ */
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  77         };
  78
  79         gic: interrupt-controller@48211000 {
  80                 compatible = "arm,cortex-a15-gic";
  81                 interrupt-controller;
  82                 #interrupt-cells = <3>;
  83                 reg = <0x48211000 0x1000>,
  84                       <0x48212000 0x1000>,
  85                       <0x48214000 0x2000>,
  86                       <0x48216000 0x2000>;
  87         };
  88
  89         /*
  90          * The soc node represents the soc top level view. It is uses for IPs
  91          * that are not memory mapped in the MPU view or for the MPU itself.
  92          */
  93         soc {
  94                 compatible = "ti,omap-infra";
  95                 mpu {
  96                         compatible = "ti,omap5-mpu";
  97                         ti,hwmods = "mpu";
  98                 };
  99         };
 100
 101         /*
 102          * XXX: Use a flat representation of the OMAP3 interconnect.
 103          * The real OMAP interconnect network is quite complex.
 104          * Since that will not bring real advantage to represent that in DT for
 105          * the moment, just use a fake OCP bus entry to represent the whole bus
 106          * hierarchy.
 107          */
 108         ocp {
 109                 compatible = "ti,omap4-l3-noc", "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges;
 113                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 114                 reg = <0x44000000 0x2000>,
 115                       <0x44800000 0x3000>,
 116                       <0x45000000 0x4000>;
 117                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 119
 120                 counter32k: counter@4ae04000 {
 121                         compatible = "ti,omap-counter32k";
 122                         reg = <0x4ae04000 0x40>;
 123                         ti,hwmods = "counter_32k";
 124                 };
 125
 126                 omap5_pmx_core: pinmux@4a002840 {
 127                         compatible = "ti,omap4-padconf", "pinctrl-single";
 128                         reg = <0x4a002840 0x01b6>;
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         pinctrl-single,register-width = <16>;
 132                         pinctrl-single,function-mask = <0x7fff>;
 133                 };
 134                 omap5_pmx_wkup: pinmux@4ae0c840 {
 135                         compatible = "ti,omap4-padconf", "pinctrl-single";
 136                         reg = <0x4ae0c840 0x0038>;
 137                         #address-cells = <1>;
 138                         #size-cells = <0>;
 139                         pinctrl-single,register-width = <16>;
 140                         pinctrl-single,function-mask = <0x7fff>;
 141                 };
 142
 143                 sdma: dma-controller@4a056000 {
 144                         compatible = "ti,omap4430-sdma";
 145                         reg = <0x4a056000 0x1000>;
 146                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 150                         #dma-cells = <1>;
 151                         #dma-channels = <32>;
 152                         #dma-requests = <127>;
 153                 };
 154
 155                 gpio1: gpio@4ae10000 {
 156                         compatible = "ti,omap4-gpio";
 157                         reg = <0x4ae10000 0x200>;
 158                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 159                         ti,hwmods = "gpio1";
 160                         ti,gpio-always-on;
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163                         interrupt-controller;
 164                         #interrupt-cells = <2>;
 165                 };
 166
 167                 gpio2: gpio@48055000 {
 168                         compatible = "ti,omap4-gpio";
 169                         reg = <0x48055000 0x200>;
 170                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 171                         ti,hwmods = "gpio2";
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                         interrupt-controller;
 175                         #interrupt-cells = <2>;
 176                 };
 177
 178                 gpio3: gpio@48057000 {
 179                         compatible = "ti,omap4-gpio";
 180                         reg = <0x48057000 0x200>;
 181                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 182                         ti,hwmods = "gpio3";
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185                         interrupt-controller;
 186                         #interrupt-cells = <2>;
 187                 };
 188
 189                 gpio4: gpio@48059000 {
 190                         compatible = "ti,omap4-gpio";
 191                         reg = <0x48059000 0x200>;
 192                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 193                         ti,hwmods = "gpio4";
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                         interrupt-controller;
 197                         #interrupt-cells = <2>;
 198                 };
 199
 200                 gpio5: gpio@4805b000 {
 201                         compatible = "ti,omap4-gpio";
 202                         reg = <0x4805b000 0x200>;
 203                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 204                         ti,hwmods = "gpio5";
 205                         gpio-controller;
 206                         #gpio-cells = <2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <2>;
 209                 };
 210
 211                 gpio6: gpio@4805d000 {
 212                         compatible = "ti,omap4-gpio";
 213                         reg = <0x4805d000 0x200>;
 214                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 215                         ti,hwmods = "gpio6";
 216                         gpio-controller;
 217                         #gpio-cells = <2>;
 218                         interrupt-controller;
 219                         #interrupt-cells = <2>;
 220                 };
 221
 222                 gpio7: gpio@48051000 {
 223                         compatible = "ti,omap4-gpio";
 224                         reg = <0x48051000 0x200>;
 225                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 226                         ti,hwmods = "gpio7";
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                         interrupt-controller;
 230                         #interrupt-cells = <2>;
 231                 };
 232
 233                 gpio8: gpio@48053000 {
 234                         compatible = "ti,omap4-gpio";
 235                         reg = <0x48053000 0x200>;
 236                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 237                         ti,hwmods = "gpio8";
 238                         gpio-controller;
 239                         #gpio-cells = <2>;
 240                         interrupt-controller;
 241                         #interrupt-cells = <2>;
 242                 };
 243
 244                 gpmc: gpmc@50000000 {
 245                         compatible = "ti,omap4430-gpmc";
 246                         reg = <0x50000000 0x1000>;
 247                         #address-cells = <2>;
 248                         #size-cells = <1>;
 249                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 250                         gpmc,num-cs = <8>;
 251                         gpmc,num-waitpins = <4>;
 252                         ti,hwmods = "gpmc";
 253                 };
 254
 255                 i2c1: i2c@48070000 {
 256                         compatible = "ti,omap4-i2c";
 257                         reg = <0x48070000 0x100>;
 258                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         ti,hwmods = "i2c1";
 262                 };
 263
 264                 i2c2: i2c@48072000 {
 265                         compatible = "ti,omap4-i2c";
 266                         reg = <0x48072000 0x100>;
 267                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         ti,hwmods = "i2c2";
 271                 };
 272
 273                 i2c3: i2c@48060000 {
 274                         compatible = "ti,omap4-i2c";
 275                         reg = <0x48060000 0x100>;
 276                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         ti,hwmods = "i2c3";
 280                 };
 281
 282                 i2c4: i2c@4807a000 {
 283                         compatible = "ti,omap4-i2c";
 284                         reg = <0x4807a000 0x100>;
 285                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         ti,hwmods = "i2c4";
 289                 };
 290
 291                 i2c5: i2c@4807c000 {
 292                         compatible = "ti,omap4-i2c";
 293                         reg = <0x4807c000 0x100>;
 294                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         ti,hwmods = "i2c5";
 298                 };
 299
 300                 hwspinlock: spinlock@4a0f6000 {
 301                         compatible = "ti,omap4-hwspinlock";
 302                         reg = <0x4a0f6000 0x1000>;
 303                         ti,hwmods = "spinlock";
 304                 };
 305
 306                 mcspi1: spi@48098000 {
 307                         compatible = "ti,omap4-mcspi";
 308                         reg = <0x48098000 0x200>;
 309                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         ti,hwmods = "mcspi1";
 313                         ti,spi-num-cs = <4>;
 314                         dmas = <&sdma 35>,
 315                                <&sdma 36>,
 316                                <&sdma 37>,
 317                                <&sdma 38>,
 318                                <&sdma 39>,
 319                                <&sdma 40>,
 320                                <&sdma 41>,
 321                                <&sdma 42>;
 322                         dma-names = "tx0", "rx0", "tx1", "rx1",
 323                                     "tx2", "rx2", "tx3", "rx3";
 324                 };
 325
 326                 mcspi2: spi@4809a000 {
 327                         compatible = "ti,omap4-mcspi";
 328                         reg = <0x4809a000 0x200>;
 329                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         ti,hwmods = "mcspi2";
 333                         ti,spi-num-cs = <2>;
 334                         dmas = <&sdma 43>,
 335                                <&sdma 44>,
 336                                <&sdma 45>,
 337                                <&sdma 46>;
 338                         dma-names = "tx0", "rx0", "tx1", "rx1";
 339                 };
 340
 341                 mcspi3: spi@480b8000 {
 342                         compatible = "ti,omap4-mcspi";
 343                         reg = <0x480b8000 0x200>;
 344                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         ti,hwmods = "mcspi3";
 348                         ti,spi-num-cs = <2>;
 349                         dmas = <&sdma 15>, <&sdma 16>;
 350                         dma-names = "tx0", "rx0";
 351                 };
 352
 353                 mcspi4: spi@480ba000 {
 354                         compatible = "ti,omap4-mcspi";
 355                         reg = <0x480ba000 0x200>;
 356                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         ti,hwmods = "mcspi4";
 360                         ti,spi-num-cs = <1>;
 361                         dmas = <&sdma 70>, <&sdma 71>;
 362                         dma-names = "tx0", "rx0";
 363                 };
 364
 365                 uart1: serial@4806a000 {
 366                         compatible = "ti,omap4-uart";
 367                         reg = <0x4806a000 0x100>;
 368                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 369                         ti,hwmods = "uart1";
 370                         clock-frequency = <48000000>;
 371                 };
 372
 373                 uart2: serial@4806c000 {
 374                         compatible = "ti,omap4-uart";
 375                         reg = <0x4806c000 0x100>;
 376                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 377                         ti,hwmods = "uart2";
 378                         clock-frequency = <48000000>;
 379                 };
 380
 381                 uart3: serial@48020000 {
 382                         compatible = "ti,omap4-uart";
 383                         reg = <0x48020000 0x100>;
 384                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 385                         ti,hwmods = "uart3";
 386                         clock-frequency = <48000000>;
 387                 };
 388
 389                 uart4: serial@4806e000 {
 390                         compatible = "ti,omap4-uart";
 391                         reg = <0x4806e000 0x100>;
 392                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 393                         ti,hwmods = "uart4";
 394                         clock-frequency = <48000000>;
 395                 };
 396
 397                 uart5: serial@48066000 {
 398                         compatible = "ti,omap4-uart";
 399                         reg = <0x48066000 0x100>;
 400                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 401                         ti,hwmods = "uart5";
 402                         clock-frequency = <48000000>;
 403                 };
 404
 405                 uart6: serial@48068000 {
 406                         compatible = "ti,omap4-uart";
 407                         reg = <0x48068000 0x100>;
 408                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 409                         ti,hwmods = "uart6";
 410                         clock-frequency = <48000000>;
 411                 };
 412
 413                 mmc1: mmc@4809c000 {
 414                         compatible = "ti,omap4-hsmmc";
 415                         reg = <0x4809c000 0x400>;
 416                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 417                         ti,hwmods = "mmc1";
 418                         ti,dual-volt;
 419                         ti,needs-special-reset;
 420                         dmas = <&sdma 61>, <&sdma 62>;
 421                         dma-names = "tx", "rx";
 422                 };
 423
 424                 mmc2: mmc@480b4000 {
 425                         compatible = "ti,omap4-hsmmc";
 426                         reg = <0x480b4000 0x400>;
 427                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 428                         ti,hwmods = "mmc2";
 429                         ti,needs-special-reset;
 430                         dmas = <&sdma 47>, <&sdma 48>;
 431                         dma-names = "tx", "rx";
 432                 };
 433
 434                 mmc3: mmc@480ad000 {
 435                         compatible = "ti,omap4-hsmmc";
 436                         reg = <0x480ad000 0x400>;
 437                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 438                         ti,hwmods = "mmc3";
 439                         ti,needs-special-reset;
 440                         dmas = <&sdma 77>, <&sdma 78>;
 441                         dma-names = "tx", "rx";
 442                 };
 443
 444                 mmc4: mmc@480d1000 {
 445                         compatible = "ti,omap4-hsmmc";
 446                         reg = <0x480d1000 0x400>;
 447                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 448                         ti,hwmods = "mmc4";
 449                         ti,needs-special-reset;
 450                         dmas = <&sdma 57>, <&sdma 58>;
 451                         dma-names = "tx", "rx";
 452                 };
 453
 454                 mmc5: mmc@480d5000 {
 455                         compatible = "ti,omap4-hsmmc";
 456                         reg = <0x480d5000 0x400>;
 457                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 458                         ti,hwmods = "mmc5";
 459                         ti,needs-special-reset;
 460                         dmas = <&sdma 59>, <&sdma 60>;
 461                         dma-names = "tx", "rx";
 462                 };
 463
 464                 keypad: keypad@4ae1c000 {
 465                         compatible = "ti,omap4-keypad";
 466                         reg = <0x4ae1c000 0x400>;
 467                         ti,hwmods = "kbd";
 468                 };
 469
 470                 mcpdm: mcpdm@40132000 {
 471                         compatible = "ti,omap4-mcpdm";
 472                         reg = <0x40132000 0x7f>, /* MPU private access */
 473                               <0x49032000 0x7f>; /* L3 Interconnect */
 474                         reg-names = "mpu", "dma";
 475                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 476                         ti,hwmods = "mcpdm";
 477                         dmas = <&sdma 65>,
 478                                <&sdma 66>;
 479                         dma-names = "up_link", "dn_link";
 480                 };
 481
 482                 dmic: dmic@4012e000 {
 483                         compatible = "ti,omap4-dmic";
 484                         reg = <0x4012e000 0x7f>, /* MPU private access */
 485                               <0x4902e000 0x7f>; /* L3 Interconnect */
 486                         reg-names = "mpu", "dma";
 487                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 488                         ti,hwmods = "dmic";
 489                         dmas = <&sdma 67>;
 490                         dma-names = "up_link";
 491                 };
 492
 493                 mcbsp1: mcbsp@40122000 {
 494                         compatible = "ti,omap4-mcbsp";
 495                         reg = <0x40122000 0xff>, /* MPU private access */
 496                               <0x49022000 0xff>; /* L3 Interconnect */
 497                         reg-names = "mpu", "dma";
 498                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 499                         interrupt-names = "common";
 500                         ti,buffer-size = <128>;
 501                         ti,hwmods = "mcbsp1";
 502                         dmas = <&sdma 33>,
 503                                <&sdma 34>;
 504                         dma-names = "tx", "rx";
 505                 };
 506
 507                 mcbsp2: mcbsp@40124000 {
 508                         compatible = "ti,omap4-mcbsp";
 509                         reg = <0x40124000 0xff>, /* MPU private access */
 510                               <0x49024000 0xff>; /* L3 Interconnect */
 511                         reg-names = "mpu", "dma";
 512                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 513                         interrupt-names = "common";
 514                         ti,buffer-size = <128>;
 515                         ti,hwmods = "mcbsp2";
 516                         dmas = <&sdma 17>,
 517                                <&sdma 18>;
 518                         dma-names = "tx", "rx";
 519                 };
 520
 521                 mcbsp3: mcbsp@40126000 {
 522                         compatible = "ti,omap4-mcbsp";
 523                         reg = <0x40126000 0xff>, /* MPU private access */
 524                               <0x49026000 0xff>; /* L3 Interconnect */
 525                         reg-names = "mpu", "dma";
 526                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 527                         interrupt-names = "common";
 528                         ti,buffer-size = <128>;
 529                         ti,hwmods = "mcbsp3";
 530                         dmas = <&sdma 19>,
 531                                <&sdma 20>;
 532                         dma-names = "tx", "rx";
 533                 };
 534
 535                 timer1: timer@4ae18000 {
 536                         compatible = "ti,omap5430-timer";
 537                         reg = <0x4ae18000 0x80>;
 538                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "timer1";
 540                         ti,timer-alwon;
 541                 };
 542
 543                 timer2: timer@48032000 {
 544                         compatible = "ti,omap5430-timer";
 545                         reg = <0x48032000 0x80>;
 546                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 547                         ti,hwmods = "timer2";
 548                 };
 549
 550                 timer3: timer@48034000 {
 551                         compatible = "ti,omap5430-timer";
 552                         reg = <0x48034000 0x80>;
 553                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 554                         ti,hwmods = "timer3";
 555                 };
 556
 557                 timer4: timer@48036000 {
 558                         compatible = "ti,omap5430-timer";
 559                         reg = <0x48036000 0x80>;
 560                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 561                         ti,hwmods = "timer4";
 562                 };
 563
 564                 timer5: timer@40138000 {
 565                         compatible = "ti,omap5430-timer";
 566                         reg = <0x40138000 0x80>,
 567                               <0x49038000 0x80>;
 568                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "timer5";
 570                         ti,timer-dsp;
 571                         ti,timer-pwm;
 572                 };
 573
 574                 timer6: timer@4013a000 {
 575                         compatible = "ti,omap5430-timer";
 576                         reg = <0x4013a000 0x80>,
 577                               <0x4903a000 0x80>;
 578                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 579                         ti,hwmods = "timer6";
 580                         ti,timer-dsp;
 581                         ti,timer-pwm;
 582                 };
 583
 584                 timer7: timer@4013c000 {
 585                         compatible = "ti,omap5430-timer";
 586                         reg = <0x4013c000 0x80>,
 587                               <0x4903c000 0x80>;
 588                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 589                         ti,hwmods = "timer7";
 590                         ti,timer-dsp;
 591                 };
 592
 593                 timer8: timer@4013e000 {
 594                         compatible = "ti,omap5430-timer";
 595                         reg = <0x4013e000 0x80>,
 596                               <0x4903e000 0x80>;
 597                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 598                         ti,hwmods = "timer8";
 599                         ti,timer-dsp;
 600                         ti,timer-pwm;
 601                 };
 602
 603                 timer9: timer@4803e000 {
 604                         compatible = "ti,omap5430-timer";
 605                         reg = <0x4803e000 0x80>;
 606                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 607                         ti,hwmods = "timer9";
 608                         ti,timer-pwm;
 609                 };
 610
 611                 timer10: timer@48086000 {
 612                         compatible = "ti,omap5430-timer";
 613                         reg = <0x48086000 0x80>;
 614                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "timer10";
 616                         ti,timer-pwm;
 617                 };
 618
 619                 timer11: timer@48088000 {
 620                         compatible = "ti,omap5430-timer";
 621                         reg = <0x48088000 0x80>;
 622                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "timer11";
 624                         ti,timer-pwm;
 625                 };
 626
 627                 wdt2: wdt@4ae14000 {
 628                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 629                         reg = <0x4ae14000 0x80>;
 630                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 631                         ti,hwmods = "wd_timer2";
 632                 };
 633
 634                 emif1: emif@4c000000 {
 635                         compatible      = "ti,emif-4d5";
 636                         ti,hwmods       = "emif1";
 637                         ti,no-idle-on-init;
 638                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 639                         reg = <0x4c000000 0x400>;
 640                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 641                         hw-caps-read-idle-ctrl;
 642                         hw-caps-ll-interface;
 643                         hw-caps-temp-alert;
 644                 };
 645
 646                 emif2: emif@4d000000 {
 647                         compatible      = "ti,emif-4d5";
 648                         ti,hwmods       = "emif2";
 649                         ti,no-idle-on-init;
 650                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 651                         reg = <0x4d000000 0x400>;
 652                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 653                         hw-caps-read-idle-ctrl;
 654                         hw-caps-ll-interface;
 655                         hw-caps-temp-alert;
 656                 };
 657
 658                 omap_control_usb2phy: control-phy@4a002300 {
 659                         compatible = "ti,control-phy-usb2";
 660                         reg = <0x4a002300 0x4>;
 661                         reg-names = "power";
 662                 };
 663
 664                 omap_control_usb3phy: control-phy@4a002370 {
 665                         compatible = "ti,control-phy-pipe3";
 666                         reg = <0x4a002370 0x4>;
 667                         reg-names = "power";
 668                 };
 669
 670                 usb3: omap_dwc3@4a020000 {
 671                         compatible = "ti,dwc3";
 672                         ti,hwmods = "usb_otg_ss";
 673                         reg = <0x4a020000 0x10000>;
 674                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 675                         #address-cells = <1>;
 676                         #size-cells = <1>;
 677                         utmi-mode = <2>;
 678                         ranges;
 679                         dwc3@4a030000 {
 680                                 compatible = "snps,dwc3";
 681                                 reg = <0x4a030000 0x10000>;
 682                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 683                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
 684                                 dr_mode = "peripheral";
 685                                 tx-fifo-resize;
 686                         };
 687                 };
 688
 689                 ocp2scp@4a080000 {
 690                         compatible = "ti,omap-ocp2scp";
 691                         #address-cells = <1>;
 692                         #size-cells = <1>;
 693                         reg = <0x4a080000 0x20>;
 694                         ranges;
 695                         ti,hwmods = "ocp2scp1";
 696                         usb2_phy: usb2phy@4a084000 {
 697                                 compatible = "ti,omap-usb2";
 698                                 reg = <0x4a084000 0x7c>;
 699                                 ctrl-module = <&omap_control_usb2phy>;
 700                         };
 701
 702                         usb3_phy: usb3phy@4a084400 {
 703                                 compatible = "ti,omap-usb3";
 704                                 reg = <0x4a084400 0x80>,
 705                                       <0x4a084800 0x64>,
 706                                       <0x4a084c00 0x40>;
 707                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 708                                 ctrl-module = <&omap_control_usb3phy>;
 709                         };
 710                 };
 711
 712                 usbhstll: usbhstll@4a062000 {
 713                         compatible = "ti,usbhs-tll";
 714                         reg = <0x4a062000 0x1000>;
 715                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 716                         ti,hwmods = "usb_tll_hs";
 717                 };
 718
 719                 usbhshost: usbhshost@4a064000 {
 720                         compatible = "ti,usbhs-host";
 721                         reg = <0x4a064000 0x800>;
 722                         ti,hwmods = "usb_host_hs";
 723                         #address-cells = <1>;
 724                         #size-cells = <1>;
 725                         ranges;
 726
 727                         usbhsohci: ohci@4a064800 {
 728                                 compatible = "ti,ohci-omap3", "usb-ohci";
 729                                 reg = <0x4a064800 0x400>;
 730                                 interrupt-parent = <&gic>;
 731                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 732                         };
 733
 734                         usbhsehci: ehci@4a064c00 {
 735                                 compatible = "ti,ehci-omap", "usb-ehci";
 736                                 reg = <0x4a064c00 0x400>;
 737                                 interrupt-parent = <&gic>;
 738                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 739                         };
 740                 };
 741
 742                 bandgap: bandgap@4a0021e0 {
 743                         reg = <0x4a0021e0 0xc
 744                                0x4a00232c 0xc
 745                                0x4a002380 0x2c
 746                                0x4a0023C0 0x3c>;
 747                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 748                         compatible = "ti,omap5430-bandgap";
 749
 750                         #thermal-sensor-cells = <1>;
 751                 };
 752         };
 753 };