2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
12 #include "skeleton.dtsi"
18 compatible = "ti,omap5";
19 interrupt-parent = <&gic>;
32 compatible = "arm,cortex-a15";
35 compatible = "arm,cortex-a15";
40 compatible = "arm,armv7-timer";
41 /* PPI secure/nonsecure IRQ, active low level-sensitive */
42 interrupts = <1 13 0x308>,
46 clock-frequency = <6144000>;
49 gic: interrupt-controller@48211000 {
50 compatible = "arm,cortex-a15-gic";
52 #interrupt-cells = <3>;
53 reg = <0x48211000 0x1000>,
60 * The soc node represents the soc top level view. It is uses for IPs
61 * that are not memory mapped in the MPU view or for the MPU itself.
64 compatible = "ti,omap-infra";
66 compatible = "ti,omap5-mpu";
72 * XXX: Use a flat representation of the OMAP3 interconnect.
73 * The real OMAP interconnect network is quite complex.
74 * Since that will not bring real advantage to represent that in DT for
75 * the moment, just use a fake OCP bus entry to represent the whole bus
79 compatible = "ti,omap4-l3-noc", "simple-bus";
83 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
84 reg = <0x44000000 0x2000>,
87 interrupts = <0 9 0x4>,
90 counter32k: counter@4ae04000 {
91 compatible = "ti,omap-counter32k";
92 reg = <0x4ae04000 0x40>;
93 ti,hwmods = "counter_32k";
96 omap5_pmx_core: pinmux@4a002840 {
97 compatible = "ti,omap4-padconf", "pinctrl-single";
98 reg = <0x4a002840 0x01b6>;
101 pinctrl-single,register-width = <16>;
102 pinctrl-single,function-mask = <0x7fff>;
104 omap5_pmx_wkup: pinmux@4ae0c840 {
105 compatible = "ti,omap4-padconf", "pinctrl-single";
106 reg = <0x4ae0c840 0x0038>;
107 #address-cells = <1>;
109 pinctrl-single,register-width = <16>;
110 pinctrl-single,function-mask = <0x7fff>;
113 sdma: dma-controller@4a056000 {
114 compatible = "ti,omap4430-sdma";
115 reg = <0x4a056000 0x1000>;
116 interrupts = <0 12 0x4>,
121 #dma-channels = <32>;
122 #dma-requests = <127>;
125 gpio1: gpio@4ae10000 {
126 compatible = "ti,omap4-gpio";
127 reg = <0x4ae10000 0x200>;
128 interrupts = <0 29 0x4>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
137 gpio2: gpio@48055000 {
138 compatible = "ti,omap4-gpio";
139 reg = <0x48055000 0x200>;
140 interrupts = <0 30 0x4>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
148 gpio3: gpio@48057000 {
149 compatible = "ti,omap4-gpio";
150 reg = <0x48057000 0x200>;
151 interrupts = <0 31 0x4>;
155 interrupt-controller;
156 #interrupt-cells = <2>;
159 gpio4: gpio@48059000 {
160 compatible = "ti,omap4-gpio";
161 reg = <0x48059000 0x200>;
162 interrupts = <0 32 0x4>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
170 gpio5: gpio@4805b000 {
171 compatible = "ti,omap4-gpio";
172 reg = <0x4805b000 0x200>;
173 interrupts = <0 33 0x4>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
181 gpio6: gpio@4805d000 {
182 compatible = "ti,omap4-gpio";
183 reg = <0x4805d000 0x200>;
184 interrupts = <0 34 0x4>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
192 gpio7: gpio@48051000 {
193 compatible = "ti,omap4-gpio";
194 reg = <0x48051000 0x200>;
195 interrupts = <0 35 0x4>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
203 gpio8: gpio@48053000 {
204 compatible = "ti,omap4-gpio";
205 reg = <0x48053000 0x200>;
206 interrupts = <0 121 0x4>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
214 gpmc: gpmc@50000000 {
215 compatible = "ti,omap4430-gpmc";
216 reg = <0x50000000 0x1000>;
217 #address-cells = <2>;
219 interrupts = <0 20 0x4>;
221 gpmc,num-waitpins = <4>;
226 compatible = "ti,omap4-i2c";
227 reg = <0x48070000 0x100>;
228 interrupts = <0 56 0x4>;
229 #address-cells = <1>;
235 compatible = "ti,omap4-i2c";
236 reg = <0x48072000 0x100>;
237 interrupts = <0 57 0x4>;
238 #address-cells = <1>;
244 compatible = "ti,omap4-i2c";
245 reg = <0x48060000 0x100>;
246 interrupts = <0 61 0x4>;
247 #address-cells = <1>;
253 compatible = "ti,omap4-i2c";
254 reg = <0x4807a000 0x100>;
255 interrupts = <0 62 0x4>;
256 #address-cells = <1>;
262 compatible = "ti,omap4-i2c";
263 reg = <0x4807c000 0x100>;
264 interrupts = <0 60 0x4>;
265 #address-cells = <1>;
270 mcspi1: spi@48098000 {
271 compatible = "ti,omap4-mcspi";
272 reg = <0x48098000 0x200>;
273 interrupts = <0 65 0x4>;
274 #address-cells = <1>;
276 ti,hwmods = "mcspi1";
286 dma-names = "tx0", "rx0", "tx1", "rx1",
287 "tx2", "rx2", "tx3", "rx3";
290 mcspi2: spi@4809a000 {
291 compatible = "ti,omap4-mcspi";
292 reg = <0x4809a000 0x200>;
293 interrupts = <0 66 0x4>;
294 #address-cells = <1>;
296 ti,hwmods = "mcspi2";
302 dma-names = "tx0", "rx0", "tx1", "rx1";
305 mcspi3: spi@480b8000 {
306 compatible = "ti,omap4-mcspi";
307 reg = <0x480b8000 0x200>;
308 interrupts = <0 91 0x4>;
309 #address-cells = <1>;
311 ti,hwmods = "mcspi3";
313 dmas = <&sdma 15>, <&sdma 16>;
314 dma-names = "tx0", "rx0";
317 mcspi4: spi@480ba000 {
318 compatible = "ti,omap4-mcspi";
319 reg = <0x480ba000 0x200>;
320 interrupts = <0 48 0x4>;
321 #address-cells = <1>;
323 ti,hwmods = "mcspi4";
325 dmas = <&sdma 70>, <&sdma 71>;
326 dma-names = "tx0", "rx0";
329 uart1: serial@4806a000 {
330 compatible = "ti,omap4-uart";
331 reg = <0x4806a000 0x100>;
332 interrupts = <0 72 0x4>;
334 clock-frequency = <48000000>;
337 uart2: serial@4806c000 {
338 compatible = "ti,omap4-uart";
339 reg = <0x4806c000 0x100>;
340 interrupts = <0 73 0x4>;
342 clock-frequency = <48000000>;
345 uart3: serial@48020000 {
346 compatible = "ti,omap4-uart";
347 reg = <0x48020000 0x100>;
348 interrupts = <0 74 0x4>;
350 clock-frequency = <48000000>;
353 uart4: serial@4806e000 {
354 compatible = "ti,omap4-uart";
355 reg = <0x4806e000 0x100>;
356 interrupts = <0 70 0x4>;
358 clock-frequency = <48000000>;
361 uart5: serial@48066000 {
362 compatible = "ti,omap4-uart";
363 reg = <0x48066000 0x100>;
364 interrupts = <0 105 0x4>;
366 clock-frequency = <48000000>;
369 uart6: serial@48068000 {
370 compatible = "ti,omap4-uart";
371 reg = <0x48068000 0x100>;
372 interrupts = <0 106 0x4>;
374 clock-frequency = <48000000>;
378 compatible = "ti,omap4-hsmmc";
379 reg = <0x4809c000 0x400>;
380 interrupts = <0 83 0x4>;
383 ti,needs-special-reset;
384 dmas = <&sdma 61>, <&sdma 62>;
385 dma-names = "tx", "rx";
389 compatible = "ti,omap4-hsmmc";
390 reg = <0x480b4000 0x400>;
391 interrupts = <0 86 0x4>;
393 ti,needs-special-reset;
394 dmas = <&sdma 47>, <&sdma 48>;
395 dma-names = "tx", "rx";
399 compatible = "ti,omap4-hsmmc";
400 reg = <0x480ad000 0x400>;
401 interrupts = <0 94 0x4>;
403 ti,needs-special-reset;
404 dmas = <&sdma 77>, <&sdma 78>;
405 dma-names = "tx", "rx";
409 compatible = "ti,omap4-hsmmc";
410 reg = <0x480d1000 0x400>;
411 interrupts = <0 96 0x4>;
413 ti,needs-special-reset;
414 dmas = <&sdma 57>, <&sdma 58>;
415 dma-names = "tx", "rx";
419 compatible = "ti,omap4-hsmmc";
420 reg = <0x480d5000 0x400>;
421 interrupts = <0 59 0x4>;
423 ti,needs-special-reset;
424 dmas = <&sdma 59>, <&sdma 60>;
425 dma-names = "tx", "rx";
428 keypad: keypad@4ae1c000 {
429 compatible = "ti,omap4-keypad";
430 reg = <0x4ae1c000 0x400>;
434 mcpdm: mcpdm@40132000 {
435 compatible = "ti,omap4-mcpdm";
436 reg = <0x40132000 0x7f>, /* MPU private access */
437 <0x49032000 0x7f>; /* L3 Interconnect */
438 reg-names = "mpu", "dma";
439 interrupts = <0 112 0x4>;
443 dma-names = "up_link", "dn_link";
446 dmic: dmic@4012e000 {
447 compatible = "ti,omap4-dmic";
448 reg = <0x4012e000 0x7f>, /* MPU private access */
449 <0x4902e000 0x7f>; /* L3 Interconnect */
450 reg-names = "mpu", "dma";
451 interrupts = <0 114 0x4>;
454 dma-names = "up_link";
457 mcbsp1: mcbsp@40122000 {
458 compatible = "ti,omap4-mcbsp";
459 reg = <0x40122000 0xff>, /* MPU private access */
460 <0x49022000 0xff>; /* L3 Interconnect */
461 reg-names = "mpu", "dma";
462 interrupts = <0 17 0x4>;
463 interrupt-names = "common";
464 ti,buffer-size = <128>;
465 ti,hwmods = "mcbsp1";
468 dma-names = "tx", "rx";
471 mcbsp2: mcbsp@40124000 {
472 compatible = "ti,omap4-mcbsp";
473 reg = <0x40124000 0xff>, /* MPU private access */
474 <0x49024000 0xff>; /* L3 Interconnect */
475 reg-names = "mpu", "dma";
476 interrupts = <0 22 0x4>;
477 interrupt-names = "common";
478 ti,buffer-size = <128>;
479 ti,hwmods = "mcbsp2";
482 dma-names = "tx", "rx";
485 mcbsp3: mcbsp@40126000 {
486 compatible = "ti,omap4-mcbsp";
487 reg = <0x40126000 0xff>, /* MPU private access */
488 <0x49026000 0xff>; /* L3 Interconnect */
489 reg-names = "mpu", "dma";
490 interrupts = <0 23 0x4>;
491 interrupt-names = "common";
492 ti,buffer-size = <128>;
493 ti,hwmods = "mcbsp3";
496 dma-names = "tx", "rx";
499 timer1: timer@4ae18000 {
500 compatible = "ti,omap5430-timer";
501 reg = <0x4ae18000 0x80>;
502 interrupts = <0 37 0x4>;
503 ti,hwmods = "timer1";
507 timer2: timer@48032000 {
508 compatible = "ti,omap5430-timer";
509 reg = <0x48032000 0x80>;
510 interrupts = <0 38 0x4>;
511 ti,hwmods = "timer2";
514 timer3: timer@48034000 {
515 compatible = "ti,omap5430-timer";
516 reg = <0x48034000 0x80>;
517 interrupts = <0 39 0x4>;
518 ti,hwmods = "timer3";
521 timer4: timer@48036000 {
522 compatible = "ti,omap5430-timer";
523 reg = <0x48036000 0x80>;
524 interrupts = <0 40 0x4>;
525 ti,hwmods = "timer4";
528 timer5: timer@40138000 {
529 compatible = "ti,omap5430-timer";
530 reg = <0x40138000 0x80>,
532 interrupts = <0 41 0x4>;
533 ti,hwmods = "timer5";
538 timer6: timer@4013a000 {
539 compatible = "ti,omap5430-timer";
540 reg = <0x4013a000 0x80>,
542 interrupts = <0 42 0x4>;
543 ti,hwmods = "timer6";
548 timer7: timer@4013c000 {
549 compatible = "ti,omap5430-timer";
550 reg = <0x4013c000 0x80>,
552 interrupts = <0 43 0x4>;
553 ti,hwmods = "timer7";
557 timer8: timer@4013e000 {
558 compatible = "ti,omap5430-timer";
559 reg = <0x4013e000 0x80>,
561 interrupts = <0 44 0x4>;
562 ti,hwmods = "timer8";
567 timer9: timer@4803e000 {
568 compatible = "ti,omap5430-timer";
569 reg = <0x4803e000 0x80>;
570 interrupts = <0 45 0x4>;
571 ti,hwmods = "timer9";
575 timer10: timer@48086000 {
576 compatible = "ti,omap5430-timer";
577 reg = <0x48086000 0x80>;
578 interrupts = <0 46 0x4>;
579 ti,hwmods = "timer10";
583 timer11: timer@48088000 {
584 compatible = "ti,omap5430-timer";
585 reg = <0x48088000 0x80>;
586 interrupts = <0 47 0x4>;
587 ti,hwmods = "timer11";
592 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
593 reg = <0x4ae14000 0x80>;
594 interrupts = <0 80 0x4>;
595 ti,hwmods = "wd_timer2";
598 emif1: emif@0x4c000000 {
599 compatible = "ti,emif-4d5";
601 phy-type = <2>; /* DDR PHY type: Intelli PHY */
602 reg = <0x4c000000 0x400>;
603 interrupts = <0 110 0x4>;
604 hw-caps-read-idle-ctrl;
605 hw-caps-ll-interface;
609 emif2: emif@0x4d000000 {
610 compatible = "ti,emif-4d5";
612 phy-type = <2>; /* DDR PHY type: Intelli PHY */
613 reg = <0x4d000000 0x400>;
614 interrupts = <0 111 0x4>;
615 hw-caps-read-idle-ctrl;
616 hw-caps-ll-interface;
620 omap_control_usb: omap-control-usb@4a002300 {
621 compatible = "ti,omap-control-usb";
622 reg = <0x4a002300 0x4>,
624 reg-names = "control_dev_conf", "phy_power_usb";
629 compatible = "ti,dwc3";
630 ti,hwmods = "usb_otg_ss";
631 reg = <0x4a020000 0x1000>;
632 interrupts = <0 93 4>;
633 #address-cells = <1>;
638 compatible = "synopsys,dwc3";
639 reg = <0x4a030000 0x1000>;
640 interrupts = <0 92 4>;
641 usb-phy = <&usb2_phy>, <&usb3_phy>;
647 compatible = "ti,omap-ocp2scp";
648 #address-cells = <1>;
651 ti,hwmods = "ocp2scp1";
652 usb2_phy: usb2phy@4a084000 {
653 compatible = "ti,omap-usb2";
654 reg = <0x4a084000 0x7c>;
655 ctrl-module = <&omap_control_usb>;
658 usb3_phy: usb3phy@4a084400 {
659 compatible = "ti,omap-usb3";
660 reg = <0x4a084400 0x80>,
663 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
664 ctrl-module = <&omap_control_usb>;