3 #include "skeleton.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
27 wcnss_mem: wcnss@8f000000 {
28 reg = <0x8f000000 0x700000>;
38 compatible = "qcom,krait";
39 enable-method = "qcom,kpss-acc-v1";
42 next-level-cache = <&L2>;
45 cpu-idle-states = <&CPU_SPC>;
46 clocks = <&kraitcc 0>, <&kraitcc 4>;
47 clock-names = "cpu", "l2";
48 clock-latency = <100000>;
49 cooling-min-level = <0>;
50 cooling-max-level = <7>;
55 compatible = "qcom,krait";
56 enable-method = "qcom,kpss-acc-v1";
59 next-level-cache = <&L2>;
62 cpu-idle-states = <&CPU_SPC>;
63 clocks = <&kraitcc 1>, <&kraitcc 4>;
64 clock-names = "cpu", "l2";
65 clock-latency = <100000>;
66 cooling-min-level = <0>;
67 cooling-max-level = <7>;
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
76 next-level-cache = <&L2>;
79 cpu-idle-states = <&CPU_SPC>;
80 clocks = <&kraitcc 2>, <&kraitcc 4>;
81 clock-names = "cpu", "l2";
82 clock-latency = <100000>;
83 cooling-min-level = <0>;
84 cooling-max-level = <7>;
89 compatible = "qcom,krait";
90 enable-method = "qcom,kpss-acc-v1";
93 next-level-cache = <&L2>;
96 cpu-idle-states = <&CPU_SPC>;
97 clocks = <&kraitcc 3>, <&kraitcc 4>;
98 clock-names = "cpu", "l2";
99 clock-latency = <100000>;
100 cooling-min-level = <0>;
101 cooling-max-level = <7>;
102 #cooling-cells = <2>;
106 compatible = "cache";
111 qcom,l2-rates = <384000000 972000000 1188000000>;
116 compatible = "qcom,idle-state-spc",
118 entry-latency-us = <400>;
119 exit-latency-us = <900>;
120 min-residency-us = <3000>;
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
130 thermal-sensors = <&gcc 7>;
134 temperature = <75000>;
139 temperature = <110000>;
147 trip = <&cpu_alert0>;
148 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
154 polling-delay-passive = <250>;
155 polling-delay = <1000>;
157 thermal-sensors = <&gcc 8>;
161 temperature = <75000>;
166 temperature = <110000>;
174 trip = <&cpu_alert1>;
175 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
181 polling-delay-passive = <250>;
182 polling-delay = <1000>;
184 thermal-sensors = <&gcc 9>;
188 temperature = <75000>;
193 temperature = <110000>;
201 trip = <&cpu_alert2>;
202 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208 polling-delay-passive = <250>;
209 polling-delay = <1000>;
211 thermal-sensors = <&gcc 10>;
215 temperature = <75000>;
220 temperature = <110000>;
228 trip = <&cpu_alert3>;
229 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236 compatible = "qcom,krait-pmu";
237 interrupts = <1 10 0x304>;
242 compatible = "fixed-clock";
244 clock-frequency = <19200000>;
248 compatible = "fixed-clock";
250 clock-frequency = <27000000>;
254 compatible = "fixed-clock";
256 clock-frequency = <32768>;
260 sfpb_mutex: hwmutex {
261 compatible = "qcom,sfpb-mutex";
262 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
267 compatible = "qcom,smem";
268 memory-region = <&smem_region>;
270 hwlocks = <&sfpb_mutex 3>;
275 qcom,speed0-pvs0-bin-v0 =
276 < 384000000 950000 >,
277 < 486000000 975000 >,
278 < 594000000 1000000 >,
279 < 702000000 1025000 >,
280 < 810000000 1075000 >,
281 < 918000000 1100000 >,
282 < 1026000000 1125000 >,
283 < 1080000000 1175000 >,
284 < 1134000000 1175000 >,
285 < 1188000000 1200000 >,
286 < 1242000000 1200000 >,
287 < 1296000000 1225000 >,
288 < 1350000000 1225000 >,
289 < 1404000000 1237500 >,
290 < 1458000000 1237500 >,
291 < 1512000000 1250000 >;
293 qcom,speed0-pvs1-bin-v0 =
294 < 384000000 900000 >,
295 < 486000000 925000 >,
296 < 594000000 950000 >,
297 < 702000000 975000 >,
298 < 810000000 1025000 >,
299 < 918000000 1050000 >,
300 < 1026000000 1075000 >,
301 < 1080000000 1125000 >,
302 < 1134000000 1125000 >,
303 < 1188000000 1150000 >,
304 < 1242000000 1150000 >,
305 < 1296000000 1175000 >,
306 < 1350000000 1175000 >,
307 < 1404000000 1187500 >,
308 < 1458000000 1187500 >,
309 < 1512000000 1200000 >;
311 qcom,speed0-pvs3-bin-v0 =
312 < 384000000 850000 >,
313 < 486000000 875000 >,
314 < 594000000 900000 >,
315 < 702000000 925000 >,
316 < 810000000 975000 >,
317 < 918000000 1000000 >,
318 < 1026000000 1025000 >,
319 < 1080000000 1075000 >,
320 < 1134000000 1075000 >,
321 < 1188000000 1100000 >,
322 < 1242000000 1100000 >,
323 < 1296000000 1125000 >,
324 < 1350000000 1125000 >,
325 < 1404000000 1137500 >,
326 < 1458000000 1137500 >,
327 < 1512000000 1150000 >;
329 qcom,speed0-pvs4-bin-v0 =
330 < 384000000 850000 >,
331 < 486000000 875000 >,
332 < 594000000 900000 >,
333 < 702000000 925000 >,
334 < 810000000 962500 >,
335 < 918000000 975000 >,
336 < 1026000000 1000000 >,
337 < 1080000000 1050000 >,
338 < 1134000000 1050000 >,
339 < 1188000000 1075000 >,
340 < 1242000000 1075000 >,
341 < 1296000000 1100000 >,
342 < 1350000000 1100000 >,
343 < 1404000000 1112500 >,
344 < 1458000000 1112500 >,
345 < 1512000000 1125000 >;
347 qcom,speed1-pvs0-bin-v0 =
348 < 384000000 950000 >,
349 < 486000000 950000 >,
350 < 594000000 950000 >,
351 < 702000000 962500 >,
352 < 810000000 1000000 >,
353 < 918000000 1025000 >,
354 < 1026000000 1037500 >,
355 < 1134000000 1075000 >,
356 < 1242000000 1087500 >,
357 < 1350000000 1125000 >,
358 < 1458000000 1150000 >,
359 < 1566000000 1175000 >,
360 < 1674000000 1225000 >,
361 < 1728000000 1250000 >;
363 qcom,speed1-pvs1-bin-v0 =
364 < 384000000 950000 >,
365 < 486000000 950000 >,
366 < 594000000 950000 >,
367 < 702000000 962500 >,
368 < 810000000 975000 >,
369 < 918000000 1000000 >,
370 < 1026000000 1012500 >,
371 < 1134000000 1037500 >,
372 < 1242000000 1050000 >,
373 < 1350000000 1087500 >,
374 < 1458000000 1112500 >,
375 < 1566000000 1150000 >,
376 < 1674000000 1187500 >,
377 < 1728000000 1200000 >;
379 qcom,speed1-pvs2-bin-v0 =
380 < 384000000 925000 >,
381 < 486000000 925000 >,
382 < 594000000 925000 >,
383 < 702000000 925000 >,
384 < 810000000 937500 >,
385 < 918000000 950000 >,
386 < 1026000000 975000 >,
387 < 1134000000 1000000 >,
388 < 1242000000 1012500 >,
389 < 1350000000 1037500 >,
390 < 1458000000 1075000 >,
391 < 1566000000 1100000 >,
392 < 1674000000 1137500 >,
393 < 1728000000 1162500 >;
395 qcom,speed1-pvs3-bin-v0 =
396 < 384000000 900000 >,
397 < 486000000 900000 >,
398 < 594000000 900000 >,
399 < 702000000 900000 >,
400 < 810000000 900000 >,
401 < 918000000 925000 >,
402 < 1026000000 950000 >,
403 < 1134000000 975000 >,
404 < 1242000000 987500 >,
405 < 1350000000 1000000 >,
406 < 1458000000 1037500 >,
407 < 1566000000 1062500 >,
408 < 1674000000 1100000 >,
409 < 1728000000 1125000 >;
411 qcom,speed1-pvs4-bin-v0 =
412 < 384000000 875000 >,
413 < 486000000 875000 >,
414 < 594000000 875000 >,
415 < 702000000 875000 >,
416 < 810000000 887500 >,
417 < 918000000 900000 >,
418 < 1026000000 925000 >,
419 < 1134000000 950000 >,
420 < 1242000000 962500 >,
421 < 1350000000 975000 >,
422 < 1458000000 1000000 >,
423 < 1566000000 1037500 >,
424 < 1674000000 1075000 >,
425 < 1728000000 1100000 >;
427 qcom,speed1-pvs5-bin-v0 =
428 < 384000000 875000 >,
429 < 486000000 875000 >,
430 < 594000000 875000 >,
431 < 702000000 875000 >,
432 < 810000000 887500 >,
433 < 918000000 900000 >,
434 < 1026000000 925000 >,
435 < 1134000000 937500 >,
436 < 1242000000 950000 >,
437 < 1350000000 962500 >,
438 < 1458000000 987500 >,
439 < 1566000000 1012500 >,
440 < 1674000000 1050000 >,
441 < 1728000000 1075000 >;
443 qcom,speed1-pvs6-bin-v0 =
444 < 384000000 875000 >,
445 < 486000000 875000 >,
446 < 594000000 875000 >,
447 < 702000000 875000 >,
448 < 810000000 887500 >,
449 < 918000000 900000 >,
450 < 1026000000 925000 >,
451 < 1134000000 937500 >,
452 < 1242000000 950000 >,
453 < 1350000000 962500 >,
454 < 1458000000 975000 >,
455 < 1566000000 1000000 >,
456 < 1674000000 1025000 >,
457 < 1728000000 1050000 >;
459 qcom,speed2-pvs0-bin-v0 =
460 < 384000000 950000 >,
461 < 486000000 950000 >,
462 < 594000000 950000 >,
463 < 702000000 950000 >,
464 < 810000000 962500 >,
465 < 918000000 975000 >,
466 < 1026000000 1000000 >,
467 < 1134000000 1025000 >,
468 < 1242000000 1037500 >,
469 < 1350000000 1062500 >,
470 < 1458000000 1100000 >,
471 < 1566000000 1125000 >,
472 < 1674000000 1175000 >,
473 < 1782000000 1225000 >,
474 < 1890000000 1287500 >;
476 qcom,speed2-pvs1-bin-v0 =
477 < 384000000 925000 >,
478 < 486000000 925000 >,
479 < 594000000 925000 >,
480 < 702000000 925000 >,
481 < 810000000 937500 >,
482 < 918000000 950000 >,
483 < 1026000000 975000 >,
484 < 1134000000 1000000 >,
485 < 1242000000 1012500 >,
486 < 1350000000 1037500 >,
487 < 1458000000 1075000 >,
488 < 1566000000 1100000 >,
489 < 1674000000 1137500 >,
490 < 1782000000 1187500 >,
491 < 1890000000 1250000 >;
493 qcom,speed2-pvs2-bin-v0 =
494 < 384000000 900000 >,
495 < 486000000 900000 >,
496 < 594000000 900000 >,
497 < 702000000 900000 >,
498 < 810000000 912500 >,
499 < 918000000 925000 >,
500 < 1026000000 950000 >,
501 < 1134000000 975000 >,
502 < 1242000000 987500 >,
503 < 1350000000 1012500 >,
504 < 1458000000 1050000 >,
505 < 1566000000 1075000 >,
506 < 1674000000 1112500 >,
507 < 1782000000 1162500 >,
508 < 1890000000 1212500 >;
510 qcom,speed2-pvs3-bin-v0 =
511 < 384000000 900000 >,
512 < 486000000 900000 >,
513 < 594000000 900000 >,
514 < 702000000 900000 >,
515 < 810000000 900000 >,
516 < 918000000 912500 >,
517 < 1026000000 937500 >,
518 < 1134000000 962500 >,
519 < 1242000000 975000 >,
520 < 1350000000 1000000 >,
521 < 1458000000 1025000 >,
522 < 1566000000 1050000 >,
523 < 1674000000 1087500 >,
524 < 1782000000 1137500 >,
525 < 1890000000 1175000 >;
527 qcom,speed2-pvs4-bin-v0 =
528 < 384000000 875000 >,
529 < 486000000 875000 >,
530 < 594000000 875000 >,
531 < 702000000 875000 >,
532 < 810000000 887500 >,
533 < 918000000 900000 >,
534 < 1026000000 925000 >,
535 < 1134000000 950000 >,
536 < 1242000000 962500 >,
537 < 1350000000 975000 >,
538 < 1458000000 1000000 >,
539 < 1566000000 1037500 >,
540 < 1674000000 1075000 >,
541 < 1782000000 1112500 >,
542 < 1890000000 1150000 >;
544 qcom,speed2-pvs5-bin-v0 =
545 < 384000000 875000 >,
546 < 486000000 875000 >,
547 < 594000000 875000 >,
548 < 702000000 875000 >,
549 < 810000000 887500 >,
550 < 918000000 900000 >,
551 < 1026000000 925000 >,
552 < 1134000000 937500 >,
553 < 1242000000 950000 >,
554 < 1350000000 962500 >,
555 < 1458000000 987500 >,
556 < 1566000000 1012500 >,
557 < 1674000000 1050000 >,
558 < 1782000000 1087500 >,
559 < 1890000000 1125000 >;
561 qcom,speed2-pvs6-bin-v0 =
562 < 384000000 875000 >,
563 < 486000000 875000 >,
564 < 594000000 875000 >,
565 < 702000000 875000 >,
566 < 810000000 887500 >,
567 < 918000000 900000 >,
568 < 1026000000 925000 >,
569 < 1134000000 937500 >,
570 < 1242000000 950000 >,
571 < 1350000000 962500 >,
572 < 1458000000 975000 >,
573 < 1566000000 1000000 >,
574 < 1674000000 1025000 >,
575 < 1782000000 1062500 >,
576 < 1890000000 1100000 >;
578 qcom,speed14-pvs0-bin-v0 =
579 < 384000000 950000 >,
580 < 486000000 950000 >,
581 < 594000000 950000 >,
582 < 702000000 962500 >,
583 < 810000000 1000000 >,
584 < 918000000 1025000 >,
585 < 1026000000 1037500 >,
586 < 1134000000 1075000 >,
587 < 1242000000 1087500 >,
588 < 1350000000 1125000 >,
589 < 1458000000 1150000 >,
590 < 1512000000 1162500 >;
592 qcom,speed14-pvs1-bin-v0 =
593 < 384000000 950000 >,
594 < 486000000 950000 >,
595 < 594000000 950000 >,
596 < 702000000 962500 >,
597 < 810000000 975000 >,
598 < 918000000 1000000 >,
599 < 1026000000 1012500 >,
600 < 1134000000 1037500 >,
601 < 1242000000 1050000 >,
602 < 1350000000 1087500 >,
603 < 1458000000 1112500 >,
604 < 1512000000 1125000 >;
606 qcom,speed14-pvs2-bin-v0 =
607 < 384000000 925000 >,
608 < 486000000 925000 >,
609 < 594000000 925000 >,
610 < 702000000 925000 >,
611 < 810000000 937500 >,
612 < 918000000 950000 >,
613 < 1026000000 975000 >,
614 < 1134000000 1000000 >,
615 < 1242000000 1012500 >,
616 < 1350000000 1037500 >,
617 < 1458000000 1075000 >,
618 < 1512000000 1087500 >;
620 qcom,speed14-pvs3-bin-v0 =
621 < 384000000 900000 >,
622 < 486000000 900000 >,
623 < 594000000 900000 >,
624 < 702000000 900000 >,
625 < 810000000 900000 >,
626 < 918000000 925000 >,
627 < 1026000000 950000 >,
628 < 1134000000 975000 >,
629 < 1242000000 987500 >,
630 < 1350000000 1000000 >,
631 < 1458000000 1037500 >,
632 < 1512000000 1050000 >;
634 qcom,speed14-pvs4-bin-v0 =
635 < 384000000 875000 >,
636 < 486000000 875000 >,
637 < 594000000 875000 >,
638 < 702000000 875000 >,
639 < 810000000 887500 >,
640 < 918000000 900000 >,
641 < 1026000000 925000 >,
642 < 1134000000 950000 >,
643 < 1242000000 962500 >,
644 < 1350000000 975000 >,
645 < 1458000000 1000000 >,
646 < 1512000000 1012500 >;
648 qcom,speed14-pvs5-bin-v0 =
649 < 384000000 875000 >,
650 < 486000000 875000 >,
651 < 594000000 875000 >,
652 < 702000000 875000 >,
653 < 810000000 887500 >,
654 < 918000000 900000 >,
655 < 1026000000 925000 >,
656 < 1134000000 937500 >,
657 < 1242000000 950000 >,
658 < 1350000000 962500 >,
659 < 1458000000 987500 >,
660 < 1512000000 1000000 >;
662 qcom,speed14-pvs6-bin-v0 =
663 < 384000000 875000 >,
664 < 486000000 875000 >,
665 < 594000000 875000 >,
666 < 702000000 875000 >,
667 < 810000000 887500 >,
668 < 918000000 900000 >,
669 < 1026000000 925000 >,
670 < 1134000000 937500 >,
671 < 1242000000 950000 >,
672 < 1350000000 962500 >,
673 < 1458000000 975000 >,
674 < 1512000000 987500 >;
677 kraitcc: clock-controller {
678 compatible = "qcom,krait-cc-v1";
683 sleep_clk: sleep_clk {
684 compatible = "fixed-clock";
685 clock-frequency = <32768>;
692 compatible = "fixed-clock";
694 clock-frequency = <19200000>;
698 compatible = "fixed-clock";
700 clock-frequency = <27000000>;
704 compatible = "fixed-clock";
706 clock-frequency = <32768>;
711 compatible = "simple-bus";
714 compatible = "qcom,scm";
719 compatible = "qcom,smd";
722 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
724 qcom,ipc = <&l2cc 8 3>;
731 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
733 qcom,ipc = <&l2cc 8 15>;
739 compatible = "qcom,apr";
740 qcom,smd-channels = "apr_audio_svc";
746 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
748 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
755 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
757 qcom,ipc = <&l2cc 8 25>;
765 compatible = "qcom,smsm";
767 #address-cells = <1>;
770 qcom,ipc-1 = <&l2cc 8 4>;
771 qcom,ipc-2 = <&l2cc 8 14>;
772 qcom,ipc-3 = <&l2cc 8 23>;
773 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
777 #qcom,state-cells = <1>;
780 modem_smsm: modem@1 {
782 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
784 interrupt-controller;
785 #interrupt-cells = <2>;
790 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
792 interrupt-controller;
793 #interrupt-cells = <2>;
796 wcnss_smsm: wcnss@3 {
798 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
800 interrupt-controller;
801 #interrupt-cells = <2>;
806 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
814 #address-cells = <1>;
817 compatible = "simple-bus";
819 tlmm_pinmux: pinctrl@800000 {
820 compatible = "qcom,apq8064-pinctrl";
821 reg = <0x800000 0x4000>;
825 interrupt-controller;
826 #interrupt-cells = <2>;
827 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
829 pinctrl-names = "default";
830 pinctrl-0 = <&ps_hold>;
833 sfpb_wrapper_mutex: syscon@1200000 {
834 compatible = "syscon";
835 reg = <0x01200000 0x8000>;
838 intc: interrupt-controller@2000000 {
839 compatible = "qcom,msm-qgic2";
840 interrupt-controller;
841 #interrupt-cells = <3>;
842 reg = <0x02000000 0x1000>,
847 compatible = "qcom,kpss-timer", "qcom,msm-timer";
848 interrupts = <1 1 0x301>,
851 reg = <0x0200a000 0x100>;
852 clock-frequency = <27000000>,
854 cpu-offset = <0x80000>;
858 compatible = "qcom,kpss-wdt-apq8064";
859 reg = <0x0208a038 0x40>;
860 clocks = <&sleep_clk>;
864 acc0: clock-controller@2088000 {
865 compatible = "qcom,kpss-acc-v1";
866 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
867 clock-output-names = "acpu0_aux";
870 acc1: clock-controller@2098000 {
871 compatible = "qcom,kpss-acc-v1";
872 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
873 clock-output-names = "acpu1_aux";
876 acc2: clock-controller@20a8000 {
877 compatible = "qcom,kpss-acc-v1";
878 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
879 clock-output-names = "acpu2_aux";
882 acc3: clock-controller@20b8000 {
883 compatible = "qcom,kpss-acc-v1";
884 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
885 clock-output-names = "acpu3_aux";
888 saw0: power-controller@2089000 {
889 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
890 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
892 regulator-name = "krait0";
894 regulator-min-microvolt = <825000>;
895 regulator-max-microvolt = <1250000>;
898 saw1: power-controller@2099000 {
899 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
900 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
902 regulator-name = "krait1";
904 regulator-min-microvolt = <825000>;
905 regulator-max-microvolt = <1250000>;
908 saw2: power-controller@20a9000 {
909 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
910 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
912 regulator-name = "krait2";
914 regulator-min-microvolt = <825000>;
915 regulator-max-microvolt = <1250000>;
918 saw3: power-controller@20b9000 {
919 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
920 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
922 regulator-name = "krait3";
924 regulator-min-microvolt = <825000>;
925 regulator-max-microvolt = <1250000>;
928 sps_sic_non_secure: sps-sic-non-secure@12100000 {
929 compatible = "syscon";
930 reg = <0x12100000 0x10000>;
933 gsbi1: gsbi@12440000 {
935 compatible = "qcom,gsbi-v1.0.0";
937 reg = <0x12440000 0x100>;
938 clocks = <&gcc GSBI1_H_CLK>;
939 clock-names = "iface";
940 #address-cells = <1>;
944 syscon-tcsr = <&tcsr>;
946 gsbi1_serial: serial@12450000 {
947 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
948 reg = <0x12450000 0x100>,
950 interrupts = <0 193 0x0>;
951 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
952 clock-names = "core", "iface";
956 gsbi1_i2c: i2c@12460000 {
957 compatible = "qcom,i2c-qup-v1.1.1";
958 pinctrl-0 = <&i2c1_pins>;
959 pinctrl-1 = <&i2c1_pins_sleep>;
960 pinctrl-names = "default", "sleep";
961 reg = <0x12460000 0x1000>;
962 interrupts = <0 194 IRQ_TYPE_NONE>;
963 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
964 clock-names = "core", "iface";
965 #address-cells = <1>;
971 gsbi2: gsbi@12480000 {
973 compatible = "qcom,gsbi-v1.0.0";
975 reg = <0x12480000 0x100>;
976 clocks = <&gcc GSBI2_H_CLK>;
977 clock-names = "iface";
978 #address-cells = <1>;
982 syscon-tcsr = <&tcsr>;
984 gsbi2_i2c: i2c@124a0000 {
985 compatible = "qcom,i2c-qup-v1.1.1";
986 reg = <0x124a0000 0x1000>;
987 pinctrl-0 = <&i2c2_pins>;
988 pinctrl-1 = <&i2c2_pins_sleep>;
989 pinctrl-names = "default", "sleep";
990 interrupts = <0 196 IRQ_TYPE_NONE>;
991 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
992 clock-names = "core", "iface";
993 #address-cells = <1>;
998 gsbi3: gsbi@16200000 {
1000 compatible = "qcom,gsbi-v1.0.0";
1002 reg = <0x16200000 0x100>;
1003 clocks = <&gcc GSBI3_H_CLK>;
1004 clock-names = "iface";
1005 #address-cells = <1>;
1008 gsbi3_i2c: i2c@16280000 {
1009 compatible = "qcom,i2c-qup-v1.1.1";
1010 pinctrl-0 = <&i2c3_pins>;
1011 pinctrl-1 = <&i2c3_pins_sleep>;
1012 pinctrl-names = "default", "sleep";
1013 reg = <0x16280000 0x1000>;
1014 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
1015 clocks = <&gcc GSBI3_QUP_CLK>,
1017 clock-names = "core", "iface";
1018 #address-cells = <1>;
1023 gsbi4: gsbi@16300000 {
1024 status = "disabled";
1025 compatible = "qcom,gsbi-v1.0.0";
1027 reg = <0x16300000 0x03>;
1028 clocks = <&gcc GSBI4_H_CLK>;
1029 clock-names = "iface";
1030 #address-cells = <1>;
1034 gsbi4_i2c: i2c@16380000 {
1035 compatible = "qcom,i2c-qup-v1.1.1";
1036 pinctrl-0 = <&i2c4_pins>;
1037 pinctrl-1 = <&i2c4_pins_sleep>;
1038 pinctrl-names = "default", "sleep";
1039 reg = <0x16380000 0x1000>;
1040 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
1041 clocks = <&gcc GSBI4_QUP_CLK>,
1043 clock-names = "core", "iface";
1047 gsbi5: gsbi@1a200000 {
1048 status = "disabled";
1049 compatible = "qcom,gsbi-v1.0.0";
1051 reg = <0x1a200000 0x03>;
1052 clocks = <&gcc GSBI5_H_CLK>;
1053 clock-names = "iface";
1054 #address-cells = <1>;
1058 gsbi5_serial: serial@1a240000 {
1059 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1060 reg = <0x1a240000 0x100>,
1062 interrupts = <0 154 0x0>;
1063 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1064 clock-names = "core", "iface";
1065 status = "disabled";
1068 gsbi5_spi: spi@1a280000 {
1069 compatible = "qcom,spi-qup-v1.1.1";
1070 reg = <0x1a280000 0x1000>;
1071 interrupts = <0 155 0>;
1072 pinctrl-0 = <&spi5_default>;
1073 pinctrl-1 = <&spi5_sleep>;
1074 pinctrl-names = "default", "sleep";
1075 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1076 clock-names = "core", "iface";
1077 status = "disabled";
1078 #address-cells = <1>;
1083 gsbi6: gsbi@16500000 {
1084 status = "disabled";
1085 compatible = "qcom,gsbi-v1.0.0";
1087 reg = <0x16500000 0x03>;
1088 clocks = <&gcc GSBI6_H_CLK>;
1089 clock-names = "iface";
1090 #address-cells = <1>;
1093 syscon-tcsr = <&tcsr>;
1095 gsbi6_serial: serial@16540000 {
1096 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1097 reg = <0x16540000 0x100>,
1099 interrupts = <0 156 0x0>;
1100 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1101 clock-names = "core", "iface";
1103 qcom,rx-crci = <11>;
1106 dmas = <&adm 6>, <&adm 7>;
1107 dma-names = "rx", "tx";
1109 status = "disabled";
1112 gsbi6_i2c: i2c@16580000 {
1113 compatible = "qcom,i2c-qup-v1.1.1";
1114 pinctrl-0 = <&i2c6_pins>;
1115 pinctrl-1 = <&i2c6_pins_sleep>;
1116 pinctrl-names = "default", "sleep";
1117 reg = <0x16580000 0x1000>;
1118 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
1119 clocks = <&gcc GSBI6_QUP_CLK>,
1121 clock-names = "core", "iface";
1125 gsbi7: gsbi@16600000 {
1126 status = "disabled";
1127 compatible = "qcom,gsbi-v1.0.0";
1129 reg = <0x16600000 0x100>;
1130 clocks = <&gcc GSBI7_H_CLK>;
1131 clock-names = "iface";
1132 #address-cells = <1>;
1135 syscon-tcsr = <&tcsr>;
1137 gsbi7_serial: serial@16640000 {
1138 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1139 reg = <0x16640000 0x1000>,
1140 <0x16600000 0x1000>;
1141 interrupts = <0 158 0x0>;
1142 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1143 clock-names = "core", "iface";
1144 status = "disabled";
1147 gsbi7_i2c: i2c@16680000 {
1148 compatible = "qcom,i2c-qup-v1.1.1";
1149 pinctrl-0 = <&i2c7_pins>;
1150 pinctrl-1 = <&i2c7_pins_sleep>;
1151 pinctrl-names = "default", "sleep";
1152 reg = <0x16680000 0x1000>;
1153 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
1154 clocks = <&gcc GSBI7_QUP_CLK>,
1156 clock-names = "core", "iface";
1157 status = "disabled";
1162 compatible = "qcom,prng";
1163 reg = <0x1a500000 0x200>;
1164 clocks = <&gcc PRNG_CLK>;
1165 clock-names = "core";
1169 compatible = "qcom,ssbi";
1170 reg = <0x00500000 0x1000>;
1171 qcom,controller-type = "pmic-arbiter";
1174 compatible = "qcom,pm8921";
1175 interrupt-parent = <&tlmm_pinmux>;
1176 interrupts = <74 8>;
1177 #interrupt-cells = <2>;
1178 interrupt-controller;
1179 #address-cells = <1>;
1182 pm8921_gpio: gpio@150 {
1184 compatible = "qcom,pm8921-gpio",
1187 interrupts = <192 1>, <193 1>, <194 1>,
1188 <195 1>, <196 1>, <197 1>,
1189 <198 1>, <199 1>, <200 1>,
1190 <201 1>, <202 1>, <203 1>,
1191 <204 1>, <205 1>, <206 1>,
1192 <207 1>, <208 1>, <209 1>,
1193 <210 1>, <211 1>, <212 1>,
1194 <213 1>, <214 1>, <215 1>,
1195 <216 1>, <217 1>, <218 1>,
1196 <219 1>, <220 1>, <221 1>,
1197 <222 1>, <223 1>, <224 1>,
1198 <225 1>, <226 1>, <227 1>,
1199 <228 1>, <229 1>, <230 1>,
1200 <231 1>, <232 1>, <233 1>,
1208 pm8921_mpps: mpps@50 {
1209 compatible = "qcom,pm8921-mpp",
1215 <128 1>, <129 1>, <130 1>, <131 1>,
1216 <132 1>, <133 1>, <134 1>, <135 1>,
1217 <136 1>, <137 1>, <138 1>, <139 1>;
1221 compatible = "qcom,pm8921-rtc";
1222 interrupt-parent = <&pmicintc>;
1223 interrupts = <39 1>;
1229 compatible = "qcom,pm8921-pwrkey";
1231 interrupt-parent = <&pmicintc>;
1232 interrupts = <50 1>, <51 1>;
1239 qfprom: qfprom@00700000 {
1240 compatible = "qcom,qfprom";
1241 reg = <0x00700000 0x1000>;
1242 #address-cells = <1>;
1245 tsens_calib: calib {
1248 tsens_backup: backup_calib {
1253 gcc: clock-controller@900000 {
1254 compatible = "qcom,gcc-apq8064";
1255 reg = <0x00900000 0x4000>;
1256 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1257 nvmem-cell-names = "calib", "calib_backup";
1258 qcom,tsens-slopes = <1176 1176 1154 1176 1111
1259 1132 1132 1199 1132 1199 1132>;
1262 #thermal-sensor-cells = <1>;
1265 lcc: clock-controller@28000000 {
1266 compatible = "qcom,lcc-apq8064";
1267 reg = <0x28000000 0x1000>;
1272 mmcc: clock-controller@4000000 {
1273 compatible = "qcom,mmcc-apq8064";
1274 reg = <0x4000000 0x1000>;
1279 l2cc: clock-controller@2011000 {
1280 compatible = "syscon";
1281 reg = <0x2011000 0x1000>;
1285 compatible = "qcom,rpm-apq8064";
1286 reg = <0x108000 0x1000>;
1287 qcom,ipc = <&l2cc 0x8 2>;
1289 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1290 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1291 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1292 interrupt-names = "ack", "err", "wakeup";
1294 rpmcc: clock-controller {
1295 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1300 compatible = "qcom,rpm-pm8921-regulators";
1336 pm8921_lvs1: lvs1 {};
1337 pm8921_lvs2: lvs2 {};
1338 pm8921_lvs3: lvs3 {};
1339 pm8921_lvs4: lvs4 {};
1340 pm8921_lvs5: lvs5 {};
1341 pm8921_lvs6: lvs6 {};
1342 pm8921_lvs7: lvs7 {};
1344 pm8921_usb_switch: usb-switch {};
1346 pm8921_hdmi_switch: hdmi-switch {
1354 wcnss-rproc@3204000 {
1355 compatible = "qcom,riva-pil";
1356 reg = <0x03204000 0x100>;
1358 interrupts-extended = <&intc 0 199 IRQ_TYPE_EDGE_RISING>,
1359 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1360 interrupt-names = "wdog", "fatal";
1362 memory-region = <&wcnss_mem>;
1364 vddcx-supply = <&pm8921_s3>;
1365 vddmx-supply = <&pm8921_l24>;
1366 vddpx-supply = <&pm8921_s4>;
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&wcnss_pin_a>;
1372 compatible = "qcom,wcn3660";
1374 clocks = <&rpmcc 9>;
1377 vddxo-supply = <&pm8921_l4>;
1378 vddrfa-supply = <&pm8921_s2>;
1379 vddpa-supply = <&pm8921_l10>;
1380 vdddig-supply = <&pm8921_lvs2>;
1385 usb1_phy: phy@12500000 {
1386 compatible = "qcom,usb-otg-ci";
1387 reg = <0x12500000 0x400>;
1388 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1389 status = "disabled";
1392 clocks = <&gcc USB_HS1_XCVR_CLK>,
1393 <&gcc USB_HS1_H_CLK>;
1394 clock-names = "core", "iface";
1396 resets = <&gcc USB_HS1_RESET>;
1397 reset-names = "link";
1400 usb3_phy: phy@12520000 {
1401 compatible = "qcom,usb-otg-ci";
1402 reg = <0x12520000 0x400>;
1403 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1404 status = "disabled";
1407 clocks = <&gcc USB_HS3_XCVR_CLK>,
1408 <&gcc USB_HS3_H_CLK>;
1409 clock-names = "core", "iface";
1411 resets = <&gcc USB_HS3_RESET>;
1412 reset-names = "link";
1415 usb4_phy: phy@12530000 {
1416 compatible = "qcom,usb-otg-ci";
1417 reg = <0x12530000 0x400>;
1418 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1419 status = "disabled";
1422 clocks = <&gcc USB_HS4_XCVR_CLK>,
1423 <&gcc USB_HS4_H_CLK>;
1424 clock-names = "core", "iface";
1426 resets = <&gcc USB_HS4_RESET>;
1427 reset-names = "link";
1430 gadget1: gadget@12500000 {
1431 compatible = "qcom,ci-hdrc";
1432 reg = <0x12500000 0x400>;
1433 status = "disabled";
1434 dr_mode = "peripheral";
1435 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1436 usb-phy = <&usb1_phy>;
1439 usb1: usb@12500000 {
1440 compatible = "qcom,ehci-host";
1441 reg = <0x12500000 0x400>;
1442 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1443 status = "disabled";
1444 usb-phy = <&usb1_phy>;
1447 usb3: usb@12520000 {
1448 compatible = "qcom,ehci-host";
1449 reg = <0x12520000 0x400>;
1450 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1451 status = "disabled";
1452 usb-phy = <&usb3_phy>;
1455 usb4: usb@12530000 {
1456 compatible = "qcom,ehci-host";
1457 reg = <0x12530000 0x400>;
1458 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1459 status = "disabled";
1460 usb-phy = <&usb4_phy>;
1463 sata_phy0: phy@1b400000 {
1464 compatible = "qcom,apq8064-sata-phy";
1465 status = "disabled";
1466 reg = <0x1b400000 0x200>;
1467 reg-names = "phy_mem";
1468 clocks = <&gcc SATA_PHY_CFG_CLK>;
1469 clock-names = "cfg";
1473 sata0: sata@29000000 {
1474 compatible = "qcom,apq8064-ahci", "generic-ahci";
1475 status = "disabled";
1476 reg = <0x29000000 0x180>;
1477 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1479 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1482 <&gcc SATA_RXOOB_CLK>,
1483 <&gcc SATA_PMALIVE_CLK>;
1484 clock-names = "slave_iface",
1490 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1491 <&gcc SATA_PMALIVE_CLK>;
1492 assigned-clock-rates = <100000000>, <100000000>;
1494 phys = <&sata_phy0>;
1495 phy-names = "sata-phy";
1496 ports-implemented = <0x1>;
1499 /* Temporary fixed regulator */
1500 sdcc1bam:dma@12402000{
1501 compatible = "qcom,bam-v1.3.0";
1502 reg = <0x12402000 0x8000>;
1503 interrupts = <0 98 0>;
1504 clocks = <&gcc SDC1_H_CLK>;
1505 clock-names = "bam_clk";
1510 sdcc3bam:dma@12182000{
1511 compatible = "qcom,bam-v1.3.0";
1512 reg = <0x12182000 0x8000>;
1513 interrupts = <0 96 0>;
1514 clocks = <&gcc SDC3_H_CLK>;
1515 clock-names = "bam_clk";
1520 sdcc4bam:dma@121c2000{
1521 compatible = "qcom,bam-v1.3.0";
1522 reg = <0x121c2000 0x8000>;
1523 interrupts = <0 95 0>;
1524 clocks = <&gcc SDC4_H_CLK>;
1525 clock-names = "bam_clk";
1531 compatible = "arm,amba-bus";
1532 #address-cells = <1>;
1535 sdcc1: sdcc@12400000 {
1536 status = "disabled";
1537 compatible = "arm,pl18x", "arm,primecell";
1538 arm,primecell-periphid = <0x00051180>;
1539 reg = <0x12400000 0x2000>;
1540 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1541 interrupt-names = "cmd_irq";
1542 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1543 clock-names = "mclk", "apb_pclk";
1545 max-frequency = <96000000>;
1549 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1550 dma-names = "tx", "rx";
1553 sdcc3: sdcc@12180000 {
1554 compatible = "arm,pl18x", "arm,primecell";
1555 arm,primecell-periphid = <0x00051180>;
1556 status = "disabled";
1557 reg = <0x12180000 0x2000>;
1558 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1559 interrupt-names = "cmd_irq";
1560 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1561 clock-names = "mclk", "apb_pclk";
1565 max-frequency = <192000000>;
1567 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1568 dma-names = "tx", "rx";
1571 sdcc4: sdcc@121c0000 {
1572 compatible = "arm,pl18x", "arm,primecell";
1573 arm,primecell-periphid = <0x00051180>;
1574 status = "disabled";
1575 reg = <0x121c0000 0x2000>;
1576 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1577 interrupt-names = "cmd_irq";
1578 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1579 clock-names = "mclk", "apb_pclk";
1583 max-frequency = <48000000>;
1584 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1585 dma-names = "tx", "rx";
1586 pinctrl-names = "default";
1587 pinctrl-0 = <&sdc4_gpios>;
1592 compatible = "qcom,adm";
1593 reg = <0x18320000 0xE0000>;
1594 interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1597 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1598 clock-names = "core", "iface";
1600 resets = <&gcc ADM0_RESET>,
1601 <&gcc ADM0_PBUS_RESET>,
1602 <&gcc ADM0_C0_RESET>,
1603 <&gcc ADM0_C1_RESET>,
1604 <&gcc ADM0_C2_RESET>;
1605 reset-names = "clk", "pbus", "c0", "c1", "c2";
1608 status = "disabled";
1611 tcsr: syscon@1a400000 {
1612 compatible = "qcom,tcsr-apq8064", "syscon";
1613 reg = <0x1a400000 0x100>;
1616 pcie: pci@1b500000 {
1617 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1618 reg = <0x1b500000 0x1000
1621 0x0ff00000 0x100000>;
1622 reg-names = "dbi", "elbi", "parf", "config";
1623 device_type = "pci";
1624 linux,pci-domain = <0>;
1625 bus-range = <0x00 0xff>;
1627 #address-cells = <3>;
1629 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1630 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1631 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1632 interrupt-names = "msi";
1633 #interrupt-cells = <1>;
1634 interrupt-map-mask = <0 0 0 0x7>;
1635 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1636 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1637 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1638 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1639 clocks = <&gcc PCIE_A_CLK>,
1641 <&gcc PCIE_PHY_REF_CLK>;
1642 clock-names = "core", "iface", "phy";
1643 resets = <&gcc PCIE_ACLK_RESET>,
1644 <&gcc PCIE_HCLK_RESET>,
1645 <&gcc PCIE_POR_RESET>,
1646 <&gcc PCIE_PCI_RESET>,
1647 <&gcc PCIE_PHY_RESET>;
1648 reset-names = "axi", "ahb", "por", "pci", "phy";
1649 status = "disabled";
1652 pil_q6v4: pil@28800000 {
1653 compatible = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1654 qcom,firmware-name = "q6";
1655 reg = <0x28800000 0x100>;
1656 reg-names = "qdsp6_base";
1657 qcom,pas-id = <1>; /* PAS_Q6 */
1661 compatible = "qcom,msm-dai-fe";
1662 #sound-dai-cells = <0>;
1665 hdmi_dai: dai_hdmi {
1666 compatible = "qcom,msm-dai-q6-hdmi";
1667 #sound-dai-cells = <0>;
1670 hdmi_codec: codec_hdmi {
1671 compatible = "linux,hdmi-audio";
1672 #sound-dai-cells = <0>;
1676 compatible = "qcom,msm-pcm-dsp";
1677 #sound-dai-cells = <0>;
1680 q6_route: msm_pcm_routing {
1681 compatible = "qcom,msm-pcm-routing";
1682 #sound-dai-cells = <0>;
1686 compatible = "qcom,snd-apq8064";
1690 hdmi: qcom,hdmi-tx@4a00000 {
1691 compatible = "qcom,hdmi-tx-8960";
1692 reg-names = "core_physical";
1693 reg = <0x04a00000 0x1000>;
1694 interrupts = <GIC_SPI 79 0>;
1700 <&mmcc HDMI_APP_CLK>,
1701 <&mmcc HDMI_M_AHB_CLK>,
1702 <&mmcc HDMI_S_AHB_CLK>;
1703 qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1704 qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1705 qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1706 pinctrl-names = "default";
1707 pinctrl-0 = <&hdmi_pinctrl>;
1710 gpu: qcom,adreno-3xx@4300000 {
1711 compatible = "qcom,adreno-3xx";
1712 reg = <0x04300000 0x20000>;
1713 reg-names = "kgsl_3d0_reg_memory";
1714 interrupts = <GIC_SPI 80 0>;
1715 interrupt-names = "kgsl_3d0_irq";
1723 <&mmcc GFX3D_AHB_CLK>,
1724 <&mmcc GFX3D_AXI_CLK>,
1725 <&mmcc MMSS_IMEM_AHB_CLK>;
1726 qcom,chipid = <0x03020002>;
1728 iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1729 &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1730 &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1731 &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1733 qcom,gpu-pwrlevels {
1734 compatible = "qcom,gpu-pwrlevels";
1735 qcom,gpu-pwrlevel@0 {
1736 qcom,gpu-freq = <450000000>;
1738 qcom,gpu-pwrlevel@1 {
1739 qcom,gpu-freq = <27000000>;
1744 mdp: qcom,mdp@5100000 {
1745 compatible = "qcom,mdp";
1746 reg = <0x05100000 0xf0000>;
1747 interrupts = <GIC_SPI 75 0>;
1748 connectors = <&hdmi>;
1760 <&mmcc MDP_AHB_CLK>,
1761 <&mmcc MDP_LUT_CLK>,
1763 <&mmcc HDMI_TV_CLK>,
1765 <&mmcc MDP_AXI_CLK>;
1767 iommus = <&mdp_port0 0 2
1771 mdp_port0: qcom,iommu@7500000 {
1772 compatible = "qcom,iommu-v0";
1778 <&mmcc SMMU_AHB_CLK>,
1779 <&mmcc MDP_AXI_CLK>;
1780 reg = <0x07500000 0x100000>;
1787 mdp_port1: qcom,iommu@7600000 {
1788 compatible = "qcom,iommu";
1794 <&mmcc SMMU_AHB_CLK>,
1795 <&mmcc MDP_AXI_CLK>;
1796 reg = <0x07600000 0x100000>;
1803 gfx3d: qcom,iommu@7c00000 {
1804 compatible = "qcom,iommu-v0";
1805 #iommu-cells = <16>;
1810 <&mmcc SMMU_AHB_CLK>,
1811 <&mmcc GFX3D_AXI_CLK>;
1812 reg = <0x07c00000 0x100000>;
1819 gfx3d1: qcom,iommu@7d00000 {
1820 compatible = "qcom,iommu-v0";
1821 #iommu-cells = <16>;
1826 <&mmcc SMMU_AHB_CLK>,
1827 <&mmcc GFX3D_AXI_CLK>;
1828 reg = <0x07d00000 0x100000>;
1837 #include "qcom-apq8064-coresight.dtsi"
1838 #include "qcom-apq8064-pins.dtsi"