3 #include "skeleton.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
37 next-level-cache = <&L2>;
40 cpu-idle-states = <&CPU_SPC>;
41 clocks = <&kraitcc 0>;
43 clock-latency = <100000>;
44 cooling-min-level = <0>;
45 cooling-max-level = <7>;
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
58 clocks = <&kraitcc 1>;
60 clock-latency = <100000>;
61 cooling-min-level = <0>;
62 cooling-max-level = <7>;
67 compatible = "qcom,krait";
68 enable-method = "qcom,kpss-acc-v1";
71 next-level-cache = <&L2>;
74 cpu-idle-states = <&CPU_SPC>;
75 clocks = <&kraitcc 2>;
77 clock-latency = <100000>;
78 cooling-min-level = <0>;
79 cooling-max-level = <7>;
84 compatible = "qcom,krait";
85 enable-method = "qcom,kpss-acc-v1";
88 next-level-cache = <&L2>;
91 cpu-idle-states = <&CPU_SPC>;
92 clocks = <&kraitcc 3>;
94 clock-latency = <100000>;
95 cooling-min-level = <0>;
96 cooling-max-level = <7>;
101 compatible = "cache";
107 compatible = "qcom,idle-state-spc",
109 entry-latency-us = <400>;
110 exit-latency-us = <900>;
111 min-residency-us = <3000>;
118 polling-delay-passive = <250>;
119 polling-delay = <1000>;
121 thermal-sensors = <&tsens 7>;
125 temperature = <75000>;
130 temperature = <95000>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
145 polling-delay-passive = <250>;
146 polling-delay = <1000>;
148 thermal-sensors = <&tsens 8>;
152 temperature = <75000>;
157 temperature = <95000>;
165 trip = <&cpu_alert1>;
166 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
172 polling-delay-passive = <250>;
173 polling-delay = <1000>;
175 thermal-sensors = <&tsens 9>;
179 temperature = <75000>;
184 temperature = <95000>;
192 trip = <&cpu_alert2>;
193 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
199 polling-delay-passive = <250>;
200 polling-delay = <1000>;
202 thermal-sensors = <&tsens 10>;
206 temperature = <75000>;
211 temperature = <95000>;
219 trip = <&cpu_alert3>;
220 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 compatible = "qcom,krait-pmu";
228 interrupts = <1 10 0x304>;
233 compatible = "fixed-clock";
235 clock-frequency = <19200000>;
239 compatible = "fixed-clock";
241 clock-frequency = <27000000>;
245 compatible = "fixed-clock";
247 clock-frequency = <32768>;
251 sfpb_mutex: hwmutex {
252 compatible = "qcom,sfpb-mutex";
253 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
258 compatible = "qcom,smem";
259 memory-region = <&smem_region>;
261 hwlocks = <&sfpb_mutex 3>;
266 qcom,speed0-pvs0-bin-v0 =
267 < 384000000 950000 >,
268 < 486000000 975000 >,
269 < 594000000 1000000 >,
270 < 702000000 1025000 >,
271 < 810000000 1075000 >,
272 < 918000000 1100000 >,
273 < 1026000000 1125000 >,
274 < 1080000000 1175000 >,
275 < 1134000000 1175000 >,
276 < 1188000000 1200000 >,
277 < 1242000000 1200000 >,
278 < 1296000000 1225000 >,
279 < 1350000000 1225000 >,
280 < 1404000000 1237500 >,
281 < 1458000000 1237500 >,
282 < 1512000000 1250000 >;
284 qcom,speed0-pvs1-bin-v0 =
285 < 384000000 900000 >,
286 < 486000000 925000 >,
287 < 594000000 950000 >,
288 < 702000000 975000 >,
289 < 810000000 1025000 >,
290 < 918000000 1050000 >,
291 < 1026000000 1075000 >,
292 < 1080000000 1125000 >,
293 < 1134000000 1125000 >,
294 < 1188000000 1150000 >,
295 < 1242000000 1150000 >,
296 < 1296000000 1175000 >,
297 < 1350000000 1175000 >,
298 < 1404000000 1187500 >,
299 < 1458000000 1187500 >,
300 < 1512000000 1200000 >;
302 qcom,speed0-pvs3-bin-v0 =
303 < 384000000 850000 >,
304 < 486000000 875000 >,
305 < 594000000 900000 >,
306 < 702000000 925000 >,
307 < 810000000 975000 >,
308 < 918000000 1000000 >,
309 < 1026000000 1025000 >,
310 < 1080000000 1075000 >,
311 < 1134000000 1075000 >,
312 < 1188000000 1100000 >,
313 < 1242000000 1100000 >,
314 < 1296000000 1125000 >,
315 < 1350000000 1125000 >,
316 < 1404000000 1137500 >,
317 < 1458000000 1137500 >,
318 < 1512000000 1150000 >;
320 qcom,speed0-pvs4-bin-v0 =
321 < 384000000 850000 >,
322 < 486000000 875000 >,
323 < 594000000 900000 >,
324 < 702000000 925000 >,
325 < 810000000 962500 >,
326 < 918000000 975000 >,
327 < 1026000000 1000000 >,
328 < 1080000000 1050000 >,
329 < 1134000000 1050000 >,
330 < 1188000000 1075000 >,
331 < 1242000000 1075000 >,
332 < 1296000000 1100000 >,
333 < 1350000000 1100000 >,
334 < 1404000000 1112500 >,
335 < 1458000000 1112500 >,
336 < 1512000000 1125000 >;
338 qcom,speed1-pvs0-bin-v0 =
339 < 384000000 950000 >,
340 < 486000000 950000 >,
341 < 594000000 950000 >,
342 < 702000000 962500 >,
343 < 810000000 1000000 >,
344 < 918000000 1025000 >,
345 < 1026000000 1037500 >,
346 < 1134000000 1075000 >,
347 < 1242000000 1087500 >,
348 < 1350000000 1125000 >,
349 < 1458000000 1150000 >,
350 < 1566000000 1175000 >,
351 < 1674000000 1225000 >,
352 < 1728000000 1250000 >;
354 qcom,speed1-pvs1-bin-v0 =
355 < 384000000 950000 >,
356 < 486000000 950000 >,
357 < 594000000 950000 >,
358 < 702000000 962500 >,
359 < 810000000 975000 >,
360 < 918000000 1000000 >,
361 < 1026000000 1012500 >,
362 < 1134000000 1037500 >,
363 < 1242000000 1050000 >,
364 < 1350000000 1087500 >,
365 < 1458000000 1112500 >,
366 < 1566000000 1150000 >,
367 < 1674000000 1187500 >,
368 < 1728000000 1200000 >;
370 qcom,speed1-pvs2-bin-v0 =
371 < 384000000 925000 >,
372 < 486000000 925000 >,
373 < 594000000 925000 >,
374 < 702000000 925000 >,
375 < 810000000 937500 >,
376 < 918000000 950000 >,
377 < 1026000000 975000 >,
378 < 1134000000 1000000 >,
379 < 1242000000 1012500 >,
380 < 1350000000 1037500 >,
381 < 1458000000 1075000 >,
382 < 1566000000 1100000 >,
383 < 1674000000 1137500 >,
384 < 1728000000 1162500 >;
386 qcom,speed1-pvs3-bin-v0 =
387 < 384000000 900000 >,
388 < 486000000 900000 >,
389 < 594000000 900000 >,
390 < 702000000 900000 >,
391 < 810000000 900000 >,
392 < 918000000 925000 >,
393 < 1026000000 950000 >,
394 < 1134000000 975000 >,
395 < 1242000000 987500 >,
396 < 1350000000 1000000 >,
397 < 1458000000 1037500 >,
398 < 1566000000 1062500 >,
399 < 1674000000 1100000 >,
400 < 1728000000 1125000 >;
402 qcom,speed1-pvs4-bin-v0 =
403 < 384000000 875000 >,
404 < 486000000 875000 >,
405 < 594000000 875000 >,
406 < 702000000 875000 >,
407 < 810000000 887500 >,
408 < 918000000 900000 >,
409 < 1026000000 925000 >,
410 < 1134000000 950000 >,
411 < 1242000000 962500 >,
412 < 1350000000 975000 >,
413 < 1458000000 1000000 >,
414 < 1566000000 1037500 >,
415 < 1674000000 1075000 >,
416 < 1728000000 1100000 >;
418 qcom,speed1-pvs5-bin-v0 =
419 < 384000000 875000 >,
420 < 486000000 875000 >,
421 < 594000000 875000 >,
422 < 702000000 875000 >,
423 < 810000000 887500 >,
424 < 918000000 900000 >,
425 < 1026000000 925000 >,
426 < 1134000000 937500 >,
427 < 1242000000 950000 >,
428 < 1350000000 962500 >,
429 < 1458000000 987500 >,
430 < 1566000000 1012500 >,
431 < 1674000000 1050000 >,
432 < 1728000000 1075000 >;
434 qcom,speed1-pvs6-bin-v0 =
435 < 384000000 875000 >,
436 < 486000000 875000 >,
437 < 594000000 875000 >,
438 < 702000000 875000 >,
439 < 810000000 887500 >,
440 < 918000000 900000 >,
441 < 1026000000 925000 >,
442 < 1134000000 937500 >,
443 < 1242000000 950000 >,
444 < 1350000000 962500 >,
445 < 1458000000 975000 >,
446 < 1566000000 1000000 >,
447 < 1674000000 1025000 >,
448 < 1728000000 1050000 >;
450 qcom,speed2-pvs0-bin-v0 =
451 < 384000000 950000 >,
452 < 486000000 950000 >,
453 < 594000000 950000 >,
454 < 702000000 950000 >,
455 < 810000000 962500 >,
456 < 918000000 975000 >,
457 < 1026000000 1000000 >,
458 < 1134000000 1025000 >,
459 < 1242000000 1037500 >,
460 < 1350000000 1062500 >,
461 < 1458000000 1100000 >,
462 < 1566000000 1125000 >,
463 < 1674000000 1175000 >,
464 < 1782000000 1225000 >,
465 < 1890000000 1287500 >;
467 qcom,speed2-pvs1-bin-v0 =
468 < 384000000 925000 >,
469 < 486000000 925000 >,
470 < 594000000 925000 >,
471 < 702000000 925000 >,
472 < 810000000 937500 >,
473 < 918000000 950000 >,
474 < 1026000000 975000 >,
475 < 1134000000 1000000 >,
476 < 1242000000 1012500 >,
477 < 1350000000 1037500 >,
478 < 1458000000 1075000 >,
479 < 1566000000 1100000 >,
480 < 1674000000 1137500 >,
481 < 1782000000 1187500 >,
482 < 1890000000 1250000 >;
484 qcom,speed2-pvs2-bin-v0 =
485 < 384000000 900000 >,
486 < 486000000 900000 >,
487 < 594000000 900000 >,
488 < 702000000 900000 >,
489 < 810000000 912500 >,
490 < 918000000 925000 >,
491 < 1026000000 950000 >,
492 < 1134000000 975000 >,
493 < 1242000000 987500 >,
494 < 1350000000 1012500 >,
495 < 1458000000 1050000 >,
496 < 1566000000 1075000 >,
497 < 1674000000 1112500 >,
498 < 1782000000 1162500 >,
499 < 1890000000 1212500 >;
501 qcom,speed2-pvs3-bin-v0 =
502 < 384000000 900000 >,
503 < 486000000 900000 >,
504 < 594000000 900000 >,
505 < 702000000 900000 >,
506 < 810000000 900000 >,
507 < 918000000 912500 >,
508 < 1026000000 937500 >,
509 < 1134000000 962500 >,
510 < 1242000000 975000 >,
511 < 1350000000 1000000 >,
512 < 1458000000 1025000 >,
513 < 1566000000 1050000 >,
514 < 1674000000 1087500 >,
515 < 1782000000 1137500 >,
516 < 1890000000 1175000 >;
518 qcom,speed2-pvs4-bin-v0 =
519 < 384000000 875000 >,
520 < 486000000 875000 >,
521 < 594000000 875000 >,
522 < 702000000 875000 >,
523 < 810000000 887500 >,
524 < 918000000 900000 >,
525 < 1026000000 925000 >,
526 < 1134000000 950000 >,
527 < 1242000000 962500 >,
528 < 1350000000 975000 >,
529 < 1458000000 1000000 >,
530 < 1566000000 1037500 >,
531 < 1674000000 1075000 >,
532 < 1782000000 1112500 >,
533 < 1890000000 1150000 >;
535 qcom,speed2-pvs5-bin-v0 =
536 < 384000000 875000 >,
537 < 486000000 875000 >,
538 < 594000000 875000 >,
539 < 702000000 875000 >,
540 < 810000000 887500 >,
541 < 918000000 900000 >,
542 < 1026000000 925000 >,
543 < 1134000000 937500 >,
544 < 1242000000 950000 >,
545 < 1350000000 962500 >,
546 < 1458000000 987500 >,
547 < 1566000000 1012500 >,
548 < 1674000000 1050000 >,
549 < 1782000000 1087500 >,
550 < 1890000000 1125000 >;
552 qcom,speed2-pvs6-bin-v0 =
553 < 384000000 875000 >,
554 < 486000000 875000 >,
555 < 594000000 875000 >,
556 < 702000000 875000 >,
557 < 810000000 887500 >,
558 < 918000000 900000 >,
559 < 1026000000 925000 >,
560 < 1134000000 937500 >,
561 < 1242000000 950000 >,
562 < 1350000000 962500 >,
563 < 1458000000 975000 >,
564 < 1566000000 1000000 >,
565 < 1674000000 1025000 >,
566 < 1782000000 1062500 >,
567 < 1890000000 1100000 >;
569 qcom,speed14-pvs0-bin-v0 =
570 < 384000000 950000 >,
571 < 486000000 950000 >,
572 < 594000000 950000 >,
573 < 702000000 962500 >,
574 < 810000000 1000000 >,
575 < 918000000 1025000 >,
576 < 1026000000 1037500 >,
577 < 1134000000 1075000 >,
578 < 1242000000 1087500 >,
579 < 1350000000 1125000 >,
580 < 1458000000 1150000 >,
581 < 1512000000 1162500 >;
583 qcom,speed14-pvs1-bin-v0 =
584 < 384000000 950000 >,
585 < 486000000 950000 >,
586 < 594000000 950000 >,
587 < 702000000 962500 >,
588 < 810000000 975000 >,
589 < 918000000 1000000 >,
590 < 1026000000 1012500 >,
591 < 1134000000 1037500 >,
592 < 1242000000 1050000 >,
593 < 1350000000 1087500 >,
594 < 1458000000 1112500 >,
595 < 1512000000 1125000 >;
597 qcom,speed14-pvs2-bin-v0 =
598 < 384000000 925000 >,
599 < 486000000 925000 >,
600 < 594000000 925000 >,
601 < 702000000 925000 >,
602 < 810000000 937500 >,
603 < 918000000 950000 >,
604 < 1026000000 975000 >,
605 < 1134000000 1000000 >,
606 < 1242000000 1012500 >,
607 < 1350000000 1037500 >,
608 < 1458000000 1075000 >,
609 < 1512000000 1087500 >;
611 qcom,speed14-pvs3-bin-v0 =
612 < 384000000 900000 >,
613 < 486000000 900000 >,
614 < 594000000 900000 >,
615 < 702000000 900000 >,
616 < 810000000 900000 >,
617 < 918000000 925000 >,
618 < 1026000000 950000 >,
619 < 1134000000 975000 >,
620 < 1242000000 987500 >,
621 < 1350000000 1000000 >,
622 < 1458000000 1037500 >,
623 < 1512000000 1050000 >;
625 qcom,speed14-pvs4-bin-v0 =
626 < 384000000 875000 >,
627 < 486000000 875000 >,
628 < 594000000 875000 >,
629 < 702000000 875000 >,
630 < 810000000 887500 >,
631 < 918000000 900000 >,
632 < 1026000000 925000 >,
633 < 1134000000 950000 >,
634 < 1242000000 962500 >,
635 < 1350000000 975000 >,
636 < 1458000000 1000000 >,
637 < 1512000000 1012500 >;
639 qcom,speed14-pvs5-bin-v0 =
640 < 384000000 875000 >,
641 < 486000000 875000 >,
642 < 594000000 875000 >,
643 < 702000000 875000 >,
644 < 810000000 887500 >,
645 < 918000000 900000 >,
646 < 1026000000 925000 >,
647 < 1134000000 937500 >,
648 < 1242000000 950000 >,
649 < 1350000000 962500 >,
650 < 1458000000 987500 >,
651 < 1512000000 1000000 >;
653 qcom,speed14-pvs6-bin-v0 =
654 < 384000000 875000 >,
655 < 486000000 875000 >,
656 < 594000000 875000 >,
657 < 702000000 875000 >,
658 < 810000000 887500 >,
659 < 918000000 900000 >,
660 < 1026000000 925000 >,
661 < 1134000000 937500 >,
662 < 1242000000 950000 >,
663 < 1350000000 962500 >,
664 < 1458000000 975000 >,
665 < 1512000000 987500 >;
668 kraitcc: clock-controller {
669 compatible = "qcom,krait-cc-v1";
674 sleep_clk: sleep_clk {
675 compatible = "fixed-clock";
676 clock-frequency = <32768>;
682 #address-cells = <1>;
685 compatible = "simple-bus";
687 tlmm_pinmux: pinctrl@800000 {
688 compatible = "qcom,apq8064-pinctrl";
689 reg = <0x800000 0x4000>;
693 interrupt-controller;
694 #interrupt-cells = <2>;
695 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&ps_hold>;
700 sdc4_gpios: sdc4-gpios {
702 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
707 hdmi_pinctrl: hdmi-pinctrl {
709 pins = "gpio69", "gpio70", "gpio71";
712 drive-strength = <2>;
718 drive-strength = <16>;
724 function = "ps_hold";
730 pins = "gpio20", "gpio21";
737 pins = "gpio8", "gpio9";
742 gsbi6_uart_2pins: gsbi6_uart_2pins {
744 pins = "gpio14", "gpio15";
749 gsbi6_uart_4pins: gsbi6_uart_4pins {
751 pins = "gpio14", "gpio15", "gpio16", "gpio17";
756 gsbi7_uart_2pins: gsbi7_uart_2pins {
758 pins = "gpio82", "gpio83";
763 gsbi7_uart_4pins: gsbi7_uart_4pins {
765 pins = "gpio82", "gpio83", "gpio84", "gpio85";
771 sfpb_wrapper_mutex: syscon@1200000 {
772 compatible = "syscon";
773 reg = <0x01200000 0x8000>;
776 intc: interrupt-controller@2000000 {
777 compatible = "qcom,msm-qgic2";
778 interrupt-controller;
779 #interrupt-cells = <3>;
780 reg = <0x02000000 0x1000>,
785 compatible = "qcom,kpss-timer", "qcom,msm-timer";
786 interrupts = <1 1 0x301>,
789 reg = <0x0200a000 0x100>;
790 clock-frequency = <27000000>,
792 cpu-offset = <0x80000>;
796 compatible = "qcom,kpss-wdt-apq8064";
797 reg = <0x0208a038 0x40>;
798 clocks = <&sleep_clk>;
802 acc0: clock-controller@2088000 {
803 compatible = "qcom,kpss-acc-v1";
804 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
805 clock-output-names = "acpu0_aux";
808 acc1: clock-controller@2098000 {
809 compatible = "qcom,kpss-acc-v1";
810 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
811 clock-output-names = "acpu1_aux";
814 acc2: clock-controller@20a8000 {
815 compatible = "qcom,kpss-acc-v1";
816 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
817 clock-output-names = "acpu2_aux";
820 acc3: clock-controller@20b8000 {
821 compatible = "qcom,kpss-acc-v1";
822 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
823 clock-output-names = "acpu3_aux";
826 saw0: power-controller@2089000 {
827 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
828 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
830 regulator-name = "krait0";
832 regulator-min-microvolt = <825000>;
833 regulator-max-microvolt = <1250000>;
836 saw1: power-controller@2099000 {
837 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
838 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
840 regulator-name = "krait1";
842 regulator-min-microvolt = <825000>;
843 regulator-max-microvolt = <1250000>;
846 saw2: power-controller@20a9000 {
847 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
848 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
850 regulator-name = "krait2";
852 regulator-min-microvolt = <825000>;
853 regulator-max-microvolt = <1250000>;
856 saw3: power-controller@20b9000 {
857 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
858 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
860 regulator-name = "krait3";
862 regulator-min-microvolt = <825000>;
863 regulator-max-microvolt = <1250000>;
866 gsbi1: gsbi@12440000 {
868 compatible = "qcom,gsbi-v1.0.0";
870 reg = <0x12440000 0x100>;
871 clocks = <&gcc GSBI1_H_CLK>;
872 clock-names = "iface";
873 #address-cells = <1>;
877 syscon-tcsr = <&tcsr>;
880 compatible = "qcom,i2c-qup-v1.1.1";
881 pinctrl-0 = <&i2c1_pins>;
882 pinctrl-names = "default";
883 reg = <0x12460000 0x1000>;
884 interrupts = <0 194 IRQ_TYPE_NONE>;
885 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
886 clock-names = "core", "iface";
887 #address-cells = <1>;
892 gsbi2: gsbi@12480000 {
894 compatible = "qcom,gsbi-v1.0.0";
896 reg = <0x12480000 0x100>;
897 clocks = <&gcc GSBI2_H_CLK>;
898 clock-names = "iface";
899 #address-cells = <1>;
903 syscon-tcsr = <&tcsr>;
906 compatible = "qcom,i2c-qup-v1.1.1";
907 reg = <0x124a0000 0x1000>;
908 interrupts = <0 196 IRQ_TYPE_NONE>;
909 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
910 clock-names = "core", "iface";
911 #address-cells = <1>;
916 gsbi3: gsbi@16200000 {
918 compatible = "qcom,gsbi-v1.0.0";
920 reg = <0x16200000 0x100>;
921 clocks = <&gcc GSBI3_H_CLK>;
922 clock-names = "iface";
923 #address-cells = <1>;
927 compatible = "qcom,i2c-qup-v1.1.1";
928 pinctrl-0 = <&i2c3_pins>;
929 pinctrl-names = "default";
930 reg = <0x16280000 0x1000>;
931 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
932 clocks = <&gcc GSBI3_QUP_CLK>,
934 clock-names = "core", "iface";
938 gsbi5: gsbi@1a200000 {
940 compatible = "qcom,gsbi-v1.0.0";
942 reg = <0x1a200000 0x03>;
943 clocks = <&gcc GSBI5_H_CLK>;
944 clock-names = "iface";
945 #address-cells = <1>;
949 gsbi5_serial: serial@1a240000 {
950 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
951 reg = <0x1a240000 0x100>,
953 interrupts = <0 154 0x0>;
954 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
955 clock-names = "core", "iface";
960 gsbi6: gsbi@16500000 {
962 compatible = "qcom,gsbi-v1.0.0";
964 reg = <0x16500000 0x03>;
965 clocks = <&gcc GSBI6_H_CLK>;
966 clock-names = "iface";
967 #address-cells = <1>;
971 gsbi6_serial: serial@16540000 {
972 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
973 reg = <0x16540000 0x100>,
975 interrupts = <0 156 0x0>;
976 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
977 clock-names = "core", "iface";
982 gsbi7: gsbi@16600000 {
984 compatible = "qcom,gsbi-v1.0.0";
986 reg = <0x16600000 0x100>;
987 clocks = <&gcc GSBI7_H_CLK>;
988 clock-names = "iface";
989 #address-cells = <1>;
992 syscon-tcsr = <&tcsr>;
994 gsbi7_serial: serial@16640000 {
995 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
996 reg = <0x16640000 0x1000>,
998 interrupts = <0 158 0x0>;
999 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1000 clock-names = "core", "iface";
1001 status = "disabled";
1006 compatible = "qcom,prng";
1007 reg = <0x1a500000 0x200>;
1008 clocks = <&gcc PRNG_CLK>;
1009 clock-names = "core";
1013 compatible = "qcom,ssbi";
1014 reg = <0x00500000 0x1000>;
1015 qcom,controller-type = "pmic-arbiter";
1018 compatible = "qcom,pm8921";
1019 interrupt-parent = <&tlmm_pinmux>;
1020 interrupts = <74 8>;
1021 #interrupt-cells = <2>;
1022 interrupt-controller;
1023 #address-cells = <1>;
1026 pm8921_gpio: gpio@150 {
1028 compatible = "qcom,pm8921-gpio",
1031 interrupts = <192 1>, <193 1>, <194 1>,
1032 <195 1>, <196 1>, <197 1>,
1033 <198 1>, <199 1>, <200 1>,
1034 <201 1>, <202 1>, <203 1>,
1035 <204 1>, <205 1>, <206 1>,
1036 <207 1>, <208 1>, <209 1>,
1037 <210 1>, <211 1>, <212 1>,
1038 <213 1>, <214 1>, <215 1>,
1039 <216 1>, <217 1>, <218 1>,
1040 <219 1>, <220 1>, <221 1>,
1041 <222 1>, <223 1>, <224 1>,
1042 <225 1>, <226 1>, <227 1>,
1043 <228 1>, <229 1>, <230 1>,
1044 <231 1>, <232 1>, <233 1>,
1052 pm8921_mpps: mpps@50 {
1053 compatible = "qcom,pm8921-mpp",
1059 <128 1>, <129 1>, <130 1>, <131 1>,
1060 <132 1>, <133 1>, <134 1>, <135 1>,
1061 <136 1>, <137 1>, <138 1>, <139 1>;
1065 compatible = "qcom,pm8921-rtc";
1066 interrupt-parent = <&pmicintc>;
1067 interrupts = <39 1>;
1073 compatible = "qcom,pm8921-pwrkey";
1075 interrupt-parent = <&pmicintc>;
1076 interrupts = <50 1>, <51 1>;
1083 gcc: clock-controller@900000 {
1084 compatible = "qcom,gcc-apq8064";
1085 reg = <0x00900000 0x4000>;
1090 lcc: clock-controller@28000000 {
1091 compatible = "qcom,lcc-apq8064";
1092 reg = <0x28000000 0x1000>;
1097 mmcc: clock-controller@4000000 {
1098 compatible = "qcom,mmcc-apq8064";
1099 reg = <0x4000000 0x1000>;
1104 l2cc: clock-controller@2011000 {
1105 compatible = "syscon";
1106 reg = <0x2011000 0x1000>;
1110 compatible = "qcom,rpm-apq8064";
1111 reg = <0x108000 0x1000>;
1112 qcom,ipc = <&l2cc 0x8 2>;
1114 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1115 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1116 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1117 interrupt-names = "ack", "err", "wakeup";
1120 compatible = "qcom,rpm-pm8921-regulators";
1156 pm8921_lvs1: lvs1 {};
1157 pm8921_lvs2: lvs2 {};
1158 pm8921_lvs3: lvs3 {};
1159 pm8921_lvs4: lvs4 {};
1160 pm8921_lvs5: lvs5 {};
1161 pm8921_lvs6: lvs6 {};
1162 pm8921_lvs7: lvs7 {};
1164 pm8921_usb_switch: usb-switch {};
1166 pm8921_hdmi_switch: hdmi-switch {
1174 usb1_phy: phy@12500000 {
1175 compatible = "qcom,usb-otg-ci";
1176 reg = <0x12500000 0x400>;
1177 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1178 status = "disabled";
1181 clocks = <&gcc USB_HS1_XCVR_CLK>,
1182 <&gcc USB_HS1_H_CLK>;
1183 clock-names = "core", "iface";
1185 resets = <&gcc USB_HS1_RESET>;
1186 reset-names = "link";
1189 usb3_phy: phy@12520000 {
1190 compatible = "qcom,usb-otg-ci";
1191 reg = <0x12520000 0x400>;
1192 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1193 status = "disabled";
1196 clocks = <&gcc USB_HS3_XCVR_CLK>,
1197 <&gcc USB_HS3_H_CLK>;
1198 clock-names = "core", "iface";
1200 resets = <&gcc USB_HS3_RESET>;
1201 reset-names = "link";
1204 usb4_phy: phy@12530000 {
1205 compatible = "qcom,usb-otg-ci";
1206 reg = <0x12530000 0x400>;
1207 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1208 status = "disabled";
1211 clocks = <&gcc USB_HS4_XCVR_CLK>,
1212 <&gcc USB_HS4_H_CLK>;
1213 clock-names = "core", "iface";
1215 resets = <&gcc USB_HS4_RESET>;
1216 reset-names = "link";
1219 gadget1: gadget@12500000 {
1220 compatible = "qcom,ci-hdrc";
1221 reg = <0x12500000 0x400>;
1222 status = "disabled";
1223 dr_mode = "peripheral";
1224 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1225 usb-phy = <&usb1_phy>;
1228 usb1: usb@12500000 {
1229 compatible = "qcom,ehci-host";
1230 reg = <0x12500000 0x400>;
1231 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1232 status = "disabled";
1233 usb-phy = <&usb1_phy>;
1236 usb3: usb@12520000 {
1237 compatible = "qcom,ehci-host";
1238 reg = <0x12520000 0x400>;
1239 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1240 status = "disabled";
1241 usb-phy = <&usb3_phy>;
1244 usb4: usb@12530000 {
1245 compatible = "qcom,ehci-host";
1246 reg = <0x12530000 0x400>;
1247 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1248 status = "disabled";
1249 usb-phy = <&usb4_phy>;
1252 sata_phy0: phy@1b400000 {
1253 compatible = "qcom,apq8064-sata-phy";
1254 status = "disabled";
1255 reg = <0x1b400000 0x200>;
1256 reg-names = "phy_mem";
1257 clocks = <&gcc SATA_PHY_CFG_CLK>;
1258 clock-names = "cfg";
1262 sata0: sata@29000000 {
1263 compatible = "generic-ahci";
1264 status = "disabled";
1265 reg = <0x29000000 0x180>;
1266 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1268 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1271 <&gcc SATA_RXOOB_CLK>,
1272 <&gcc SATA_PMALIVE_CLK>;
1273 clock-names = "slave_iface",
1279 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1280 <&gcc SATA_PMALIVE_CLK>;
1281 assigned-clock-rates = <100000000>, <100000000>;
1283 phys = <&sata_phy0>;
1284 phy-names = "sata-phy";
1287 /* Temporary fixed regulator */
1288 sdcc1bam:dma@12402000{
1289 compatible = "qcom,bam-v1.3.0";
1290 reg = <0x12402000 0x8000>;
1291 interrupts = <0 98 0>;
1292 clocks = <&gcc SDC1_H_CLK>;
1293 clock-names = "bam_clk";
1298 sdcc3bam:dma@12182000{
1299 compatible = "qcom,bam-v1.3.0";
1300 reg = <0x12182000 0x8000>;
1301 interrupts = <0 96 0>;
1302 clocks = <&gcc SDC3_H_CLK>;
1303 clock-names = "bam_clk";
1308 sdcc4bam:dma@121c2000{
1309 compatible = "qcom,bam-v1.3.0";
1310 reg = <0x121c2000 0x8000>;
1311 interrupts = <0 95 0>;
1312 clocks = <&gcc SDC4_H_CLK>;
1313 clock-names = "bam_clk";
1319 compatible = "arm,amba-bus";
1320 #address-cells = <1>;
1323 sdcc1: sdcc@12400000 {
1324 status = "disabled";
1325 compatible = "arm,pl18x", "arm,primecell";
1326 arm,primecell-periphid = <0x00051180>;
1327 reg = <0x12400000 0x2000>;
1328 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1329 interrupt-names = "cmd_irq";
1330 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1331 clock-names = "mclk", "apb_pclk";
1333 max-frequency = <96000000>;
1337 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1338 dma-names = "tx", "rx";
1341 sdcc3: sdcc@12180000 {
1342 compatible = "arm,pl18x", "arm,primecell";
1343 arm,primecell-periphid = <0x00051180>;
1344 status = "disabled";
1345 reg = <0x12180000 0x2000>;
1346 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1347 interrupt-names = "cmd_irq";
1348 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1349 clock-names = "mclk", "apb_pclk";
1353 max-frequency = <192000000>;
1355 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1356 dma-names = "tx", "rx";
1359 sdcc4: sdcc@121c0000 {
1360 compatible = "arm,pl18x", "arm,primecell";
1361 arm,primecell-periphid = <0x00051180>;
1362 status = "disabled";
1363 reg = <0x121c0000 0x2000>;
1364 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1365 interrupt-names = "cmd_irq";
1366 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1367 clock-names = "mclk", "apb_pclk";
1371 max-frequency = <48000000>;
1372 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1373 dma-names = "tx", "rx";
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&sdc4_gpios>;
1379 tcsr: syscon@1a400000 {
1380 compatible = "qcom,tcsr-apq8064", "syscon";
1381 reg = <0x1a400000 0x100>;
1384 pcie: pci@1b500000 {
1385 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1386 reg = <0x1b500000 0x1000
1389 0x0ff00000 0x100000>;
1390 reg-names = "dbi", "elbi", "parf", "config";
1391 device_type = "pci";
1392 linux,pci-domain = <0>;
1393 bus-range = <0x00 0xff>;
1395 #address-cells = <3>;
1397 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1398 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1399 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1400 interrupt-names = "msi";
1401 #interrupt-cells = <1>;
1402 interrupt-map-mask = <0 0 0 0x7>;
1403 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1404 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1405 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1406 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1407 clocks = <&gcc PCIE_A_CLK>,
1409 <&gcc PCIE_PHY_REF_CLK>;
1410 clock-names = "core", "iface", "phy";
1411 resets = <&gcc PCIE_ACLK_RESET>,
1412 <&gcc PCIE_HCLK_RESET>,
1413 <&gcc PCIE_POR_RESET>,
1414 <&gcc PCIE_PCI_RESET>,
1415 <&gcc PCIE_PHY_RESET>;
1416 reset-names = "axi", "ahb", "por", "pci", "phy";
1417 status = "disabled";
1420 hdmi: qcom,hdmi-tx@4a00000 {
1421 compatible = "qcom,hdmi-tx-8960";
1422 reg-names = "core_physical";
1423 reg = <0x04a00000 0x1000>;
1424 interrupts = <GIC_SPI 79 0>;
1430 <&mmcc HDMI_APP_CLK>,
1431 <&mmcc HDMI_M_AHB_CLK>,
1432 <&mmcc HDMI_S_AHB_CLK>;
1433 qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1434 qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1435 qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&hdmi_pinctrl>;
1440 gpu: qcom,adreno-3xx@4300000 {
1441 compatible = "qcom,adreno-3xx";
1442 reg = <0x04300000 0x20000>;
1443 reg-names = "kgsl_3d0_reg_memory";
1444 interrupts = <GIC_SPI 80 0>;
1445 interrupt-names = "kgsl_3d0_irq";
1453 <&mmcc GFX3D_AHB_CLK>,
1454 <&mmcc GFX3D_AXI_CLK>,
1455 <&mmcc MMSS_IMEM_AHB_CLK>;
1456 qcom,chipid = <0x03020002>;
1458 iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1459 &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1460 &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1461 &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1463 qcom,gpu-pwrlevels {
1464 compatible = "qcom,gpu-pwrlevels";
1465 qcom,gpu-pwrlevel@0 {
1466 qcom,gpu-freq = <450000000>;
1468 qcom,gpu-pwrlevel@1 {
1469 qcom,gpu-freq = <27000000>;
1474 mdp: qcom,mdp@5100000 {
1475 compatible = "qcom,mdp";
1476 reg = <0x05100000 0xf0000>;
1477 interrupts = <GIC_SPI 75 0>;
1478 connectors = <&hdmi>;
1490 <&mmcc MDP_AHB_CLK>,
1491 <&mmcc MDP_LUT_CLK>,
1493 <&mmcc HDMI_TV_CLK>,
1495 <&mmcc MDP_AXI_CLK>;
1497 iommus = <&mdp_port0 0 2
1501 mdp_port0: qcom,iommu@7500000 {
1502 compatible = "qcom,iommu-v0";
1508 <&mmcc SMMU_AHB_CLK>,
1509 <&mmcc MDP_AXI_CLK>;
1510 reg = <0x07500000 0x100000>;
1517 mdp_port1: qcom,iommu@7600000 {
1518 compatible = "qcom,iommu";
1524 <&mmcc SMMU_AHB_CLK>,
1525 <&mmcc MDP_AXI_CLK>;
1526 reg = <0x07600000 0x100000>;
1533 gfx3d: qcom,iommu@7c00000 {
1534 compatible = "qcom,iommu-v0";
1535 #iommu-cells = <16>;
1540 <&mmcc SMMU_AHB_CLK>,
1541 <&mmcc GFX3D_AXI_CLK>;
1542 reg = <0x07c00000 0x100000>;
1549 gfx3d1: qcom,iommu@7d00000 {
1550 compatible = "qcom,iommu-v0";
1551 #iommu-cells = <16>;
1556 <&mmcc SMMU_AHB_CLK>,
1557 <&mmcc GFX3D_AXI_CLK>;
1558 reg = <0x07d00000 0x100000>;