3 #include "skeleton.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
37 next-level-cache = <&L2>;
40 cpu-idle-states = <&CPU_SPC>;
41 clocks = <&kraitcc 0>, <&kraitcc 4>;
42 clock-names = "cpu", "l2";
43 clock-latency = <100000>;
44 cooling-min-level = <0>;
45 cooling-max-level = <7>;
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
58 clocks = <&kraitcc 1>, <&kraitcc 4>;
59 clock-names = "cpu", "l2";
60 clock-latency = <100000>;
61 cooling-min-level = <0>;
62 cooling-max-level = <7>;
67 compatible = "qcom,krait";
68 enable-method = "qcom,kpss-acc-v1";
71 next-level-cache = <&L2>;
74 cpu-idle-states = <&CPU_SPC>;
75 clocks = <&kraitcc 2>, <&kraitcc 4>;
76 clock-names = "cpu", "l2";
77 clock-latency = <100000>;
78 cooling-min-level = <0>;
79 cooling-max-level = <7>;
84 compatible = "qcom,krait";
85 enable-method = "qcom,kpss-acc-v1";
88 next-level-cache = <&L2>;
91 cpu-idle-states = <&CPU_SPC>;
92 clocks = <&kraitcc 3>, <&kraitcc 4>;
93 clock-names = "cpu", "l2";
94 clock-latency = <100000>;
95 cooling-min-level = <0>;
96 cooling-max-level = <7>;
101 compatible = "cache";
106 qcom,l2-rates = <384000000 972000000 1188000000>;
111 compatible = "qcom,idle-state-spc",
113 entry-latency-us = <400>;
114 exit-latency-us = <900>;
115 min-residency-us = <3000>;
122 polling-delay-passive = <250>;
123 polling-delay = <1000>;
125 thermal-sensors = <&tsens 7>;
129 temperature = <75000>;
134 temperature = <110000>;
142 trip = <&cpu_alert0>;
143 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 8>;
156 temperature = <75000>;
161 temperature = <110000>;
169 trip = <&cpu_alert1>;
170 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
176 polling-delay-passive = <250>;
177 polling-delay = <1000>;
179 thermal-sensors = <&tsens 9>;
183 temperature = <75000>;
188 temperature = <110000>;
196 trip = <&cpu_alert2>;
197 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
203 polling-delay-passive = <250>;
204 polling-delay = <1000>;
206 thermal-sensors = <&tsens 10>;
210 temperature = <75000>;
215 temperature = <110000>;
223 trip = <&cpu_alert3>;
224 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
232 polling-delay-passive = <250>;
233 polling-delay = <1000>;
235 thermal-sensors = <&gcc 7>;
239 temperature = <75000>;
244 temperature = <95000>;
252 polling-delay-passive = <250>;
253 polling-delay = <1000>;
255 thermal-sensors = <&gcc 8>;
259 temperature = <75000>;
264 temperature = <95000>;
272 polling-delay-passive = <250>;
273 polling-delay = <1000>;
275 thermal-sensors = <&gcc 9>;
279 temperature = <75000>;
284 temperature = <95000>;
292 polling-delay-passive = <250>;
293 polling-delay = <1000>;
295 thermal-sensors = <&gcc 10>;
299 temperature = <75000>;
304 temperature = <95000>;
313 compatible = "qcom,krait-pmu";
314 interrupts = <1 10 0x304>;
319 compatible = "fixed-clock";
321 clock-frequency = <19200000>;
325 compatible = "fixed-clock";
327 clock-frequency = <27000000>;
331 compatible = "fixed-clock";
333 clock-frequency = <32768>;
337 sfpb_mutex: hwmutex {
338 compatible = "qcom,sfpb-mutex";
339 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
344 compatible = "qcom,smem";
345 memory-region = <&smem_region>;
347 hwlocks = <&sfpb_mutex 3>;
352 qcom,speed0-pvs0-bin-v0 =
353 < 384000000 950000 >,
354 < 486000000 975000 >,
355 < 594000000 1000000 >,
356 < 702000000 1025000 >,
357 < 810000000 1075000 >,
358 < 918000000 1100000 >,
359 < 1026000000 1125000 >,
360 < 1080000000 1175000 >,
361 < 1134000000 1175000 >,
362 < 1188000000 1200000 >,
363 < 1242000000 1200000 >,
364 < 1296000000 1225000 >,
365 < 1350000000 1225000 >,
366 < 1404000000 1237500 >,
367 < 1458000000 1237500 >,
368 < 1512000000 1250000 >;
370 qcom,speed0-pvs1-bin-v0 =
371 < 384000000 900000 >,
372 < 486000000 925000 >,
373 < 594000000 950000 >,
374 < 702000000 975000 >,
375 < 810000000 1025000 >,
376 < 918000000 1050000 >,
377 < 1026000000 1075000 >,
378 < 1080000000 1125000 >,
379 < 1134000000 1125000 >,
380 < 1188000000 1150000 >,
381 < 1242000000 1150000 >,
382 < 1296000000 1175000 >,
383 < 1350000000 1175000 >,
384 < 1404000000 1187500 >,
385 < 1458000000 1187500 >,
386 < 1512000000 1200000 >;
388 qcom,speed0-pvs3-bin-v0 =
389 < 384000000 850000 >,
390 < 486000000 875000 >,
391 < 594000000 900000 >,
392 < 702000000 925000 >,
393 < 810000000 975000 >,
394 < 918000000 1000000 >,
395 < 1026000000 1025000 >,
396 < 1080000000 1075000 >,
397 < 1134000000 1075000 >,
398 < 1188000000 1100000 >,
399 < 1242000000 1100000 >,
400 < 1296000000 1125000 >,
401 < 1350000000 1125000 >,
402 < 1404000000 1137500 >,
403 < 1458000000 1137500 >,
404 < 1512000000 1150000 >;
406 qcom,speed0-pvs4-bin-v0 =
407 < 384000000 850000 >,
408 < 486000000 875000 >,
409 < 594000000 900000 >,
410 < 702000000 925000 >,
411 < 810000000 962500 >,
412 < 918000000 975000 >,
413 < 1026000000 1000000 >,
414 < 1080000000 1050000 >,
415 < 1134000000 1050000 >,
416 < 1188000000 1075000 >,
417 < 1242000000 1075000 >,
418 < 1296000000 1100000 >,
419 < 1350000000 1100000 >,
420 < 1404000000 1112500 >,
421 < 1458000000 1112500 >,
422 < 1512000000 1125000 >;
424 qcom,speed1-pvs0-bin-v0 =
425 < 384000000 950000 >,
426 < 486000000 950000 >,
427 < 594000000 950000 >,
428 < 702000000 962500 >,
429 < 810000000 1000000 >,
430 < 918000000 1025000 >,
431 < 1026000000 1037500 >,
432 < 1134000000 1075000 >,
433 < 1242000000 1087500 >,
434 < 1350000000 1125000 >,
435 < 1458000000 1150000 >,
436 < 1566000000 1175000 >,
437 < 1674000000 1225000 >,
438 < 1728000000 1250000 >;
440 qcom,speed1-pvs1-bin-v0 =
441 < 384000000 950000 >,
442 < 486000000 950000 >,
443 < 594000000 950000 >,
444 < 702000000 962500 >,
445 < 810000000 975000 >,
446 < 918000000 1000000 >,
447 < 1026000000 1012500 >,
448 < 1134000000 1037500 >,
449 < 1242000000 1050000 >,
450 < 1350000000 1087500 >,
451 < 1458000000 1112500 >,
452 < 1566000000 1150000 >,
453 < 1674000000 1187500 >,
454 < 1728000000 1200000 >;
456 qcom,speed1-pvs2-bin-v0 =
457 < 384000000 925000 >,
458 < 486000000 925000 >,
459 < 594000000 925000 >,
460 < 702000000 925000 >,
461 < 810000000 937500 >,
462 < 918000000 950000 >,
463 < 1026000000 975000 >,
464 < 1134000000 1000000 >,
465 < 1242000000 1012500 >,
466 < 1350000000 1037500 >,
467 < 1458000000 1075000 >,
468 < 1566000000 1100000 >,
469 < 1674000000 1137500 >,
470 < 1728000000 1162500 >;
472 qcom,speed1-pvs3-bin-v0 =
473 < 384000000 900000 >,
474 < 486000000 900000 >,
475 < 594000000 900000 >,
476 < 702000000 900000 >,
477 < 810000000 900000 >,
478 < 918000000 925000 >,
479 < 1026000000 950000 >,
480 < 1134000000 975000 >,
481 < 1242000000 987500 >,
482 < 1350000000 1000000 >,
483 < 1458000000 1037500 >,
484 < 1566000000 1062500 >,
485 < 1674000000 1100000 >,
486 < 1728000000 1125000 >;
488 qcom,speed1-pvs4-bin-v0 =
489 < 384000000 875000 >,
490 < 486000000 875000 >,
491 < 594000000 875000 >,
492 < 702000000 875000 >,
493 < 810000000 887500 >,
494 < 918000000 900000 >,
495 < 1026000000 925000 >,
496 < 1134000000 950000 >,
497 < 1242000000 962500 >,
498 < 1350000000 975000 >,
499 < 1458000000 1000000 >,
500 < 1566000000 1037500 >,
501 < 1674000000 1075000 >,
502 < 1728000000 1100000 >;
504 qcom,speed1-pvs5-bin-v0 =
505 < 384000000 875000 >,
506 < 486000000 875000 >,
507 < 594000000 875000 >,
508 < 702000000 875000 >,
509 < 810000000 887500 >,
510 < 918000000 900000 >,
511 < 1026000000 925000 >,
512 < 1134000000 937500 >,
513 < 1242000000 950000 >,
514 < 1350000000 962500 >,
515 < 1458000000 987500 >,
516 < 1566000000 1012500 >,
517 < 1674000000 1050000 >,
518 < 1728000000 1075000 >;
520 qcom,speed1-pvs6-bin-v0 =
521 < 384000000 875000 >,
522 < 486000000 875000 >,
523 < 594000000 875000 >,
524 < 702000000 875000 >,
525 < 810000000 887500 >,
526 < 918000000 900000 >,
527 < 1026000000 925000 >,
528 < 1134000000 937500 >,
529 < 1242000000 950000 >,
530 < 1350000000 962500 >,
531 < 1458000000 975000 >,
532 < 1566000000 1000000 >,
533 < 1674000000 1025000 >,
534 < 1728000000 1050000 >;
536 qcom,speed2-pvs0-bin-v0 =
537 < 384000000 950000 >,
538 < 486000000 950000 >,
539 < 594000000 950000 >,
540 < 702000000 950000 >,
541 < 810000000 962500 >,
542 < 918000000 975000 >,
543 < 1026000000 1000000 >,
544 < 1134000000 1025000 >,
545 < 1242000000 1037500 >,
546 < 1350000000 1062500 >,
547 < 1458000000 1100000 >,
548 < 1566000000 1125000 >,
549 < 1674000000 1175000 >,
550 < 1782000000 1225000 >,
551 < 1890000000 1287500 >;
553 qcom,speed2-pvs1-bin-v0 =
554 < 384000000 925000 >,
555 < 486000000 925000 >,
556 < 594000000 925000 >,
557 < 702000000 925000 >,
558 < 810000000 937500 >,
559 < 918000000 950000 >,
560 < 1026000000 975000 >,
561 < 1134000000 1000000 >,
562 < 1242000000 1012500 >,
563 < 1350000000 1037500 >,
564 < 1458000000 1075000 >,
565 < 1566000000 1100000 >,
566 < 1674000000 1137500 >,
567 < 1782000000 1187500 >,
568 < 1890000000 1250000 >;
570 qcom,speed2-pvs2-bin-v0 =
571 < 384000000 900000 >,
572 < 486000000 900000 >,
573 < 594000000 900000 >,
574 < 702000000 900000 >,
575 < 810000000 912500 >,
576 < 918000000 925000 >,
577 < 1026000000 950000 >,
578 < 1134000000 975000 >,
579 < 1242000000 987500 >,
580 < 1350000000 1012500 >,
581 < 1458000000 1050000 >,
582 < 1566000000 1075000 >,
583 < 1674000000 1112500 >,
584 < 1782000000 1162500 >,
585 < 1890000000 1212500 >;
587 qcom,speed2-pvs3-bin-v0 =
588 < 384000000 900000 >,
589 < 486000000 900000 >,
590 < 594000000 900000 >,
591 < 702000000 900000 >,
592 < 810000000 900000 >,
593 < 918000000 912500 >,
594 < 1026000000 937500 >,
595 < 1134000000 962500 >,
596 < 1242000000 975000 >,
597 < 1350000000 1000000 >,
598 < 1458000000 1025000 >,
599 < 1566000000 1050000 >,
600 < 1674000000 1087500 >,
601 < 1782000000 1137500 >,
602 < 1890000000 1175000 >;
604 qcom,speed2-pvs4-bin-v0 =
605 < 384000000 875000 >,
606 < 486000000 875000 >,
607 < 594000000 875000 >,
608 < 702000000 875000 >,
609 < 810000000 887500 >,
610 < 918000000 900000 >,
611 < 1026000000 925000 >,
612 < 1134000000 950000 >,
613 < 1242000000 962500 >,
614 < 1350000000 975000 >,
615 < 1458000000 1000000 >,
616 < 1566000000 1037500 >,
617 < 1674000000 1075000 >,
618 < 1782000000 1112500 >,
619 < 1890000000 1150000 >;
621 qcom,speed2-pvs5-bin-v0 =
622 < 384000000 875000 >,
623 < 486000000 875000 >,
624 < 594000000 875000 >,
625 < 702000000 875000 >,
626 < 810000000 887500 >,
627 < 918000000 900000 >,
628 < 1026000000 925000 >,
629 < 1134000000 937500 >,
630 < 1242000000 950000 >,
631 < 1350000000 962500 >,
632 < 1458000000 987500 >,
633 < 1566000000 1012500 >,
634 < 1674000000 1050000 >,
635 < 1782000000 1087500 >,
636 < 1890000000 1125000 >;
638 qcom,speed2-pvs6-bin-v0 =
639 < 384000000 875000 >,
640 < 486000000 875000 >,
641 < 594000000 875000 >,
642 < 702000000 875000 >,
643 < 810000000 887500 >,
644 < 918000000 900000 >,
645 < 1026000000 925000 >,
646 < 1134000000 937500 >,
647 < 1242000000 950000 >,
648 < 1350000000 962500 >,
649 < 1458000000 975000 >,
650 < 1566000000 1000000 >,
651 < 1674000000 1025000 >,
652 < 1782000000 1062500 >,
653 < 1890000000 1100000 >;
655 qcom,speed14-pvs0-bin-v0 =
656 < 384000000 950000 >,
657 < 486000000 950000 >,
658 < 594000000 950000 >,
659 < 702000000 962500 >,
660 < 810000000 1000000 >,
661 < 918000000 1025000 >,
662 < 1026000000 1037500 >,
663 < 1134000000 1075000 >,
664 < 1242000000 1087500 >,
665 < 1350000000 1125000 >,
666 < 1458000000 1150000 >,
667 < 1512000000 1162500 >;
669 qcom,speed14-pvs1-bin-v0 =
670 < 384000000 950000 >,
671 < 486000000 950000 >,
672 < 594000000 950000 >,
673 < 702000000 962500 >,
674 < 810000000 975000 >,
675 < 918000000 1000000 >,
676 < 1026000000 1012500 >,
677 < 1134000000 1037500 >,
678 < 1242000000 1050000 >,
679 < 1350000000 1087500 >,
680 < 1458000000 1112500 >,
681 < 1512000000 1125000 >;
683 qcom,speed14-pvs2-bin-v0 =
684 < 384000000 925000 >,
685 < 486000000 925000 >,
686 < 594000000 925000 >,
687 < 702000000 925000 >,
688 < 810000000 937500 >,
689 < 918000000 950000 >,
690 < 1026000000 975000 >,
691 < 1134000000 1000000 >,
692 < 1242000000 1012500 >,
693 < 1350000000 1037500 >,
694 < 1458000000 1075000 >,
695 < 1512000000 1087500 >;
697 qcom,speed14-pvs3-bin-v0 =
698 < 384000000 900000 >,
699 < 486000000 900000 >,
700 < 594000000 900000 >,
701 < 702000000 900000 >,
702 < 810000000 900000 >,
703 < 918000000 925000 >,
704 < 1026000000 950000 >,
705 < 1134000000 975000 >,
706 < 1242000000 987500 >,
707 < 1350000000 1000000 >,
708 < 1458000000 1037500 >,
709 < 1512000000 1050000 >;
711 qcom,speed14-pvs4-bin-v0 =
712 < 384000000 875000 >,
713 < 486000000 875000 >,
714 < 594000000 875000 >,
715 < 702000000 875000 >,
716 < 810000000 887500 >,
717 < 918000000 900000 >,
718 < 1026000000 925000 >,
719 < 1134000000 950000 >,
720 < 1242000000 962500 >,
721 < 1350000000 975000 >,
722 < 1458000000 1000000 >,
723 < 1512000000 1012500 >;
725 qcom,speed14-pvs5-bin-v0 =
726 < 384000000 875000 >,
727 < 486000000 875000 >,
728 < 594000000 875000 >,
729 < 702000000 875000 >,
730 < 810000000 887500 >,
731 < 918000000 900000 >,
732 < 1026000000 925000 >,
733 < 1134000000 937500 >,
734 < 1242000000 950000 >,
735 < 1350000000 962500 >,
736 < 1458000000 987500 >,
737 < 1512000000 1000000 >;
739 qcom,speed14-pvs6-bin-v0 =
740 < 384000000 875000 >,
741 < 486000000 875000 >,
742 < 594000000 875000 >,
743 < 702000000 875000 >,
744 < 810000000 887500 >,
745 < 918000000 900000 >,
746 < 1026000000 925000 >,
747 < 1134000000 937500 >,
748 < 1242000000 950000 >,
749 < 1350000000 962500 >,
750 < 1458000000 975000 >,
751 < 1512000000 987500 >;
754 kraitcc: clock-controller {
755 compatible = "qcom,krait-cc-v1";
760 sleep_clk: sleep_clk {
761 compatible = "fixed-clock";
762 clock-frequency = <32768>;
769 compatible = "fixed-clock";
771 clock-frequency = <19200000>;
775 compatible = "fixed-clock";
777 clock-frequency = <27000000>;
781 compatible = "fixed-clock";
783 clock-frequency = <32768>;
788 #address-cells = <1>;
791 compatible = "simple-bus";
793 tlmm_pinmux: pinctrl@800000 {
794 compatible = "qcom,apq8064-pinctrl";
795 reg = <0x800000 0x4000>;
799 interrupt-controller;
800 #interrupt-cells = <2>;
801 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&ps_hold>;
806 sdc4_gpios: sdc4-gpios {
808 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
813 hdmi_pinctrl: hdmi-pinctrl {
815 pins = "gpio69", "gpio70", "gpio71";
818 drive-strength = <2>;
824 drive-strength = <16>;
830 function = "ps_hold";
836 pins = "gpio20", "gpio21";
843 pins = "gpio8", "gpio9";
848 gsbi6_uart_2pins: gsbi6_uart_2pins {
850 pins = "gpio14", "gpio15";
855 gsbi6_uart_4pins: gsbi6_uart_4pins {
857 pins = "gpio14", "gpio15", "gpio16", "gpio17";
862 gsbi7_uart_2pins: gsbi7_uart_2pins {
864 pins = "gpio82", "gpio83";
869 gsbi7_uart_4pins: gsbi7_uart_4pins {
871 pins = "gpio82", "gpio83", "gpio84", "gpio85";
877 sfpb_wrapper_mutex: syscon@1200000 {
878 compatible = "syscon";
879 reg = <0x01200000 0x8000>;
882 intc: interrupt-controller@2000000 {
883 compatible = "qcom,msm-qgic2";
884 interrupt-controller;
885 #interrupt-cells = <3>;
886 reg = <0x02000000 0x1000>,
891 compatible = "qcom,kpss-timer", "qcom,msm-timer";
892 interrupts = <1 1 0x301>,
895 reg = <0x0200a000 0x100>;
896 clock-frequency = <27000000>,
898 cpu-offset = <0x80000>;
902 compatible = "qcom,kpss-wdt-apq8064";
903 reg = <0x0208a038 0x40>;
904 clocks = <&sleep_clk>;
908 acc0: clock-controller@2088000 {
909 compatible = "qcom,kpss-acc-v1";
910 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
911 clock-output-names = "acpu0_aux";
914 acc1: clock-controller@2098000 {
915 compatible = "qcom,kpss-acc-v1";
916 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
917 clock-output-names = "acpu1_aux";
920 acc2: clock-controller@20a8000 {
921 compatible = "qcom,kpss-acc-v1";
922 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
923 clock-output-names = "acpu2_aux";
926 acc3: clock-controller@20b8000 {
927 compatible = "qcom,kpss-acc-v1";
928 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
929 clock-output-names = "acpu3_aux";
932 saw0: power-controller@2089000 {
933 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
934 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
936 regulator-name = "krait0";
938 regulator-min-microvolt = <825000>;
939 regulator-max-microvolt = <1250000>;
942 saw1: power-controller@2099000 {
943 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
944 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
946 regulator-name = "krait1";
948 regulator-min-microvolt = <825000>;
949 regulator-max-microvolt = <1250000>;
952 saw2: power-controller@20a9000 {
953 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
954 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
956 regulator-name = "krait2";
958 regulator-min-microvolt = <825000>;
959 regulator-max-microvolt = <1250000>;
962 saw3: power-controller@20b9000 {
963 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
964 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
966 regulator-name = "krait3";
968 regulator-min-microvolt = <825000>;
969 regulator-max-microvolt = <1250000>;
972 gsbi1: gsbi@12440000 {
974 compatible = "qcom,gsbi-v1.0.0";
976 reg = <0x12440000 0x100>;
977 clocks = <&gcc GSBI1_H_CLK>;
978 clock-names = "iface";
979 #address-cells = <1>;
983 syscon-tcsr = <&tcsr>;
986 compatible = "qcom,i2c-qup-v1.1.1";
987 pinctrl-0 = <&i2c1_pins>;
988 pinctrl-names = "default";
989 reg = <0x12460000 0x1000>;
990 interrupts = <0 194 IRQ_TYPE_NONE>;
991 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
992 clock-names = "core", "iface";
993 #address-cells = <1>;
998 gsbi2: gsbi@12480000 {
1000 compatible = "qcom,gsbi-v1.0.0";
1002 reg = <0x12480000 0x100>;
1003 clocks = <&gcc GSBI2_H_CLK>;
1004 clock-names = "iface";
1005 #address-cells = <1>;
1009 syscon-tcsr = <&tcsr>;
1011 i2c2: i2c@124a0000 {
1012 compatible = "qcom,i2c-qup-v1.1.1";
1013 reg = <0x124a0000 0x1000>;
1014 interrupts = <0 196 IRQ_TYPE_NONE>;
1015 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
1016 clock-names = "core", "iface";
1017 #address-cells = <1>;
1022 gsbi3: gsbi@16200000 {
1023 status = "disabled";
1024 compatible = "qcom,gsbi-v1.0.0";
1026 reg = <0x16200000 0x100>;
1027 clocks = <&gcc GSBI3_H_CLK>;
1028 clock-names = "iface";
1029 #address-cells = <1>;
1032 i2c3: i2c@16280000 {
1033 compatible = "qcom,i2c-qup-v1.1.1";
1034 pinctrl-0 = <&i2c3_pins>;
1035 pinctrl-names = "default";
1036 reg = <0x16280000 0x1000>;
1037 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
1038 clocks = <&gcc GSBI3_QUP_CLK>,
1040 clock-names = "core", "iface";
1044 gsbi5: gsbi@1a200000 {
1045 status = "disabled";
1046 compatible = "qcom,gsbi-v1.0.0";
1048 reg = <0x1a200000 0x03>;
1049 clocks = <&gcc GSBI5_H_CLK>;
1050 clock-names = "iface";
1051 #address-cells = <1>;
1055 gsbi5_serial: serial@1a240000 {
1056 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1057 reg = <0x1a240000 0x100>,
1059 interrupts = <0 154 0x0>;
1060 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1061 clock-names = "core", "iface";
1062 status = "disabled";
1066 gsbi6: gsbi@16500000 {
1067 status = "disabled";
1068 compatible = "qcom,gsbi-v1.0.0";
1070 reg = <0x16500000 0x03>;
1071 clocks = <&gcc GSBI6_H_CLK>;
1072 clock-names = "iface";
1073 #address-cells = <1>;
1076 syscon-tcsr = <&tcsr>;
1078 gsbi6_serial: serial@16540000 {
1079 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1080 reg = <0x16540000 0x100>,
1082 interrupts = <0 156 0x0>;
1083 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1084 clock-names = "core", "iface";
1086 qcom,rx-crci = <11>;
1089 dmas = <&adm 6>, <&adm 7>;
1090 dma-names = "rx", "tx";
1092 status = "disabled";
1096 gsbi7: gsbi@16600000 {
1097 status = "disabled";
1098 compatible = "qcom,gsbi-v1.0.0";
1100 reg = <0x16600000 0x100>;
1101 clocks = <&gcc GSBI7_H_CLK>;
1102 clock-names = "iface";
1103 #address-cells = <1>;
1106 syscon-tcsr = <&tcsr>;
1108 gsbi7_serial: serial@16640000 {
1109 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1110 reg = <0x16640000 0x1000>,
1111 <0x16600000 0x1000>;
1112 interrupts = <0 158 0x0>;
1113 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1114 clock-names = "core", "iface";
1115 status = "disabled";
1120 compatible = "qcom,prng";
1121 reg = <0x1a500000 0x200>;
1122 clocks = <&gcc PRNG_CLK>;
1123 clock-names = "core";
1127 compatible = "qcom,ssbi";
1128 reg = <0x00500000 0x1000>;
1129 qcom,controller-type = "pmic-arbiter";
1132 compatible = "qcom,pm8921";
1133 interrupt-parent = <&tlmm_pinmux>;
1134 interrupts = <74 8>;
1135 #interrupt-cells = <2>;
1136 interrupt-controller;
1137 #address-cells = <1>;
1140 pm8921_gpio: gpio@150 {
1142 compatible = "qcom,pm8921-gpio",
1145 interrupts = <192 1>, <193 1>, <194 1>,
1146 <195 1>, <196 1>, <197 1>,
1147 <198 1>, <199 1>, <200 1>,
1148 <201 1>, <202 1>, <203 1>,
1149 <204 1>, <205 1>, <206 1>,
1150 <207 1>, <208 1>, <209 1>,
1151 <210 1>, <211 1>, <212 1>,
1152 <213 1>, <214 1>, <215 1>,
1153 <216 1>, <217 1>, <218 1>,
1154 <219 1>, <220 1>, <221 1>,
1155 <222 1>, <223 1>, <224 1>,
1156 <225 1>, <226 1>, <227 1>,
1157 <228 1>, <229 1>, <230 1>,
1158 <231 1>, <232 1>, <233 1>,
1166 pm8921_mpps: mpps@50 {
1167 compatible = "qcom,pm8921-mpp",
1173 <128 1>, <129 1>, <130 1>, <131 1>,
1174 <132 1>, <133 1>, <134 1>, <135 1>,
1175 <136 1>, <137 1>, <138 1>, <139 1>;
1179 compatible = "qcom,pm8921-rtc";
1180 interrupt-parent = <&pmicintc>;
1181 interrupts = <39 1>;
1187 compatible = "qcom,pm8921-pwrkey";
1189 interrupt-parent = <&pmicintc>;
1190 interrupts = <50 1>, <51 1>;
1197 qfprom: qfprom@00700000 {
1198 compatible = "qcom,qfprom";
1199 reg = <0x00700000 0x1000>;
1200 #address-cells = <1>;
1203 tsens_calib: calib {
1206 tsens_backup: backup_calib {
1211 gcc: clock-controller@900000 {
1212 compatible = "qcom,gcc-apq8064";
1213 reg = <0x00900000 0x4000>;
1214 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1215 nvmem-cell-names = "calib", "calib_backup";
1216 qcom,tsens-slopes = <1176 1176 1154 1176 1111
1217 1132 1132 1199 1132 1199 1132>;
1220 #thermal-sensor-cells = <1>;
1223 lcc: clock-controller@28000000 {
1224 compatible = "qcom,lcc-apq8064";
1225 reg = <0x28000000 0x1000>;
1230 mmcc: clock-controller@4000000 {
1231 compatible = "qcom,mmcc-apq8064";
1232 reg = <0x4000000 0x1000>;
1237 l2cc: clock-controller@2011000 {
1238 compatible = "syscon";
1239 reg = <0x2011000 0x1000>;
1243 compatible = "qcom,rpm-apq8064";
1244 reg = <0x108000 0x1000>;
1245 qcom,ipc = <&l2cc 0x8 2>;
1247 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1248 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1249 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1250 interrupt-names = "ack", "err", "wakeup";
1252 rpmcc: clock-controller {
1253 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1258 compatible = "qcom,rpm-pm8921-regulators";
1294 pm8921_lvs1: lvs1 {};
1295 pm8921_lvs2: lvs2 {};
1296 pm8921_lvs3: lvs3 {};
1297 pm8921_lvs4: lvs4 {};
1298 pm8921_lvs5: lvs5 {};
1299 pm8921_lvs6: lvs6 {};
1300 pm8921_lvs7: lvs7 {};
1302 pm8921_usb_switch: usb-switch {};
1304 pm8921_hdmi_switch: hdmi-switch {
1312 usb1_phy: phy@12500000 {
1313 compatible = "qcom,usb-otg-ci";
1314 reg = <0x12500000 0x400>;
1315 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1316 status = "disabled";
1319 clocks = <&gcc USB_HS1_XCVR_CLK>,
1320 <&gcc USB_HS1_H_CLK>;
1321 clock-names = "core", "iface";
1323 resets = <&gcc USB_HS1_RESET>;
1324 reset-names = "link";
1327 usb3_phy: phy@12520000 {
1328 compatible = "qcom,usb-otg-ci";
1329 reg = <0x12520000 0x400>;
1330 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1331 status = "disabled";
1334 clocks = <&gcc USB_HS3_XCVR_CLK>,
1335 <&gcc USB_HS3_H_CLK>;
1336 clock-names = "core", "iface";
1338 resets = <&gcc USB_HS3_RESET>;
1339 reset-names = "link";
1342 usb4_phy: phy@12530000 {
1343 compatible = "qcom,usb-otg-ci";
1344 reg = <0x12530000 0x400>;
1345 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1346 status = "disabled";
1349 clocks = <&gcc USB_HS4_XCVR_CLK>,
1350 <&gcc USB_HS4_H_CLK>;
1351 clock-names = "core", "iface";
1353 resets = <&gcc USB_HS4_RESET>;
1354 reset-names = "link";
1357 gadget1: gadget@12500000 {
1358 compatible = "qcom,ci-hdrc";
1359 reg = <0x12500000 0x400>;
1360 status = "disabled";
1361 dr_mode = "peripheral";
1362 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1363 usb-phy = <&usb1_phy>;
1366 usb1: usb@12500000 {
1367 compatible = "qcom,ehci-host";
1368 reg = <0x12500000 0x400>;
1369 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1370 status = "disabled";
1371 usb-phy = <&usb1_phy>;
1374 usb3: usb@12520000 {
1375 compatible = "qcom,ehci-host";
1376 reg = <0x12520000 0x400>;
1377 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1378 status = "disabled";
1379 usb-phy = <&usb3_phy>;
1382 usb4: usb@12530000 {
1383 compatible = "qcom,ehci-host";
1384 reg = <0x12530000 0x400>;
1385 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1386 status = "disabled";
1387 usb-phy = <&usb4_phy>;
1390 sata_phy0: phy@1b400000 {
1391 compatible = "qcom,apq8064-sata-phy";
1392 status = "disabled";
1393 reg = <0x1b400000 0x200>;
1394 reg-names = "phy_mem";
1395 clocks = <&gcc SATA_PHY_CFG_CLK>;
1396 clock-names = "cfg";
1400 sata0: sata@29000000 {
1401 compatible = "generic-ahci";
1402 status = "disabled";
1403 reg = <0x29000000 0x180>;
1404 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1406 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1409 <&gcc SATA_RXOOB_CLK>,
1410 <&gcc SATA_PMALIVE_CLK>;
1411 clock-names = "slave_iface",
1417 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1418 <&gcc SATA_PMALIVE_CLK>;
1419 assigned-clock-rates = <100000000>, <100000000>;
1421 phys = <&sata_phy0>;
1422 phy-names = "sata-phy";
1425 /* Temporary fixed regulator */
1426 sdcc1bam:dma@12402000{
1427 compatible = "qcom,bam-v1.3.0";
1428 reg = <0x12402000 0x8000>;
1429 interrupts = <0 98 0>;
1430 clocks = <&gcc SDC1_H_CLK>;
1431 clock-names = "bam_clk";
1436 sdcc3bam:dma@12182000{
1437 compatible = "qcom,bam-v1.3.0";
1438 reg = <0x12182000 0x8000>;
1439 interrupts = <0 96 0>;
1440 clocks = <&gcc SDC3_H_CLK>;
1441 clock-names = "bam_clk";
1446 sdcc4bam:dma@121c2000{
1447 compatible = "qcom,bam-v1.3.0";
1448 reg = <0x121c2000 0x8000>;
1449 interrupts = <0 95 0>;
1450 clocks = <&gcc SDC4_H_CLK>;
1451 clock-names = "bam_clk";
1457 compatible = "arm,amba-bus";
1458 #address-cells = <1>;
1461 sdcc1: sdcc@12400000 {
1462 status = "disabled";
1463 compatible = "arm,pl18x", "arm,primecell";
1464 arm,primecell-periphid = <0x00051180>;
1465 reg = <0x12400000 0x2000>;
1466 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1467 interrupt-names = "cmd_irq";
1468 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1469 clock-names = "mclk", "apb_pclk";
1471 max-frequency = <96000000>;
1475 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1476 dma-names = "tx", "rx";
1479 sdcc3: sdcc@12180000 {
1480 compatible = "arm,pl18x", "arm,primecell";
1481 arm,primecell-periphid = <0x00051180>;
1482 status = "disabled";
1483 reg = <0x12180000 0x2000>;
1484 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1485 interrupt-names = "cmd_irq";
1486 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1487 clock-names = "mclk", "apb_pclk";
1491 max-frequency = <192000000>;
1493 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1494 dma-names = "tx", "rx";
1497 sdcc4: sdcc@121c0000 {
1498 compatible = "arm,pl18x", "arm,primecell";
1499 arm,primecell-periphid = <0x00051180>;
1500 status = "disabled";
1501 reg = <0x121c0000 0x2000>;
1502 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1503 interrupt-names = "cmd_irq";
1504 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1505 clock-names = "mclk", "apb_pclk";
1509 max-frequency = <48000000>;
1510 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1511 dma-names = "tx", "rx";
1512 pinctrl-names = "default";
1513 pinctrl-0 = <&sdc4_gpios>;
1518 compatible = "qcom,adm";
1519 reg = <0x18320000 0xE0000>;
1520 interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1523 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1524 clock-names = "core", "iface";
1526 resets = <&gcc ADM0_RESET>,
1527 <&gcc ADM0_PBUS_RESET>,
1528 <&gcc ADM0_C0_RESET>,
1529 <&gcc ADM0_C1_RESET>,
1530 <&gcc ADM0_C2_RESET>;
1531 reset-names = "clk", "pbus", "c0", "c1", "c2";
1534 status = "disabled";
1537 tcsr: syscon@1a400000 {
1538 compatible = "qcom,tcsr-apq8064", "syscon";
1539 reg = <0x1a400000 0x100>;
1542 pcie: pci@1b500000 {
1543 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1544 reg = <0x1b500000 0x1000
1547 0x0ff00000 0x100000>;
1548 reg-names = "dbi", "elbi", "parf", "config";
1549 device_type = "pci";
1550 linux,pci-domain = <0>;
1551 bus-range = <0x00 0xff>;
1553 #address-cells = <3>;
1555 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1556 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1557 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1558 interrupt-names = "msi";
1559 #interrupt-cells = <1>;
1560 interrupt-map-mask = <0 0 0 0x7>;
1561 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1562 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1563 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1564 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1565 clocks = <&gcc PCIE_A_CLK>,
1567 <&gcc PCIE_PHY_REF_CLK>;
1568 clock-names = "core", "iface", "phy";
1569 resets = <&gcc PCIE_ACLK_RESET>,
1570 <&gcc PCIE_HCLK_RESET>,
1571 <&gcc PCIE_POR_RESET>,
1572 <&gcc PCIE_PCI_RESET>,
1573 <&gcc PCIE_PHY_RESET>;
1574 reset-names = "axi", "ahb", "por", "pci", "phy";
1575 status = "disabled";
1578 pil_q6v4: pil@28800000 {
1579 compatible = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1580 qcom,firmware-name = "q6";
1581 reg = <0x28800000 0x100>;
1582 reg-names = "qdsp6_base";
1583 qcom,pas-id = <1>; /* PAS_Q6 */
1587 compatible = "qcom,smd";
1589 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
1590 qcom,ipc = <&l2cc 8 15>;
1591 qcom,smd-edge = <1>;
1592 qcom,remote-pid = <0x2>;
1594 compatible = "qcom,apr";
1595 qcom,smd-channels = "apr_audio_svc";
1596 rproc = <&pil_q6v4>;
1602 compatible = "qcom,msm-dai-fe";
1603 #sound-dai-cells = <0>;
1606 hdmi_dai: dai_hdmi {
1607 compatible = "qcom,msm-dai-q6-hdmi";
1608 #sound-dai-cells = <0>;
1611 hdmi_codec: codec_hdmi {
1612 compatible = "linux,hdmi-audio";
1613 #sound-dai-cells = <0>;
1617 compatible = "qcom,msm-pcm-dsp";
1618 #sound-dai-cells = <0>;
1621 q6_route: msm_pcm_routing {
1622 compatible = "qcom,msm-pcm-routing";
1623 #sound-dai-cells = <0>;
1627 compatible = "qcom,snd-apq8064";
1631 hdmi: qcom,hdmi-tx@4a00000 {
1632 compatible = "qcom,hdmi-tx-8960";
1633 reg-names = "core_physical";
1634 reg = <0x04a00000 0x1000>;
1635 interrupts = <GIC_SPI 79 0>;
1641 <&mmcc HDMI_APP_CLK>,
1642 <&mmcc HDMI_M_AHB_CLK>,
1643 <&mmcc HDMI_S_AHB_CLK>;
1644 qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1645 qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1646 qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&hdmi_pinctrl>;
1651 gpu: qcom,adreno-3xx@4300000 {
1652 compatible = "qcom,adreno-3xx";
1653 reg = <0x04300000 0x20000>;
1654 reg-names = "kgsl_3d0_reg_memory";
1655 interrupts = <GIC_SPI 80 0>;
1656 interrupt-names = "kgsl_3d0_irq";
1664 <&mmcc GFX3D_AHB_CLK>,
1665 <&mmcc GFX3D_AXI_CLK>,
1666 <&mmcc MMSS_IMEM_AHB_CLK>;
1667 qcom,chipid = <0x03020002>;
1669 iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1670 &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1671 &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1672 &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1674 qcom,gpu-pwrlevels {
1675 compatible = "qcom,gpu-pwrlevels";
1676 qcom,gpu-pwrlevel@0 {
1677 qcom,gpu-freq = <450000000>;
1679 qcom,gpu-pwrlevel@1 {
1680 qcom,gpu-freq = <27000000>;
1685 mdp: qcom,mdp@5100000 {
1686 compatible = "qcom,mdp";
1687 reg = <0x05100000 0xf0000>;
1688 interrupts = <GIC_SPI 75 0>;
1689 connectors = <&hdmi>;
1701 <&mmcc MDP_AHB_CLK>,
1702 <&mmcc MDP_LUT_CLK>,
1704 <&mmcc HDMI_TV_CLK>,
1706 <&mmcc MDP_AXI_CLK>;
1708 iommus = <&mdp_port0 0 2
1712 mdp_port0: qcom,iommu@7500000 {
1713 compatible = "qcom,iommu-v0";
1719 <&mmcc SMMU_AHB_CLK>,
1720 <&mmcc MDP_AXI_CLK>;
1721 reg = <0x07500000 0x100000>;
1728 mdp_port1: qcom,iommu@7600000 {
1729 compatible = "qcom,iommu";
1735 <&mmcc SMMU_AHB_CLK>,
1736 <&mmcc MDP_AXI_CLK>;
1737 reg = <0x07600000 0x100000>;
1744 gfx3d: qcom,iommu@7c00000 {
1745 compatible = "qcom,iommu-v0";
1746 #iommu-cells = <16>;
1751 <&mmcc SMMU_AHB_CLK>,
1752 <&mmcc GFX3D_AXI_CLK>;
1753 reg = <0x07c00000 0x100000>;
1760 gfx3d1: qcom,iommu@7d00000 {
1761 compatible = "qcom,iommu-v0";
1762 #iommu-cells = <16>;
1767 <&mmcc SMMU_AHB_CLK>,
1768 <&mmcc GFX3D_AXI_CLK>;
1769 reg = <0x07d00000 0x100000>;
1778 #include "qcom-apq8064-coresight.dtsi"