arch/arm/boot/dts/qcom-msm8974.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         model = "Qualcomm MSM8974";
   9         compatible = "qcom,msm8974";
  10         interrupt-parent = <&intc>;
  11
  12         reserved-memory {
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges;
  16
  17                 smem_region: smem@fa00000 {
  18                         reg = <0xfa00000 0x200000>;
  19                         no-map;
  20                 };
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 interrupts = <1 9 0xf04>;
  27
  28                 cpu0: cpu@0 {
  29                         compatible = "qcom,krait";
  30                         enable-method = "qcom,kpss-acc-v2";
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         next-level-cache = <&L2>;
  34                         qcom,acc = <&acc0>;
  35                         qcom,saw = <&saw0>;
  36                         cpu-idle-states = <&CPU_SPC>;
  37                         clocks = <&kraitcc 0>;
  38                         clock-names = "cpu";
  39                         clock-latency = <100000>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         compatible = "qcom,krait";
  44                         enable-method = "qcom,kpss-acc-v2";
  45                         device_type = "cpu";
  46                         reg = <1>;
  47                         next-level-cache = <&L2>;
  48                         qcom,acc = <&acc1>;
  49                         qcom,saw = <&saw1>;
  50                         cpu-idle-states = <&CPU_SPC>;
  51                         clocks = <&kraitcc 1>;
  52                         clock-names = "cpu";
  53                         clock-latency = <100000>;
  54                 };
  55
  56                 cpu2: cpu@2 {
  57                         compatible = "qcom,krait";
  58                         enable-method = "qcom,kpss-acc-v2";
  59                         device_type = "cpu";
  60                         reg = <2>;
  61                         next-level-cache = <&L2>;
  62                         qcom,acc = <&acc2>;
  63                         qcom,saw = <&saw2>;
  64                         cpu-idle-states = <&CPU_SPC>;
  65                         clocks = <&kraitcc 2>;
  66                         clock-names = "cpu";
  67                         clock-latency = <100000>;
  68                 };
  69
  70                 cpu3: cpu@3 {
  71                         compatible = "qcom,krait";
  72                         enable-method = "qcom,kpss-acc-v2";
  73                         device_type = "cpu";
  74                         reg = <3>;
  75                         next-level-cache = <&L2>;
  76                         qcom,acc = <&acc3>;
  77                         qcom,saw = <&saw3>;
  78                         cpu-idle-states = <&CPU_SPC>;
  79                         clocks = <&kraitcc 3>;
  80                         clock-names = "cpu";
  81                         clock-latency = <100000>;
  82                 };
  83
  84                 L2: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <2>;
  87                         qcom,saw = <&saw_l2>;
  88                 };
  89
  90                 idle-states {
  91                         CPU_SPC: spc {
  92                                 compatible = "qcom,idle-state-spc",
  93                                                 "arm,idle-state";
  94                                 entry-latency-us = <150>;
  95                                 exit-latency-us = <200>;
  96                                 min-residency-us = <2000>;
  97                         };
  98                 };
  99         };
 100
 101         cpu-pmu {
 102                 compatible = "qcom,krait-pmu";
 103                 interrupts = <1 7 0xf04>;
 104         };
 105
 106         timer {
 107                 compatible = "arm,armv7-timer";
 108                 interrupts = <1 2 0xf08>,
 109                              <1 3 0xf08>,
 110                              <1 4 0xf08>,
 111                              <1 1 0xf08>;
 112                 clock-frequency = <19200000>;
 113         };
 114
 115         smem {
 116                 compatible = "qcom,smem";
 117
 118                 memory-region = <&smem_region>;
 119                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 120
 121                 hwlocks = <&tcsr_mutex 3>;
 122         };
 123
 124         qcom,pvs {
 125                 qcom,pvs-format-b;
 126                         /* Hz           uV      ua */
 127                 qcom,speed0-pvs0-bin-v0 =
 128                         <  300000000  815000  73 >,
 129                         <  345600000  825000  85 >,
 130                         <  422400000  835000 104 >,
 131                         <  499200000  845000 124 >,
 132                         <  576000000  855000 144 >,
 133                         <  652800000  865000 165 >,
 134                         <  729600000  875000 186 >,
 135                         <  806400000  890000 208 >,
 136                         <  883200000  900000 229 >,
 137                         <  960000000  915000 252 >;
 138
 139                 qcom,speed0-pvs1-bin-v0 =
 140                         <  300000000  800000  73 >,
 141                         <  345600000  810000  85 >,
 142                         <  422400000  820000 104 >,
 143                         <  499200000  830000 124 >,
 144                         <  576000000  840000 144 >,
 145                         <  652800000  850000 165 >,
 146                         <  729600000  860000 186 >,
 147                         <  806400000  875000 208 >,
 148                         <  883200000  885000 229 >,
 149                         <  960000000  895000 252 >;
 150
 151                 qcom,speed0-pvs2-bin-v0 =
 152                         <  300000000  785000  73 >,
 153                         <  345600000  795000  85 >,
 154                         <  422400000  805000 104 >,
 155                         <  499200000  815000 124 >,
 156                         <  576000000  825000 144 >,
 157                         <  652800000  835000 165 >,
 158                         <  729600000  845000 186 >,
 159                         <  806400000  855000 208 >,
 160                         <  883200000  865000 229 >,
 161                         <  960000000  875000 252 >;
 162
 163                 qcom,speed0-pvs3-bin-v0 =
 164                         <  300000000  775000  73 >,
 165                         <  345600000  780000  85 >,
 166                         <  422400000  790000 104 >,
 167                         <  499200000  800000 124 >,
 168                         <  576000000  810000 144 >,
 169                         <  652800000  820000 165 >,
 170                         <  729600000  830000 186 >,
 171                         <  806400000  840000 208 >,
 172                         <  883200000  850000 229 >,
 173                         <  960000000  860000 252 >;
 174
 175                 qcom,speed0-pvs4-bin-v0 =
 176                         <  300000000  775000  73 >,
 177                         <  345600000  775000  85 >,
 178                         <  422400000  780000 104 >,
 179                         <  499200000  790000 124 >,
 180                         <  576000000  800000 144 >,
 181                         <  652800000  810000 165 >,
 182                         <  729600000  820000 186 >,
 183                         <  806400000  830000 208 >,
 184                         <  883200000  840000 229 >,
 185                         <  960000000  850000 252 >;
 186
 187                 qcom,speed0-pvs5-bin-v0 =
 188                         <  300000000  750000  73 >,
 189                         <  345600000  760000  85 >,
 190                         <  422400000  770000 104 >,
 191                         <  499200000  780000 124 >,
 192                         <  576000000  790000 144 >,
 193                         <  652800000  800000 165 >,
 194                         <  729600000  810000 186 >,
 195                         <  806400000  820000 208 >,
 196                         <  883200000  830000 229 >,
 197                         <  960000000  840000 252 >;
 198
 199                 qcom,speed0-pvs6-bin-v0 =
 200                         <  300000000  750000  73 >,
 201                         <  345600000  750000  85 >,
 202                         <  422400000  760000 104 >,
 203                         <  499200000  770000 124 >,
 204                         <  576000000  780000 144 >,
 205                         <  652800000  790000 165 >,
 206                         <  729600000  800000 186 >,
 207                         <  806400000  810000 208 >,
 208                         <  883200000  820000 229 >,
 209                         <  960000000  830000 252 >;
 210
 211                 qcom,speed2-pvs0-bin-v0 =
 212                         <  300000000  800000  72 >,
 213                         <  345600000  800000  83 >,
 214                         <  422400000  805000 102 >,
 215                         <  499200000  815000 121 >,
 216                         <  576000000  825000 141 >,
 217                         <  652800000  835000 161 >,
 218                         <  729600000  845000 181 >,
 219                         <  806400000  855000 202 >,
 220                         <  883200000  865000 223 >,
 221                         <  960000000  875000 245 >;
 222
 223                 qcom,speed2-pvs1-bin-v0 =
 224                         <  300000000  800000  72 >,
 225                         <  345600000  800000  83 >,
 226                         <  422400000  800000 102 >,
 227                         <  499200000  800000 121 >,
 228                         <  576000000  810000 141 >,
 229                         <  652800000  820000 161 >,
 230                         <  729600000  830000 181 >,
 231                         <  806400000  840000 202 >,
 232                         <  883200000  850000 223 >,
 233                         <  960000000  860000 245 >;
 234
 235                 qcom,speed2-pvs2-bin-v0 =
 236                         <  300000000  775000  72 >,
 237                         <  345600000  775000  83 >,
 238                         <  422400000  775000 102 >,
 239                         <  499200000  785000 121 >,
 240                         <  576000000  795000 141 >,
 241                         <  652800000  805000 161 >,
 242                         <  729600000  815000 181 >,
 243                         <  806400000  825000 202 >,
 244                         <  883200000  835000 223 >,
 245                         <  960000000  845000 245 >;
 246
 247                 qcom,speed2-pvs3-bin-v0 =
 248                         <  300000000  775000  72 >,
 249                         <  345600000  775000  83 >,
 250                         <  422400000  775000 102 >,
 251                         <  499200000  775000 121 >,
 252                         <  576000000  780000 141 >,
 253                         <  652800000  790000 161 >,
 254                         <  729600000  800000 181 >,
 255                         <  806400000  810000 202 >,
 256                         <  883200000  820000 223 >,
 257                         <  960000000  830000 245 >;
 258
 259                 qcom,speed2-pvs4-bin-v0 =
 260                         <  300000000  775000  72 >,
 261                         <  345600000  775000  83 >,
 262                         <  422400000  775000 102 >,
 263                         <  499200000  775000 121 >,
 264                         <  576000000  775000 141 >,
 265                         <  652800000  780000 161 >,
 266                         <  729600000  790000 181 >,
 267                         <  806400000  800000 202 >,
 268                         <  883200000  810000 223 >,
 269                         <  960000000  820000 245 >;
 270
 271                 qcom,speed2-pvs5-bin-v0 =
 272                         <  300000000  750000  72 >,
 273                         <  345600000  750000  83 >,
 274                         <  422400000  750000 102 >,
 275                         <  499200000  750000 121 >,
 276                         <  576000000  760000 141 >,
 277                         <  652800000  770000 161 >,
 278                         <  729600000  780000 181 >,
 279                         <  806400000  790000 202 >,
 280                         <  883200000  800000 223 >,
 281                         <  960000000  810000 245 >;
 282
 283                 qcom,speed2-pvs6-bin-v0 =
 284                         <  300000000  750000  72 >,
 285                         <  345600000  750000  83 >,
 286                         <  422400000  750000 102 >,
 287                         <  499200000  750000 121 >,
 288                         <  576000000  750000 141 >,
 289                         <  652800000  760000 161 >,
 290                         <  729600000  770000 181 >,
 291                         <  806400000  780000 202 >,
 292                         <  883200000  790000 223 >,
 293                         <  960000000  800000 245 >;
 294
 295                 qcom,speed1-pvs0-bin-v0 =
 296                         <  300000000  775000  72 >,
 297                         <  345600000  775000  83 >,
 298                         <  422400000  775000 101 >,
 299                         <  499200000  780000 120 >,
 300                         <  576000000  790000 139 >,
 301                         <  652800000  800000 159 >,
 302                         <  729600000  810000 180 >,
 303                         <  806400000  820000 200 >,
 304                         <  883200000  830000 221 >,
 305                         <  960000000  840000 242 >;
 306
 307                 qcom,speed1-pvs1-bin-v0 =
 308                         <  300000000  775000  72 >,
 309                         <  345600000  775000  83 >,
 310                         <  422400000  775000 101 >,
 311                         <  499200000  775000 120 >,
 312                         <  576000000  775000 139 >,
 313                         <  652800000  785000 159 >,
 314                         <  729600000  795000 180 >,
 315                         <  806400000  805000 200 >,
 316                         <  883200000  815000 221 >,
 317                         <  960000000  825000 242 >;
 318
 319                 qcom,speed1-pvs2-bin-v0 =
 320                         <  300000000  750000  72 >,
 321                         <  345600000  750000  83 >,
 322                         <  422400000  750000 101 >,
 323                         <  499200000  750000 120 >,
 324                         <  576000000  760000 139 >,
 325                         <  652800000  770000 159 >,
 326                         <  729600000  780000 180 >,
 327                         <  806400000  790000 200 >,
 328                         <  883200000  800000 221 >,
 329                         <  960000000  810000 242 >;
 330
 331                 qcom,speed1-pvs3-bin-v0 =
 332                         <  300000000  750000  72 >,
 333                         <  345600000  750000  83 >,
 334                         <  422400000  750000 101 >,
 335                         <  499200000  750000 120 >,
 336                         <  576000000  750000 139 >,
 337                         <  652800000  755000 159 >,
 338                         <  729600000  765000 180 >,
 339                         <  806400000  775000 200 >,
 340                         <  883200000  785000 221 >,
 341                         <  960000000  795000 242 >;
 342
 343                 qcom,speed1-pvs4-bin-v0 =
 344                         <  300000000  750000  72 >,
 345                         <  345600000  750000  83 >,
 346                         <  422400000  750000 101 >,
 347                         <  499200000  750000 120 >,
 348                         <  576000000  750000 139 >,
 349                         <  652800000  750000 159 >,
 350                         <  729600000  755000 180 >,
 351                         <  806400000  765000 200 >,
 352                         <  883200000  775000 221 >,
 353                         <  960000000  785000 242 >;
 354
 355                 qcom,speed1-pvs5-bin-v0 =
 356                         <  300000000  725000  72 >,
 357                         <  345600000  725000  83 >,
 358                         <  422400000  725000 101 >,
 359                         <  499200000  725000 120 >,
 360                         <  576000000  725000 139 >,
 361                         <  652800000  735000 159 >,
 362                         <  729600000  745000 180 >,
 363                         <  806400000  755000 200 >,
 364                         <  883200000  765000 221 >,
 365                         <  960000000  775000 242 >;
 366
 367                 qcom,speed1-pvs6-bin-v0 =
 368                         <  300000000  725000  72 >,
 369                         <  345600000  725000  83 >,
 370                         <  422400000  725000 101 >,
 371                         <  499200000  725000 120 >,
 372                         <  576000000  725000 139 >,
 373                         <  652800000  725000 159 >,
 374                         <  729600000  735000 180 >,
 375                         <  806400000  745000 200 >,
 376                         <  883200000  755000 221 >,
 377                         <  960000000  765000 242 >;
 378         };
 379
 380         kraitcc: clock-controller {
 381                 compatible = "qcom,krait-cc-v2";
 382                 #clock-cells = <1>;
 383         };
 384
 385         soc: soc {
 386                 #address-cells = <1>;
 387                 #size-cells = <1>;
 388                 ranges;
 389                 compatible = "simple-bus";
 390
 391                 intc: interrupt-controller@f9000000 {
 392                         compatible = "qcom,msm-qgic2";
 393                         interrupt-controller;
 394                         #interrupt-cells = <3>;
 395                         reg = <0xf9000000 0x1000>,
 396                               <0xf9002000 0x1000>;
 397                 };
 398
 399                 apcs: syscon@f9011000 {
 400                         compatible = "syscon";
 401                         reg = <0xf9011000 0x1000>;
 402                 };
 403
 404                 timer@f9020000 {
 405                         #address-cells = <1>;
 406                         #size-cells = <1>;
 407                         ranges;
 408                         compatible = "arm,armv7-timer-mem";
 409                         reg = <0xf9020000 0x1000>;
 410                         clock-frequency = <19200000>;
 411
 412                         frame@f9021000 {
 413                                 frame-number = <0>;
 414                                 interrupts = <0 8 0x4>,
 415                                              <0 7 0x4>;
 416                                 reg = <0xf9021000 0x1000>,
 417                                       <0xf9022000 0x1000>;
 418                         };
 419
 420                         frame@f9023000 {
 421                                 frame-number = <1>;
 422                                 interrupts = <0 9 0x4>;
 423                                 reg = <0xf9023000 0x1000>;
 424                                 status = "disabled";
 425                         };
 426
 427                         frame@f9024000 {
 428                                 frame-number = <2>;
 429                                 interrupts = <0 10 0x4>;
 430                                 reg = <0xf9024000 0x1000>;
 431                                 status = "disabled";
 432                         };
 433
 434                         frame@f9025000 {
 435                                 frame-number = <3>;
 436                                 interrupts = <0 11 0x4>;
 437                                 reg = <0xf9025000 0x1000>;
 438                                 status = "disabled";
 439                         };
 440
 441                         frame@f9026000 {
 442                                 frame-number = <4>;
 443                                 interrupts = <0 12 0x4>;
 444                                 reg = <0xf9026000 0x1000>;
 445                                 status = "disabled";
 446                         };
 447
 448                         frame@f9027000 {
 449                                 frame-number = <5>;
 450                                 interrupts = <0 13 0x4>;
 451                                 reg = <0xf9027000 0x1000>;
 452                                 status = "disabled";
 453                         };
 454
 455                         frame@f9028000 {
 456                                 frame-number = <6>;
 457                                 interrupts = <0 14 0x4>;
 458                                 reg = <0xf9028000 0x1000>;
 459                                 status = "disabled";
 460                         };
 461                 };
 462
 463                 saw0: power-controller@f9089000 {
 464                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 465                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 466                 };
 467
 468                 saw1: power-controller@f9099000 {
 469                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 470                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 471                 };
 472
 473                 saw2: power-controller@f90a9000 {
 474                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 475                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 476                 };
 477
 478                 saw3: power-controller@f90b9000 {
 479                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 480                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 481                 };
 482
 483                 clock-controller@f9016000 {
 484                         compatible = "qcom,hfpll";
 485                         reg = <0xf9016000 0x30>;
 486                         clock-output-names = "hfpll_l2";
 487                 };
 488
 489                 clock-controller@f908a000 {
 490                         compatible = "qcom,hfpll";
 491                         reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
 492                         clock-output-names = "hfpll0";
 493                 };
 494
 495                 clock-controller@f909a000 {
 496                         compatible = "qcom,hfpll";
 497                         reg = <0xf909a000 0x30>, <0xf900a000 0x30>;
 498                         clock-output-names = "hfpll1";
 499                 };
 500
 501                 clock-controller@f90aa000 {
 502                         compatible = "qcom,hfpll";
 503                         reg = <0xf90aa000 0x30>, <0xf900a000 0x30>;
 504                         clock-output-names = "hfpll2";
 505                 };
 506
 507                 clock-controller@f90ba000 {
 508                         compatible = "qcom,hfpll";
 509                         reg = <0xf90ba000 0x30>, <0xf900a000 0x30>;
 510                         clock-output-names = "hfpll3";
 511                 };
 512
 513                 saw_l2: regulator@f9012000 {
 514                         compatible = "qcom,saw2";
 515                         reg = <0xf9012000 0x1000>;
 516                         regulator;
 517                 };
 518
 519                 acc0: clock-controller@f9088000 {
 520                         compatible = "qcom,kpss-acc-v2";
 521                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 522                 };
 523
 524                 acc1: clock-controller@f9098000 {
 525                         compatible = "qcom,kpss-acc-v2";
 526                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 527                 };
 528
 529                 acc2: clock-controller@f90a8000 {
 530                         compatible = "qcom,kpss-acc-v2";
 531                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 532                 };
 533
 534                 acc3: clock-controller@f90b8000 {
 535                         compatible = "qcom,kpss-acc-v2";
 536                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 537                 };
 538
 539                 restart@fc4ab000 {
 540                         compatible = "qcom,pshold";
 541                         reg = <0xfc4ab000 0x4>;
 542                 };
 543
 544                 gcc: clock-controller@fc400000 {
 545                         compatible = "qcom,gcc-msm8974";
 546                         #clock-cells = <1>;
 547                         #reset-cells = <1>;
 548                         #power-domain-cells = <1>;
 549                         reg = <0xfc400000 0x4000>;
 550                 };
 551
 552                 tcsr_mutex_block: syscon@fd484000 {
 553                         compatible = "syscon";
 554                         reg = <0xfd484000 0x2000>;
 555                 };
 556
 557                 mmcc: clock-controller@fd8c0000 {
 558                         compatible = "qcom,mmcc-msm8974";
 559                         #clock-cells = <1>;
 560                         #reset-cells = <1>;
 561                         #power-domain-cells = <1>;
 562                         reg = <0xfd8c0000 0x6000>;
 563                 };
 564
 565                 tcsr_mutex: tcsr-mutex {
 566                         compatible = "qcom,tcsr-mutex";
 567                         syscon = <&tcsr_mutex_block 0 0x80>;
 568
 569                         #hwlock-cells = <1>;
 570                 };
 571
 572                 rpm_msg_ram: memory@fc428000 {
 573                         compatible = "qcom,rpm-msg-ram";
 574                         reg = <0xfc428000 0x4000>;
 575                 };
 576
 577                 blsp1_uart2: serial@f991e000 {
 578                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 579                         reg = <0xf991e000 0x1000>;
 580                         interrupts = <0 108 0x0>;
 581                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 582                         clock-names = "core", "iface";
 583                         status = "disabled";
 584                 };
 585
 586                 sdhci@f9824900 {
 587                         compatible = "qcom,sdhci-msm-v4";
 588                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 589                         reg-names = "hc_mem", "core_mem";
 590                         interrupts = <0 123 0>, <0 138 0>;
 591                         interrupt-names = "hc_irq", "pwr_irq";
 592                         clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
 593                         clock-names = "core", "iface";
 594                         status = "disabled";
 595                 };
 596
 597                 sdhci@f98a4900 {
 598                         compatible = "qcom,sdhci-msm-v4";
 599                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 600                         reg-names = "hc_mem", "core_mem";
 601                         interrupts = <0 125 0>, <0 221 0>;
 602                         interrupt-names = "hc_irq", "pwr_irq";
 603                         clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
 604                         clock-names = "core", "iface";
 605                         status = "disabled";
 606                 };
 607
 608                 rng@f9bff000 {
 609                         compatible = "qcom,prng";
 610                         reg = <0xf9bff000 0x200>;
 611                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 612                         clock-names = "core";
 613                 };
 614
 615                 msmgpio: pinctrl@fd510000 {
 616                         compatible = "qcom,msm8974-pinctrl";
 617                         reg = <0xfd510000 0x4000>;
 618                         gpio-controller;
 619                         #gpio-cells = <2>;
 620                         interrupt-controller;
 621                         #interrupt-cells = <2>;
 622                         interrupts = <0 208 0>;
 623                 };
 624
 625                 blsp_i2c11: i2c@f9967000 {
 626                         status = "disabled";
 627                         compatible = "qcom,i2c-qup-v2.1.1";
 628                         reg = <0xf9967000 0x1000>;
 629                         interrupts = <0 105 IRQ_TYPE_NONE>;
 630                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 631                         clock-names = "core", "iface";
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                 };
 635
 636                 spmi_bus: spmi@fc4cf000 {
 637                         compatible = "qcom,spmi-pmic-arb";
 638                         reg-names = "core", "intr", "cnfg";
 639                         reg = <0xfc4cf000 0x1000>,
 640                               <0xfc4cb000 0x1000>,
 641                               <0xfc4ca000 0x1000>;
 642                         interrupt-names = "periph_irq";
 643                         interrupts = <0 190 0>;
 644                         qcom,ee = <0>;
 645                         qcom,channel = <0>;
 646                         #address-cells = <2>;
 647                         #size-cells = <0>;
 648                         interrupt-controller;
 649                         #interrupt-cells = <4>;
 650                 };
 651         };
 652
 653         smd {
 654                 compatible = "qcom,smd";
 655
 656                 rpm {
 657                         interrupts = <0 168 1>;
 658                         qcom,ipc = <&apcs 8 0>;
 659                         qcom,smd-edge = <15>;
 660
 661                         rpm_requests {
 662                                 compatible = "qcom,rpm-msm8974";
 663                                 qcom,smd-channels = "rpm_requests";
 664
 665                                 pm8841-regulators {
 666                                         compatible = "qcom,rpm-pm8841-regulators";
 667
 668                                         pm8841_s1: s1 {};
 669                                         pm8841_s2: s2 {};
 670                                         pm8841_s3: s3 {};
 671                                         pm8841_s4: s4 {};
 672                                         pm8841_s5: s5 {};
 673                                         pm8841_s6: s6 {};
 674                                         pm8841_s7: s7 {};
 675                                         pm8841_s8: s8 {};
 676                                 };
 677
 678                                 pm8941-regulators {
 679                                         compatible = "qcom,rpm-pm8941-regulators";
 680
 681                                         pm8941_s1: s1 {};
 682                                         pm8941_s2: s2 {};
 683                                         pm8941_s3: s3 {};
 684                                         pm8941_5v: s4 {};
 685
 686                                         pm8941_l1: l1 {};
 687                                         pm8941_l2: l2 {};
 688                                         pm8941_l3: l3 {};
 689                                         pm8941_l4: l4 {};
 690                                         pm8941_l5: l5 {};
 691                                         pm8941_l6: l6 {};
 692                                         pm8941_l7: l7 {};
 693                                         pm8941_l8: l8 {};
 694                                         pm8941_l9: l9 {};
 695                                         pm8941_l10: l10 {};
 696                                         pm8941_l11: l11 {};
 697                                         pm8941_l12: l12 {};
 698                                         pm8941_l13: l13 {};
 699                                         pm8941_l14: l14 {};
 700                                         pm8941_l15: l15 {};
 701                                         pm8941_l16: l16 {};
 702                                         pm8941_l17: l17 {};
 703                                         pm8941_l18: l18 {};
 704                                         pm8941_l19: l19 {};
 705                                         pm8941_l20: l20 {};
 706                                         pm8941_l21: l21 {};
 707                                         pm8941_l22: l22 {};
 708                                         pm8941_l23: l23 {};
 709                                         pm8941_l24: l24 {};
 710
 711                                         pm8941_lvs1: lvs1 {};
 712                                         pm8941_lvs2: lvs2 {};
 713                                         pm8941_lvs3: lvs3 {};
 714
 715                                         pm8941_5vs1: 5vs1 {};
 716                                         pm8941_5vs2: 5vs2 {};
 717                                 };
 718                         };
 719                 };
 720         };
 721 };