arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7790-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7790";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &iic0;
  29                 i2c5 = &iic1;
  30                 i2c6 = &iic2;
  31                 i2c7 = &iic3;
  32                 spi0 = &qspi;
  33                 spi1 = &msiof0;
  34                 spi2 = &msiof1;
  35                 spi3 = &msiof2;
  36                 spi4 = &msiof3;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40                 vin3 = &vin3;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                         clock-frequency = <1300000000>;
  52                         voltage-tolerance = <1>; /* 1% */
  53                         clocks = <&cpg_clocks R8A7790_CLK_Z>;
  54                         clock-latency = <300000>; /* 300 us */
  55
  56                         /* kHz - uV - OPPs unknown yet */
  57                         operating-points = <1400000 1000000>,
  58                                            <1225000 1000000>,
  59                                            <1050000 1000000>,
  60                                            < 875000 1000000>,
  61                                            < 700000 1000000>,
  62                                            < 350000 1000000>;
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <1>;
  69                         clock-frequency = <1300000000>;
  70                 };
  71
  72                 cpu2: cpu@2 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a15";
  75                         reg = <2>;
  76                         clock-frequency = <1300000000>;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a15";
  82                         reg = <3>;
  83                         clock-frequency = <1300000000>;
  84                 };
  85
  86                 cpu4: cpu@4 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a7";
  89                         reg = <0x100>;
  90                         clock-frequency = <780000000>;
  91                 };
  92
  93                 cpu5: cpu@5 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x101>;
  97                         clock-frequency = <780000000>;
  98                 };
  99
 100                 cpu6: cpu@6 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a7";
 103                         reg = <0x102>;
 104                         clock-frequency = <780000000>;
 105                 };
 106
 107                 cpu7: cpu@7 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a7";
 110                         reg = <0x103>;
 111                         clock-frequency = <780000000>;
 112                 };
 113         };
 114
 115         gic: interrupt-controller@f1001000 {
 116                 compatible = "arm,cortex-a15-gic";
 117                 #interrupt-cells = <3>;
 118                 #address-cells = <0>;
 119                 interrupt-controller;
 120                 reg = <0 0xf1001000 0 0x1000>,
 121                         <0 0xf1002000 0 0x1000>,
 122                         <0 0xf1004000 0 0x2000>,
 123                         <0 0xf1006000 0 0x2000>;
 124                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 125         };
 126
 127         gpio0: gpio@e6050000 {
 128                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 129                 reg = <0 0xe6050000 0 0x50>;
 130                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 131                 #gpio-cells = <2>;
 132                 gpio-controller;
 133                 gpio-ranges = <&pfc 0 0 32>;
 134                 #interrupt-cells = <2>;
 135                 interrupt-controller;
 136                 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
 137         };
 138
 139         gpio1: gpio@e6051000 {
 140                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 141                 reg = <0 0xe6051000 0 0x50>;
 142                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 143                 #gpio-cells = <2>;
 144                 gpio-controller;
 145                 gpio-ranges = <&pfc 0 32 32>;
 146                 #interrupt-cells = <2>;
 147                 interrupt-controller;
 148                 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
 149         };
 150
 151         gpio2: gpio@e6052000 {
 152                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 153                 reg = <0 0xe6052000 0 0x50>;
 154                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 64 32>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
 161         };
 162
 163         gpio3: gpio@e6053000 {
 164                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 165                 reg = <0 0xe6053000 0 0x50>;
 166                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 167                 #gpio-cells = <2>;
 168                 gpio-controller;
 169                 gpio-ranges = <&pfc 0 96 32>;
 170                 #interrupt-cells = <2>;
 171                 interrupt-controller;
 172                 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
 173         };
 174
 175         gpio4: gpio@e6054000 {
 176                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 177                 reg = <0 0xe6054000 0 0x50>;
 178                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 179                 #gpio-cells = <2>;
 180                 gpio-controller;
 181                 gpio-ranges = <&pfc 0 128 32>;
 182                 #interrupt-cells = <2>;
 183                 interrupt-controller;
 184                 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
 185         };
 186
 187         gpio5: gpio@e6055000 {
 188                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 189                 reg = <0 0xe6055000 0 0x50>;
 190                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 191                 #gpio-cells = <2>;
 192                 gpio-controller;
 193                 gpio-ranges = <&pfc 0 160 32>;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196                 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
 197         };
 198
 199         thermal@e61f0000 {
 200                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 201                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 202                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv7-timer";
 208                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 209                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 210                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 211                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 212         };
 213
 214         cmt0: timer@ffca0000 {
 215                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 216                 reg = <0 0xffca0000 0 0x1004>;
 217                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0x60>;
 223
 224                 status = "disabled";
 225         };
 226
 227         cmt1: timer@e6130000 {
 228                 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 229                 reg = <0 0xe6130000 0 0x1004>;
 230                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 231                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 232                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 239                 clock-names = "fck";
 240
 241                 renesas,channels-mask = <0xff>;
 242
 243                 status = "disabled";
 244         };
 245
 246         irqc0: interrupt-controller@e61c0000 {
 247                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 248                 #interrupt-cells = <2>;
 249                 interrupt-controller;
 250                 reg = <0 0xe61c0000 0 0x200>;
 251                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 252                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 253                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 254                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 255         };
 256
 257         dmac0: dma-controller@e6700000 {
 258                 compatible = "renesas,rcar-dmac";
 259                 reg = <0 0xe6700000 0 0x20000>;
 260                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 261                               0 200 IRQ_TYPE_LEVEL_HIGH
 262                               0 201 IRQ_TYPE_LEVEL_HIGH
 263                               0 202 IRQ_TYPE_LEVEL_HIGH
 264                               0 203 IRQ_TYPE_LEVEL_HIGH
 265                               0 204 IRQ_TYPE_LEVEL_HIGH
 266                               0 205 IRQ_TYPE_LEVEL_HIGH
 267                               0 206 IRQ_TYPE_LEVEL_HIGH
 268                               0 207 IRQ_TYPE_LEVEL_HIGH
 269                               0 208 IRQ_TYPE_LEVEL_HIGH
 270                               0 209 IRQ_TYPE_LEVEL_HIGH
 271                               0 210 IRQ_TYPE_LEVEL_HIGH
 272                               0 211 IRQ_TYPE_LEVEL_HIGH
 273                               0 212 IRQ_TYPE_LEVEL_HIGH
 274                               0 213 IRQ_TYPE_LEVEL_HIGH
 275                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 276                 interrupt-names = "error",
 277                                 "ch0", "ch1", "ch2", "ch3",
 278                                 "ch4", "ch5", "ch6", "ch7",
 279                                 "ch8", "ch9", "ch10", "ch11",
 280                                 "ch12", "ch13", "ch14";
 281                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 282                 clock-names = "fck";
 283                 #dma-cells = <1>;
 284                 dma-channels = <15>;
 285         };
 286
 287         dmac1: dma-controller@e6720000 {
 288                 compatible = "renesas,rcar-dmac";
 289                 reg = <0 0xe6720000 0 0x20000>;
 290                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 291                               0 216 IRQ_TYPE_LEVEL_HIGH
 292                               0 217 IRQ_TYPE_LEVEL_HIGH
 293                               0 218 IRQ_TYPE_LEVEL_HIGH
 294                               0 219 IRQ_TYPE_LEVEL_HIGH
 295                               0 308 IRQ_TYPE_LEVEL_HIGH
 296                               0 309 IRQ_TYPE_LEVEL_HIGH
 297                               0 310 IRQ_TYPE_LEVEL_HIGH
 298                               0 311 IRQ_TYPE_LEVEL_HIGH
 299                               0 312 IRQ_TYPE_LEVEL_HIGH
 300                               0 313 IRQ_TYPE_LEVEL_HIGH
 301                               0 314 IRQ_TYPE_LEVEL_HIGH
 302                               0 315 IRQ_TYPE_LEVEL_HIGH
 303                               0 316 IRQ_TYPE_LEVEL_HIGH
 304                               0 317 IRQ_TYPE_LEVEL_HIGH
 305                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 306                 interrupt-names = "error",
 307                                 "ch0", "ch1", "ch2", "ch3",
 308                                 "ch4", "ch5", "ch6", "ch7",
 309                                 "ch8", "ch9", "ch10", "ch11",
 310                                 "ch12", "ch13", "ch14";
 311                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 312                 clock-names = "fck";
 313                 #dma-cells = <1>;
 314                 dma-channels = <15>;
 315         };
 316
 317         audma0: dma-controller@ec700000 {
 318                 compatible = "renesas,rcar-dmac";
 319                 reg = <0 0xec700000 0 0x10000>;
 320                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 321                                  0 320 IRQ_TYPE_LEVEL_HIGH
 322                                  0 321 IRQ_TYPE_LEVEL_HIGH
 323                                  0 322 IRQ_TYPE_LEVEL_HIGH
 324                                  0 323 IRQ_TYPE_LEVEL_HIGH
 325                                  0 324 IRQ_TYPE_LEVEL_HIGH
 326                                  0 325 IRQ_TYPE_LEVEL_HIGH
 327                                  0 326 IRQ_TYPE_LEVEL_HIGH
 328                                  0 327 IRQ_TYPE_LEVEL_HIGH
 329                                  0 328 IRQ_TYPE_LEVEL_HIGH
 330                                  0 329 IRQ_TYPE_LEVEL_HIGH
 331                                  0 330 IRQ_TYPE_LEVEL_HIGH
 332                                  0 331 IRQ_TYPE_LEVEL_HIGH
 333                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 334                 interrupt-names = "error",
 335                                 "ch0", "ch1", "ch2", "ch3",
 336                                 "ch4", "ch5", "ch6", "ch7",
 337                                 "ch8", "ch9", "ch10", "ch11",
 338                                 "ch12";
 339                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 340                 clock-names = "fck";
 341                 #dma-cells = <1>;
 342                 dma-channels = <13>;
 343         };
 344
 345         audma1: dma-controller@ec720000 {
 346                 compatible = "renesas,rcar-dmac";
 347                 reg = <0 0xec720000 0 0x10000>;
 348                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 349                                  0 333 IRQ_TYPE_LEVEL_HIGH
 350                                  0 334 IRQ_TYPE_LEVEL_HIGH
 351                                  0 335 IRQ_TYPE_LEVEL_HIGH
 352                                  0 336 IRQ_TYPE_LEVEL_HIGH
 353                                  0 337 IRQ_TYPE_LEVEL_HIGH
 354                                  0 338 IRQ_TYPE_LEVEL_HIGH
 355                                  0 339 IRQ_TYPE_LEVEL_HIGH
 356                                  0 340 IRQ_TYPE_LEVEL_HIGH
 357                                  0 341 IRQ_TYPE_LEVEL_HIGH
 358                                  0 342 IRQ_TYPE_LEVEL_HIGH
 359                                  0 343 IRQ_TYPE_LEVEL_HIGH
 360                                  0 344 IRQ_TYPE_LEVEL_HIGH
 361                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 362                 interrupt-names = "error",
 363                                 "ch0", "ch1", "ch2", "ch3",
 364                                 "ch4", "ch5", "ch6", "ch7",
 365                                 "ch8", "ch9", "ch10", "ch11",
 366                                 "ch12";
 367                 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 368                 clock-names = "fck";
 369                 #dma-cells = <1>;
 370                 dma-channels = <13>;
 371         };
 372
 373         i2c0: i2c@e6508000 {
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 compatible = "renesas,i2c-r8a7790";
 377                 reg = <0 0xe6508000 0 0x40>;
 378                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 380                 status = "disabled";
 381         };
 382
 383         i2c1: i2c@e6518000 {
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 compatible = "renesas,i2c-r8a7790";
 387                 reg = <0 0xe6518000 0 0x40>;
 388                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 390                 status = "disabled";
 391         };
 392
 393         i2c2: i2c@e6530000 {
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 compatible = "renesas,i2c-r8a7790";
 397                 reg = <0 0xe6530000 0 0x40>;
 398                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 400                 status = "disabled";
 401         };
 402
 403         i2c3: i2c@e6540000 {
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 compatible = "renesas,i2c-r8a7790";
 407                 reg = <0 0xe6540000 0 0x40>;
 408                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 410                 status = "disabled";
 411         };
 412
 413         iic0: i2c@e6500000 {
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 417                 reg = <0 0xe6500000 0 0x425>;
 418                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 420                 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 421                 dma-names = "tx", "rx";
 422                 status = "disabled";
 423         };
 424
 425         iic1: i2c@e6510000 {
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 429                 reg = <0 0xe6510000 0 0x425>;
 430                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 431                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 432                 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 433                 dma-names = "tx", "rx";
 434                 status = "disabled";
 435         };
 436
 437         iic2: i2c@e6520000 {
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 441                 reg = <0 0xe6520000 0 0x425>;
 442                 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 444                 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
 445                 dma-names = "tx", "rx";
 446                 status = "disabled";
 447         };
 448
 449         iic3: i2c@e60b0000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 453                 reg = <0 0xe60b0000 0 0x425>;
 454                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 456                 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 457                 dma-names = "tx", "rx";
 458                 status = "disabled";
 459         };
 460
 461         mmcif0: mmc@ee200000 {
 462                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 463                 reg = <0 0xee200000 0 0x80>;
 464                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 466                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 467                 dma-names = "tx", "rx";
 468                 reg-io-width = <4>;
 469                 status = "disabled";
 470         };
 471
 472         mmcif1: mmc@ee220000 {
 473                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 474                 reg = <0 0xee220000 0 0x80>;
 475                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 477                 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
 478                 dma-names = "tx", "rx";
 479                 reg-io-width = <4>;
 480                 status = "disabled";
 481         };
 482
 483         pfc: pfc@e6060000 {
 484                 compatible = "renesas,pfc-r8a7790";
 485                 reg = <0 0xe6060000 0 0x250>;
 486         };
 487
 488         sdhi0: sd@ee100000 {
 489                 compatible = "renesas,sdhi-r8a7790";
 490                 reg = <0 0xee100000 0 0x328>;
 491                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 493                 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 494                 dma-names = "tx", "rx";
 495                 status = "disabled";
 496         };
 497
 498         sdhi1: sd@ee120000 {
 499                 compatible = "renesas,sdhi-r8a7790";
 500                 reg = <0 0xee120000 0 0x328>;
 501                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 502                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 503                 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
 504                 dma-names = "tx", "rx";
 505                 status = "disabled";
 506         };
 507
 508         sdhi2: sd@ee140000 {
 509                 compatible = "renesas,sdhi-r8a7790";
 510                 reg = <0 0xee140000 0 0x100>;
 511                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 513                 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 514                 dma-names = "tx", "rx";
 515                 status = "disabled";
 516         };
 517
 518         sdhi3: sd@ee160000 {
 519                 compatible = "renesas,sdhi-r8a7790";
 520                 reg = <0 0xee160000 0 0x100>;
 521                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 523                 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 524                 dma-names = "tx", "rx";
 525                 status = "disabled";
 526         };
 527
 528         scifa0: serial@e6c40000 {
 529                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 530                 reg = <0 0xe6c40000 0 64>;
 531                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 533                 clock-names = "sci_ick";
 534                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 535                 dma-names = "tx", "rx";
 536                 status = "disabled";
 537         };
 538
 539         scifa1: serial@e6c50000 {
 540                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 541                 reg = <0 0xe6c50000 0 64>;
 542                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 544                 clock-names = "sci_ick";
 545                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 546                 dma-names = "tx", "rx";
 547                 status = "disabled";
 548         };
 549
 550         scifa2: serial@e6c60000 {
 551                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 552                 reg = <0 0xe6c60000 0 64>;
 553                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 554                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 555                 clock-names = "sci_ick";
 556                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 557                 dma-names = "tx", "rx";
 558                 status = "disabled";
 559         };
 560
 561         scifb0: serial@e6c20000 {
 562                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 563                 reg = <0 0xe6c20000 0 64>;
 564                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 565                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 566                 clock-names = "sci_ick";
 567                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 568                 dma-names = "tx", "rx";
 569                 status = "disabled";
 570         };
 571
 572         scifb1: serial@e6c30000 {
 573                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 574                 reg = <0 0xe6c30000 0 64>;
 575                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 577                 clock-names = "sci_ick";
 578                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 579                 dma-names = "tx", "rx";
 580                 status = "disabled";
 581         };
 582
 583         scifb2: serial@e6ce0000 {
 584                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 585                 reg = <0 0xe6ce0000 0 64>;
 586                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 587                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 588                 clock-names = "sci_ick";
 589                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 590                 dma-names = "tx", "rx";
 591                 status = "disabled";
 592         };
 593
 594         scif0: serial@e6e60000 {
 595                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 596                 reg = <0 0xe6e60000 0 64>;
 597                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 598                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 599                 clock-names = "sci_ick";
 600                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 601                 dma-names = "tx", "rx";
 602                 status = "disabled";
 603         };
 604
 605         scif1: serial@e6e68000 {
 606                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 607                 reg = <0 0xe6e68000 0 64>;
 608                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 610                 clock-names = "sci_ick";
 611                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 612                 dma-names = "tx", "rx";
 613                 status = "disabled";
 614         };
 615
 616         hscif0: serial@e62c0000 {
 617                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 618                 reg = <0 0xe62c0000 0 96>;
 619                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 621                 clock-names = "sci_ick";
 622                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 623                 dma-names = "tx", "rx";
 624                 status = "disabled";
 625         };
 626
 627         hscif1: serial@e62c8000 {
 628                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 629                 reg = <0 0xe62c8000 0 96>;
 630                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 632                 clock-names = "sci_ick";
 633                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 634                 dma-names = "tx", "rx";
 635                 status = "disabled";
 636         };
 637
 638         ether: ethernet@ee700000 {
 639                 compatible = "renesas,ether-r8a7790";
 640                 reg = <0 0xee700000 0 0x400>;
 641                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
 643                 phy-mode = "rmii";
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         sata0: sata@ee300000 {
 650                 compatible = "renesas,sata-r8a7790";
 651                 reg = <0 0xee300000 0 0x2000>;
 652                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 654                 status = "disabled";
 655         };
 656
 657         sata1: sata@ee500000 {
 658                 compatible = "renesas,sata-r8a7790";
 659                 reg = <0 0xee500000 0 0x2000>;
 660                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 662                 status = "disabled";
 663         };
 664
 665         hsusb: usb@e6590000 {
 666                 compatible = "renesas,usbhs-r8a7790";
 667                 reg = <0 0xe6590000 0 0x100>;
 668                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 669                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 670                 renesas,buswait = <4>;
 671                 phys = <&usb0 1>;
 672                 phy-names = "usb";
 673                 status = "disabled";
 674         };
 675
 676         usbphy: usb-phy@e6590100 {
 677                 compatible = "renesas,usb-phy-r8a7790";
 678                 reg = <0 0xe6590100 0 0x100>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 682                 clock-names = "usbhs";
 683                 status = "disabled";
 684
 685                 usb0: usb-channel@0 {
 686                         reg = <0>;
 687                         #phy-cells = <1>;
 688                 };
 689                 usb2: usb-channel@2 {
 690                         reg = <2>;
 691                         #phy-cells = <1>;
 692                 };
 693         };
 694
 695         vin0: video@e6ef0000 {
 696                 compatible = "renesas,vin-r8a7790";
 697                 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
 698                 reg = <0 0xe6ef0000 0 0x1000>;
 699                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 700                 status = "disabled";
 701         };
 702
 703         vin1: video@e6ef1000 {
 704                 compatible = "renesas,vin-r8a7790";
 705                 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
 706                 reg = <0 0xe6ef1000 0 0x1000>;
 707                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 708                 status = "disabled";
 709         };
 710
 711         vin2: video@e6ef2000 {
 712                 compatible = "renesas,vin-r8a7790";
 713                 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
 714                 reg = <0 0xe6ef2000 0 0x1000>;
 715                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 716                 status = "disabled";
 717         };
 718
 719         vin3: video@e6ef3000 {
 720                 compatible = "renesas,vin-r8a7790";
 721                 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
 722                 reg = <0 0xe6ef3000 0 0x1000>;
 723                 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
 724                 status = "disabled";
 725         };
 726
 727         vsp1@fe920000 {
 728                 compatible = "renesas,vsp1";
 729                 reg = <0 0xfe920000 0 0x8000>;
 730                 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
 732
 733                 renesas,has-sru;
 734                 renesas,#rpf = <5>;
 735                 renesas,#uds = <1>;
 736                 renesas,#wpf = <4>;
 737         };
 738
 739         vsp1@fe928000 {
 740                 compatible = "renesas,vsp1";
 741                 reg = <0 0xfe928000 0 0x8000>;
 742                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 743                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
 744
 745                 renesas,has-lut;
 746                 renesas,has-sru;
 747                 renesas,#rpf = <5>;
 748                 renesas,#uds = <3>;
 749                 renesas,#wpf = <4>;
 750         };
 751
 752         vsp1@fe930000 {
 753                 compatible = "renesas,vsp1";
 754                 reg = <0 0xfe930000 0 0x8000>;
 755                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
 757
 758                 renesas,has-lif;
 759                 renesas,has-lut;
 760                 renesas,#rpf = <4>;
 761                 renesas,#uds = <1>;
 762                 renesas,#wpf = <4>;
 763         };
 764
 765         vsp1@fe938000 {
 766                 compatible = "renesas,vsp1";
 767                 reg = <0 0xfe938000 0 0x8000>;
 768                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
 770
 771                 renesas,has-lif;
 772                 renesas,has-lut;
 773                 renesas,#rpf = <4>;
 774                 renesas,#uds = <1>;
 775                 renesas,#wpf = <4>;
 776         };
 777
 778         du: display@feb00000 {
 779                 compatible = "renesas,du-r8a7790";
 780                 reg = <0 0xfeb00000 0 0x70000>,
 781                       <0 0xfeb90000 0 0x1c>,
 782                       <0 0xfeb94000 0 0x1c>;
 783                 reg-names = "du", "lvds.0", "lvds.1";
 784                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 785                              <0 268 IRQ_TYPE_LEVEL_HIGH>,
 786                              <0 269 IRQ_TYPE_LEVEL_HIGH>;
 787                 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
 788                          <&mstp7_clks R8A7790_CLK_DU1>,
 789                          <&mstp7_clks R8A7790_CLK_DU2>,
 790                          <&mstp7_clks R8A7790_CLK_LVDS0>,
 791                          <&mstp7_clks R8A7790_CLK_LVDS1>;
 792                 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
 793                 status = "disabled";
 794
 795                 ports {
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798
 799                         port@0 {
 800                                 reg = <0>;
 801                                 du_out_rgb: endpoint {
 802                                 };
 803                         };
 804                         port@1 {
 805                                 reg = <1>;
 806                                 du_out_lvds0: endpoint {
 807                                 };
 808                         };
 809                         port@2 {
 810                                 reg = <2>;
 811                                 du_out_lvds1: endpoint {
 812                                 };
 813                         };
 814                 };
 815         };
 816
 817         can0: can@e6e80000 {
 818                 compatible = "renesas,can-r8a7790";
 819                 reg = <0 0xe6e80000 0 0x1000>;
 820                 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
 821                 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
 822                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 823                 clock-names = "clkp1", "clkp2", "can_clk";
 824                 status = "disabled";
 825         };
 826
 827         can1: can@e6e88000 {
 828                 compatible = "renesas,can-r8a7790";
 829                 reg = <0 0xe6e88000 0 0x1000>;
 830                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
 831                 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
 832                          <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 833                 clock-names = "clkp1", "clkp2", "can_clk";
 834                 status = "disabled";
 835         };
 836
 837         clocks {
 838                 #address-cells = <2>;
 839                 #size-cells = <2>;
 840                 ranges;
 841
 842                 /* External root clock */
 843                 extal_clk: extal_clk {
 844                         compatible = "fixed-clock";
 845                         #clock-cells = <0>;
 846                         /* This value must be overriden by the board. */
 847                         clock-frequency = <0>;
 848                         clock-output-names = "extal";
 849                 };
 850
 851                 /* External PCIe clock - can be overridden by the board */
 852                 pcie_bus_clk: pcie_bus_clk {
 853                         compatible = "fixed-clock";
 854                         #clock-cells = <0>;
 855                         clock-frequency = <100000000>;
 856                         clock-output-names = "pcie_bus";
 857                         status = "disabled";
 858                 };
 859
 860                 /*
 861                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 862                  * default. Boards that provide audio clocks should override them.
 863                  */
 864                 audio_clk_a: audio_clk_a {
 865                         compatible = "fixed-clock";
 866                         #clock-cells = <0>;
 867                         clock-frequency = <0>;
 868                         clock-output-names = "audio_clk_a";
 869                 };
 870                 audio_clk_b: audio_clk_b {
 871                         compatible = "fixed-clock";
 872                         #clock-cells = <0>;
 873                         clock-frequency = <0>;
 874                         clock-output-names = "audio_clk_b";
 875                 };
 876                 audio_clk_c: audio_clk_c {
 877                         compatible = "fixed-clock";
 878                         #clock-cells = <0>;
 879                         clock-frequency = <0>;
 880                         clock-output-names = "audio_clk_c";
 881                 };
 882
 883                 /* External USB clock - can be overridden by the board */
 884                 usb_extal_clk: usb_extal_clk {
 885                         compatible = "fixed-clock";
 886                         #clock-cells = <0>;
 887                         clock-frequency = <48000000>;
 888                         clock-output-names = "usb_extal";
 889                 };
 890
 891                 /* External CAN clock */
 892                 can_clk: can_clk {
 893                         compatible = "fixed-clock";
 894                         #clock-cells = <0>;
 895                         /* This value must be overridden by the board. */
 896                         clock-frequency = <0>;
 897                         clock-output-names = "can_clk";
 898                         status = "disabled";
 899                 };
 900
 901                 /* Special CPG clocks */
 902                 cpg_clocks: cpg_clocks@e6150000 {
 903                         compatible = "renesas,r8a7790-cpg-clocks",
 904                                      "renesas,rcar-gen2-cpg-clocks";
 905                         reg = <0 0xe6150000 0 0x1000>;
 906                         clocks = <&extal_clk &usb_extal_clk>;
 907                         #clock-cells = <1>;
 908                         clock-output-names = "main", "pll0", "pll1", "pll3",
 909                                              "lb", "qspi", "sdh", "sd0", "sd1",
 910                                              "z", "rcan", "adsp";
 911                 };
 912
 913                 /* Variable factor clocks */
 914                 sd2_clk: sd2_clk@e6150078 {
 915                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 916                         reg = <0 0xe6150078 0 4>;
 917                         clocks = <&pll1_div2_clk>;
 918                         #clock-cells = <0>;
 919                         clock-output-names = "sd2";
 920                 };
 921                 sd3_clk: sd3_clk@e615026c {
 922                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 923                         reg = <0 0xe615026c 0 4>;
 924                         clocks = <&pll1_div2_clk>;
 925                         #clock-cells = <0>;
 926                         clock-output-names = "sd3";
 927                 };
 928                 mmc0_clk: mmc0_clk@e6150240 {
 929                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 930                         reg = <0 0xe6150240 0 4>;
 931                         clocks = <&pll1_div2_clk>;
 932                         #clock-cells = <0>;
 933                         clock-output-names = "mmc0";
 934                 };
 935                 mmc1_clk: mmc1_clk@e6150244 {
 936                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 937                         reg = <0 0xe6150244 0 4>;
 938                         clocks = <&pll1_div2_clk>;
 939                         #clock-cells = <0>;
 940                         clock-output-names = "mmc1";
 941                 };
 942                 ssp_clk: ssp_clk@e6150248 {
 943                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 944                         reg = <0 0xe6150248 0 4>;
 945                         clocks = <&pll1_div2_clk>;
 946                         #clock-cells = <0>;
 947                         clock-output-names = "ssp";
 948                 };
 949                 ssprs_clk: ssprs_clk@e615024c {
 950                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 951                         reg = <0 0xe615024c 0 4>;
 952                         clocks = <&pll1_div2_clk>;
 953                         #clock-cells = <0>;
 954                         clock-output-names = "ssprs";
 955                 };
 956
 957                 /* Fixed factor clocks */
 958                 pll1_div2_clk: pll1_div2_clk {
 959                         compatible = "fixed-factor-clock";
 960                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 961                         #clock-cells = <0>;
 962                         clock-div = <2>;
 963                         clock-mult = <1>;
 964                         clock-output-names = "pll1_div2";
 965                 };
 966                 z2_clk: z2_clk {
 967                         compatible = "fixed-factor-clock";
 968                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 969                         #clock-cells = <0>;
 970                         clock-div = <2>;
 971                         clock-mult = <1>;
 972                         clock-output-names = "z2";
 973                 };
 974                 zg_clk: zg_clk {
 975                         compatible = "fixed-factor-clock";
 976                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 977                         #clock-cells = <0>;
 978                         clock-div = <3>;
 979                         clock-mult = <1>;
 980                         clock-output-names = "zg";
 981                 };
 982                 zx_clk: zx_clk {
 983                         compatible = "fixed-factor-clock";
 984                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 985                         #clock-cells = <0>;
 986                         clock-div = <3>;
 987                         clock-mult = <1>;
 988                         clock-output-names = "zx";
 989                 };
 990                 zs_clk: zs_clk {
 991                         compatible = "fixed-factor-clock";
 992                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 993                         #clock-cells = <0>;
 994                         clock-div = <6>;
 995                         clock-mult = <1>;
 996                         clock-output-names = "zs";
 997                 };
 998                 hp_clk: hp_clk {
 999                         compatible = "fixed-factor-clock";
1000                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1001                         #clock-cells = <0>;
1002                         clock-div = <12>;
1003                         clock-mult = <1>;
1004                         clock-output-names = "hp";
1005                 };
1006                 i_clk: i_clk {
1007                         compatible = "fixed-factor-clock";
1008                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1009                         #clock-cells = <0>;
1010                         clock-div = <2>;
1011                         clock-mult = <1>;
1012                         clock-output-names = "i";
1013                 };
1014                 b_clk: b_clk {
1015                         compatible = "fixed-factor-clock";
1016                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1017                         #clock-cells = <0>;
1018                         clock-div = <12>;
1019                         clock-mult = <1>;
1020                         clock-output-names = "b";
1021                 };
1022                 p_clk: p_clk {
1023                         compatible = "fixed-factor-clock";
1024                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1025                         #clock-cells = <0>;
1026                         clock-div = <24>;
1027                         clock-mult = <1>;
1028                         clock-output-names = "p";
1029                 };
1030                 cl_clk: cl_clk {
1031                         compatible = "fixed-factor-clock";
1032                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1033                         #clock-cells = <0>;
1034                         clock-div = <48>;
1035                         clock-mult = <1>;
1036                         clock-output-names = "cl";
1037                 };
1038                 m2_clk: m2_clk {
1039                         compatible = "fixed-factor-clock";
1040                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1041                         #clock-cells = <0>;
1042                         clock-div = <8>;
1043                         clock-mult = <1>;
1044                         clock-output-names = "m2";
1045                 };
1046                 imp_clk: imp_clk {
1047                         compatible = "fixed-factor-clock";
1048                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1049                         #clock-cells = <0>;
1050                         clock-div = <4>;
1051                         clock-mult = <1>;
1052                         clock-output-names = "imp";
1053                 };
1054                 rclk_clk: rclk_clk {
1055                         compatible = "fixed-factor-clock";
1056                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1057                         #clock-cells = <0>;
1058                         clock-div = <(48 * 1024)>;
1059                         clock-mult = <1>;
1060                         clock-output-names = "rclk";
1061                 };
1062                 oscclk_clk: oscclk_clk {
1063                         compatible = "fixed-factor-clock";
1064                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1065                         #clock-cells = <0>;
1066                         clock-div = <(12 * 1024)>;
1067                         clock-mult = <1>;
1068                         clock-output-names = "oscclk";
1069                 };
1070                 zb3_clk: zb3_clk {
1071                         compatible = "fixed-factor-clock";
1072                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1073                         #clock-cells = <0>;
1074                         clock-div = <4>;
1075                         clock-mult = <1>;
1076                         clock-output-names = "zb3";
1077                 };
1078                 zb3d2_clk: zb3d2_clk {
1079                         compatible = "fixed-factor-clock";
1080                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1081                         #clock-cells = <0>;
1082                         clock-div = <8>;
1083                         clock-mult = <1>;
1084                         clock-output-names = "zb3d2";
1085                 };
1086                 ddr_clk: ddr_clk {
1087                         compatible = "fixed-factor-clock";
1088                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1089                         #clock-cells = <0>;
1090                         clock-div = <8>;
1091                         clock-mult = <1>;
1092                         clock-output-names = "ddr";
1093                 };
1094                 mp_clk: mp_clk {
1095                         compatible = "fixed-factor-clock";
1096                         clocks = <&pll1_div2_clk>;
1097                         #clock-cells = <0>;
1098                         clock-div = <15>;
1099                         clock-mult = <1>;
1100                         clock-output-names = "mp";
1101                 };
1102                 cp_clk: cp_clk {
1103                         compatible = "fixed-factor-clock";
1104                         clocks = <&extal_clk>;
1105                         #clock-cells = <0>;
1106                         clock-div = <2>;
1107                         clock-mult = <1>;
1108                         clock-output-names = "cp";
1109                 };
1110
1111                 /* Gate clocks */
1112                 mstp0_clks: mstp0_clks@e6150130 {
1113                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1114                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1115                         clocks = <&mp_clk>;
1116                         #clock-cells = <1>;
1117                         clock-indices = <R8A7790_CLK_MSIOF0>;
1118                         clock-output-names = "msiof0";
1119                 };
1120                 mstp1_clks: mstp1_clks@e6150134 {
1121                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1122                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1123                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1124                                  <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1125                                  <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1126                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1127                         #clock-cells = <1>;
1128                         clock-indices = <
1129                                 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1130                                 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1131                                 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1132                                 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1133                                 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1134                                 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1135                                 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1136                         >;
1137                         clock-output-names =
1138                                 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1139                                 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1140                                 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1141                                 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1142                 };
1143                 mstp2_clks: mstp2_clks@e6150138 {
1144                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1145                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1146                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1147                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1148                                  <&zs_clk>;
1149                         #clock-cells = <1>;
1150                         clock-indices = <
1151                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1152                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1153                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1154                                 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1155                         >;
1156                         clock-output-names =
1157                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1158                                 "scifb1", "msiof1", "msiof3", "scifb2",
1159                                 "sys-dmac1", "sys-dmac0";
1160                 };
1161                 mstp3_clks: mstp3_clks@e615013c {
1162                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1163                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1164                         clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1165                                  <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1166                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1167                                  <&hp_clk>, <&hp_clk>;
1168                         #clock-cells = <1>;
1169                         clock-indices = <
1170                                 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1171                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1172                                 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1173                                 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1174                         >;
1175                         clock-output-names =
1176                                 "iic2", "tpu0", "mmcif1", "sdhi3",
1177                                 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1178                                 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1179                                 "usbdmac0", "usbdmac1";
1180                 };
1181                 mstp5_clks: mstp5_clks@e6150144 {
1182                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1183                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1184                         clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1185                                  <&extal_clk>, <&p_clk>;
1186                         #clock-cells = <1>;
1187                         clock-indices = <
1188                                 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1189                                 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1190                                 R8A7790_CLK_PWM
1191                         >;
1192                         clock-output-names = "audmac0", "audmac1", "adsp_mod",
1193                                              "thermal", "pwm";
1194                 };
1195                 mstp7_clks: mstp7_clks@e615014c {
1196                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1197                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1198                         clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1199                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1200                                  <&zx_clk>;
1201                         #clock-cells = <1>;
1202                         clock-indices = <
1203                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1204                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1205                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1206                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1207                         >;
1208                         clock-output-names =
1209                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1210                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1211                 };
1212                 mstp8_clks: mstp8_clks@e6150990 {
1213                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1214                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1215                         clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1216                                  <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1217                         #clock-cells = <1>;
1218                         clock-indices = <
1219                                 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1220                                 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
1221                                 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1222                         >;
1223                         clock-output-names =
1224                                 "mlb", "vin3", "vin2", "vin1", "vin0", "ether",
1225                                 "sata1", "sata0";
1226                 };
1227                 mstp9_clks: mstp9_clks@e6150994 {
1228                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1229                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1230                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1231                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1232                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1233                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1234                         #clock-cells = <1>;
1235                         clock-indices = <
1236                                 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1237                                 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1238                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1239                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1240                         >;
1241                         clock-output-names =
1242                                 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1243                                 "rcan1", "rcan0", "qspi_mod", "iic3",
1244                                 "i2c3", "i2c2", "i2c1", "i2c0";
1245                 };
1246                 mstp10_clks: mstp10_clks@e6150998 {
1247                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1248                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1249                         clocks = <&p_clk>,
1250                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1251                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1252                                 <&p_clk>,
1253                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1254                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1255                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1256                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1257                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1258                                 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1259
1260                         #clock-cells = <1>;
1261                         clock-indices = <
1262                                 R8A7790_CLK_SSI_ALL
1263                                 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1264                                 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1265                                 R8A7790_CLK_SCU_ALL
1266                                 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1267                                 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1268                                 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1269                         >;
1270                         clock-output-names =
1271                                 "ssi-all",
1272                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1273                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1274                                 "scu-all",
1275                                 "scu-dvc1", "scu-dvc0",
1276                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1277                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1278                 };
1279         };
1280
1281         qspi: spi@e6b10000 {
1282                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1283                 reg = <0 0xe6b10000 0 0x2c>;
1284                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1285                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1286                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1287                 dma-names = "tx", "rx";
1288                 num-cs = <1>;
1289                 #address-cells = <1>;
1290                 #size-cells = <0>;
1291                 status = "disabled";
1292         };
1293
1294         msiof0: spi@e6e20000 {
1295                 compatible = "renesas,msiof-r8a7790";
1296                 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1297                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1298                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1299                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1300                 dma-names = "tx", "rx";
1301                 #address-cells = <1>;
1302                 #size-cells = <0>;
1303                 status = "disabled";
1304         };
1305
1306         msiof1: spi@e6e10000 {
1307                 compatible = "renesas,msiof-r8a7790";
1308                 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1309                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1310                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1311                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1312                 dma-names = "tx", "rx";
1313                 #address-cells = <1>;
1314                 #size-cells = <0>;
1315                 status = "disabled";
1316         };
1317
1318         msiof2: spi@e6e00000 {
1319                 compatible = "renesas,msiof-r8a7790";
1320                 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1321                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1322                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1323                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1324                 dma-names = "tx", "rx";
1325                 #address-cells = <1>;
1326                 #size-cells = <0>;
1327                 status = "disabled";
1328         };
1329
1330         msiof3: spi@e6c90000 {
1331                 compatible = "renesas,msiof-r8a7790";
1332                 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
1333                 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1334                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1335                 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1336                 dma-names = "tx", "rx";
1337                 #address-cells = <1>;
1338                 #size-cells = <0>;
1339                 status = "disabled";
1340         };
1341
1342         xhci: usb@ee000000 {
1343                 compatible = "renesas,xhci-r8a7790";
1344                 reg = <0 0xee000000 0 0xc00>;
1345                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1346                 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1347                 phys = <&usb2 1>;
1348                 phy-names = "usb";
1349                 status = "disabled";
1350         };
1351
1352         pci0: pci@ee090000 {
1353                 compatible = "renesas,pci-r8a7790";
1354                 device_type = "pci";
1355                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1356                 reg = <0 0xee090000 0 0xc00>,
1357                       <0 0xee080000 0 0x1100>;
1358                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1359                 status = "disabled";
1360
1361                 bus-range = <0 0>;
1362                 #address-cells = <3>;
1363                 #size-cells = <2>;
1364                 #interrupt-cells = <1>;
1365                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1366                 interrupt-map-mask = <0xff00 0 0 0x7>;
1367                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1368                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1369                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1370
1371                 usb@0,1 {
1372                         reg = <0x800 0 0 0 0>;
1373                         device_type = "pci";
1374                         phys = <&usb0 0>;
1375                         phy-names = "usb";
1376                 };
1377
1378                 usb@0,2 {
1379                         reg = <0x1000 0 0 0 0>;
1380                         device_type = "pci";
1381                         phys = <&usb0 0>;
1382                         phy-names = "usb";
1383                 };
1384         };
1385
1386         pci1: pci@ee0b0000 {
1387                 compatible = "renesas,pci-r8a7790";
1388                 device_type = "pci";
1389                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1390                 reg = <0 0xee0b0000 0 0xc00>,
1391                       <0 0xee0a0000 0 0x1100>;
1392                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1393                 status = "disabled";
1394
1395                 bus-range = <1 1>;
1396                 #address-cells = <3>;
1397                 #size-cells = <2>;
1398                 #interrupt-cells = <1>;
1399                 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1400                 interrupt-map-mask = <0xff00 0 0 0x7>;
1401                 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1402                                  0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1403                                  0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
1404         };
1405
1406         pci2: pci@ee0d0000 {
1407                 compatible = "renesas,pci-r8a7790";
1408                 device_type = "pci";
1409                 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1410                 reg = <0 0xee0d0000 0 0xc00>,
1411                       <0 0xee0c0000 0 0x1100>;
1412                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1413                 status = "disabled";
1414
1415                 bus-range = <2 2>;
1416                 #address-cells = <3>;
1417                 #size-cells = <2>;
1418                 #interrupt-cells = <1>;
1419                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1420                 interrupt-map-mask = <0xff00 0 0 0x7>;
1421                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1422                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1423                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1424
1425                 usb@0,1 {
1426                         reg = <0x800 0 0 0 0>;
1427                         device_type = "pci";
1428                         phys = <&usb2 0>;
1429                         phy-names = "usb";
1430                 };
1431
1432                 usb@0,2 {
1433                         reg = <0x1000 0 0 0 0>;
1434                         device_type = "pci";
1435                         phys = <&usb2 0>;
1436                         phy-names = "usb";
1437                 };
1438         };
1439
1440         pciec: pcie@fe000000 {
1441                 compatible = "renesas,pcie-r8a7790";
1442                 reg = <0 0xfe000000 0 0x80000>;
1443                 #address-cells = <3>;
1444                 #size-cells = <2>;
1445                 bus-range = <0x00 0xff>;
1446                 device_type = "pci";
1447                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1448                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1449                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1450                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1451                 /* Map all possible DDR as inbound ranges */
1452                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1453                               0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1454                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1455                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1456                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1457                 #interrupt-cells = <1>;
1458                 interrupt-map-mask = <0 0 0 0>;
1459                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1460                 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1461                 clock-names = "pcie", "pcie_bus";
1462                 status = "disabled";
1463         };
1464
1465         rcar_sound: rcar_sound@ec500000 {
1466                 /*
1467                  * #sound-dai-cells is required
1468                  *
1469                  * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
1470                  * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
1471                  */
1472                 compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1473                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1474                         <0 0xec5a0000 0 0x100>,  /* ADG */
1475                         <0 0xec540000 0 0x1000>, /* SSIU */
1476                         <0 0xec541000 0 0x1280>, /* SSI */
1477                         <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
1478                 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1479
1480                 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1481                         <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1482                         <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1483                         <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1484                         <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1485                         <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1486                         <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1487                         <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1488                         <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1489                         <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1490                         <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1491                         <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1492                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1493                 clock-names = "ssi-all",
1494                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1495                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1496                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1497                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1498                                 "dvc.0", "dvc.1",
1499                                 "clk_a", "clk_b", "clk_c", "clk_i";
1500
1501                 status = "disabled";
1502
1503                 rcar_sound,dvc {
1504                         dvc0: dvc@0 {
1505                                 dmas = <&audma0 0xbc>;
1506                                 dma-names = "tx";
1507                         };
1508                         dvc1: dvc@1 {
1509                                 dmas = <&audma0 0xbe>;
1510                                 dma-names = "tx";
1511                         };
1512                 };
1513
1514                 rcar_sound,src {
1515                         src0: src@0 {
1516                                 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1517                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1518                                 dma-names = "rx", "tx";
1519                         };
1520                         src1: src@1 {
1521                                 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1522                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1523                                 dma-names = "rx", "tx";
1524                         };
1525                         src2: src@2 {
1526                                 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1527                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1528                                 dma-names = "rx", "tx";
1529                         };
1530                         src3: src@3 {
1531                                 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1532                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1533                                 dma-names = "rx", "tx";
1534                         };
1535                         src4: src@4 {
1536                                 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1537                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1538                                 dma-names = "rx", "tx";
1539                         };
1540                         src5: src@5 {
1541                                 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1542                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1543                                 dma-names = "rx", "tx";
1544                         };
1545                         src6: src@6 {
1546                                 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1547                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1548                                 dma-names = "rx", "tx";
1549                         };
1550                         src7: src@7 {
1551                                 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1552                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1553                                 dma-names = "rx", "tx";
1554                         };
1555                         src8: src@8 {
1556                                 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1557                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1558                                 dma-names = "rx", "tx";
1559                         };
1560                         src9: src@9 {
1561                                 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1562                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
1563                                 dma-names = "rx", "tx";
1564                         };
1565                 };
1566
1567                 rcar_sound,ssi {
1568                         ssi0: ssi@0 {
1569                                 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1570                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1571                                 dma-names = "rx", "tx", "rxu", "txu";
1572                         };
1573                         ssi1: ssi@1 {
1574                                  interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1575                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1576                                 dma-names = "rx", "tx", "rxu", "txu";
1577                         };
1578                         ssi2: ssi@2 {
1579                                 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1580                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1581                                 dma-names = "rx", "tx", "rxu", "txu";
1582                         };
1583                         ssi3: ssi@3 {
1584                                 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1585                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1586                                 dma-names = "rx", "tx", "rxu", "txu";
1587                         };
1588                         ssi4: ssi@4 {
1589                                 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1590                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1591                                 dma-names = "rx", "tx", "rxu", "txu";
1592                         };
1593                         ssi5: ssi@5 {
1594                                 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1595                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1596                                 dma-names = "rx", "tx", "rxu", "txu";
1597                         };
1598                         ssi6: ssi@6 {
1599                                 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1600                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1601                                 dma-names = "rx", "tx", "rxu", "txu";
1602                         };
1603                         ssi7: ssi@7 {
1604                                 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1605                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1606                                 dma-names = "rx", "tx", "rxu", "txu";
1607                         };
1608                         ssi8: ssi@8 {
1609                                 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1610                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1611                                 dma-names = "rx", "tx", "rxu", "txu";
1612                         };
1613                         ssi9: ssi@9 {
1614                                 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1615                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1616                                 dma-names = "rx", "tx", "rxu", "txu";
1617                         };
1618                 };
1619         };
1620
1621         ipmmu_sy0: mmu@e6280000 {
1622                 compatible = "renesas,ipmmu-vmsa";
1623                 reg = <0 0xe6280000 0 0x1000>;
1624                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1625                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
1626                 #iommu-cells = <1>;
1627                 status = "disabled";
1628         };
1629
1630         ipmmu_sy1: mmu@e6290000 {
1631                 compatible = "renesas,ipmmu-vmsa";
1632                 reg = <0 0xe6290000 0 0x1000>;
1633                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1634                 #iommu-cells = <1>;
1635                 status = "disabled";
1636         };
1637
1638         ipmmu_ds: mmu@e6740000 {
1639                 compatible = "renesas,ipmmu-vmsa";
1640                 reg = <0 0xe6740000 0 0x1000>;
1641                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1642                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
1643                 #iommu-cells = <1>;
1644                 status = "disabled";
1645         };
1646
1647         ipmmu_mp: mmu@ec680000 {
1648                 compatible = "renesas,ipmmu-vmsa";
1649                 reg = <0 0xec680000 0 0x1000>;
1650                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1651                 #iommu-cells = <1>;
1652                 status = "disabled";
1653         };
1654
1655         ipmmu_mx: mmu@fe951000 {
1656                 compatible = "renesas,ipmmu-vmsa";
1657                 reg = <0 0xfe951000 0 0x1000>;
1658                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1659                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
1660                 #iommu-cells = <1>;
1661                 status = "disabled";
1662         };
1663
1664         ipmmu_rt: mmu@ffc80000 {
1665                 compatible = "renesas,ipmmu-vmsa";
1666                 reg = <0 0xffc80000 0 0x1000>;
1667                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1668                 #iommu-cells = <1>;
1669                 status = "disabled";
1670         };
1671 };