arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a7-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         cmt0: timer@ffca0000 {
  54                 compatible = "renesas,cmt-48-gen2";
  55                 reg = <0 0xffca0000 0 0x1004>;
  56                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
  57                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
  58                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
  59                 clock-names = "fck";
  60
  61                 renesas,channels-mask = <0x60>;
  62
  63                 status = "disabled";
  64         };
  65
  66         cmt1: timer@e6130000 {
  67                 compatible = "renesas,cmt-48-gen2";
  68                 reg = <0 0xe6130000 0 0x1004>;
  69                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
  70                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
  71                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
  72                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
  73                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
  74                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
  75                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
  76                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
  78                 clock-names = "fck";
  79
  80                 renesas,channels-mask = <0xff>;
  81
  82                 status = "disabled";
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv7-timer";
  87                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  91         };
  92
  93         irqc0: interrupt-controller@e61c0000 {
  94                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97                 reg = <0 0xe61c0000 0 0x200>;
  98                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
  99                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 100                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 101                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 102                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 103                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 104                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 105                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 106                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 107                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 108                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 109         };
 110
 111         dmac0: dma-controller@e6700000 {
 112                 compatible = "renesas,rcar-dmac";
 113                 reg = <0 0xe6700000 0 0x20000>;
 114                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 115                               0 200 IRQ_TYPE_LEVEL_HIGH
 116                               0 201 IRQ_TYPE_LEVEL_HIGH
 117                               0 202 IRQ_TYPE_LEVEL_HIGH
 118                               0 203 IRQ_TYPE_LEVEL_HIGH
 119                               0 204 IRQ_TYPE_LEVEL_HIGH
 120                               0 205 IRQ_TYPE_LEVEL_HIGH
 121                               0 206 IRQ_TYPE_LEVEL_HIGH
 122                               0 207 IRQ_TYPE_LEVEL_HIGH
 123                               0 208 IRQ_TYPE_LEVEL_HIGH
 124                               0 209 IRQ_TYPE_LEVEL_HIGH
 125                               0 210 IRQ_TYPE_LEVEL_HIGH
 126                               0 211 IRQ_TYPE_LEVEL_HIGH
 127                               0 212 IRQ_TYPE_LEVEL_HIGH
 128                               0 213 IRQ_TYPE_LEVEL_HIGH
 129                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 130                 interrupt-names = "error",
 131                                 "ch0", "ch1", "ch2", "ch3",
 132                                 "ch4", "ch5", "ch6", "ch7",
 133                                 "ch8", "ch9", "ch10", "ch11",
 134                                 "ch12", "ch13", "ch14";
 135                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 136                 clock-names = "fck";
 137                 #dma-cells = <1>;
 138                 dma-channels = <15>;
 139         };
 140
 141         dmac1: dma-controller@e6720000 {
 142                 compatible = "renesas,rcar-dmac";
 143                 reg = <0 0xe6720000 0 0x20000>;
 144                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 145                               0 216 IRQ_TYPE_LEVEL_HIGH
 146                               0 217 IRQ_TYPE_LEVEL_HIGH
 147                               0 218 IRQ_TYPE_LEVEL_HIGH
 148                               0 219 IRQ_TYPE_LEVEL_HIGH
 149                               0 308 IRQ_TYPE_LEVEL_HIGH
 150                               0 309 IRQ_TYPE_LEVEL_HIGH
 151                               0 310 IRQ_TYPE_LEVEL_HIGH
 152                               0 311 IRQ_TYPE_LEVEL_HIGH
 153                               0 312 IRQ_TYPE_LEVEL_HIGH
 154                               0 313 IRQ_TYPE_LEVEL_HIGH
 155                               0 314 IRQ_TYPE_LEVEL_HIGH
 156                               0 315 IRQ_TYPE_LEVEL_HIGH
 157                               0 316 IRQ_TYPE_LEVEL_HIGH
 158                               0 317 IRQ_TYPE_LEVEL_HIGH
 159                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 160                 interrupt-names = "error",
 161                                 "ch0", "ch1", "ch2", "ch3",
 162                                 "ch4", "ch5", "ch6", "ch7",
 163                                 "ch8", "ch9", "ch10", "ch11",
 164                                 "ch12", "ch13", "ch14";
 165                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 166                 clock-names = "fck";
 167                 #dma-cells = <1>;
 168                 dma-channels = <15>;
 169         };
 170
 171         scifa0: serial@e6c40000 {
 172                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 173                 reg = <0 0xe6c40000 0 64>;
 174                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 176                 clock-names = "sci_ick";
 177                 status = "disabled";
 178         };
 179
 180         scifa1: serial@e6c50000 {
 181                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 182                 reg = <0 0xe6c50000 0 64>;
 183                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 185                 clock-names = "sci_ick";
 186                 status = "disabled";
 187         };
 188
 189         scifa2: serial@e6c60000 {
 190                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 191                 reg = <0 0xe6c60000 0 64>;
 192                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 194                 clock-names = "sci_ick";
 195                 status = "disabled";
 196         };
 197
 198         scifa3: serial@e6c70000 {
 199                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 200                 reg = <0 0xe6c70000 0 64>;
 201                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 203                 clock-names = "sci_ick";
 204                 status = "disabled";
 205         };
 206
 207         scifa4: serial@e6c78000 {
 208                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 209                 reg = <0 0xe6c78000 0 64>;
 210                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 212                 clock-names = "sci_ick";
 213                 status = "disabled";
 214         };
 215
 216         scifa5: serial@e6c80000 {
 217                 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
 218                 reg = <0 0xe6c80000 0 64>;
 219                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 221                 clock-names = "sci_ick";
 222                 status = "disabled";
 223         };
 224
 225         scifb0: serial@e6c20000 {
 226                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 227                 reg = <0 0xe6c20000 0 64>;
 228                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 230                 clock-names = "sci_ick";
 231                 status = "disabled";
 232         };
 233
 234         scifb1: serial@e6c30000 {
 235                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 236                 reg = <0 0xe6c30000 0 64>;
 237                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 239                 clock-names = "sci_ick";
 240                 status = "disabled";
 241         };
 242
 243         scifb2: serial@e6ce0000 {
 244                 compatible = "renesas,scifb-r8a7794", "renesas,scifb";
 245                 reg = <0 0xe6ce0000 0 64>;
 246                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 248                 clock-names = "sci_ick";
 249                 status = "disabled";
 250         };
 251
 252         scif0: serial@e6e60000 {
 253                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 254                 reg = <0 0xe6e60000 0 64>;
 255                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
 257                 clock-names = "sci_ick";
 258                 status = "disabled";
 259         };
 260
 261         scif1: serial@e6e68000 {
 262                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 263                 reg = <0 0xe6e68000 0 64>;
 264                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 265                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
 266                 clock-names = "sci_ick";
 267                 status = "disabled";
 268         };
 269
 270         scif2: serial@e6e58000 {
 271                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 272                 reg = <0 0xe6e58000 0 64>;
 273                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
 275                 clock-names = "sci_ick";
 276                 status = "disabled";
 277         };
 278
 279         scif3: serial@e6ea8000 {
 280                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 281                 reg = <0 0xe6ea8000 0 64>;
 282                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
 284                 clock-names = "sci_ick";
 285                 status = "disabled";
 286         };
 287
 288         scif4: serial@e6ee0000 {
 289                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 290                 reg = <0 0xe6ee0000 0 64>;
 291                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
 293                 clock-names = "sci_ick";
 294                 status = "disabled";
 295         };
 296
 297         scif5: serial@e6ee8000 {
 298                 compatible = "renesas,scif-r8a7794", "renesas,scif";
 299                 reg = <0 0xe6ee8000 0 64>;
 300                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 301                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
 302                 clock-names = "sci_ick";
 303                 status = "disabled";
 304         };
 305
 306         hscif0: serial@e62c0000 {
 307                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 308                 reg = <0 0xe62c0000 0 96>;
 309                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
 311                 clock-names = "sci_ick";
 312                 status = "disabled";
 313         };
 314
 315         hscif1: serial@e62c8000 {
 316                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 317                 reg = <0 0xe62c8000 0 96>;
 318                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
 320                 clock-names = "sci_ick";
 321                 status = "disabled";
 322         };
 323
 324         hscif2: serial@e62d0000 {
 325                 compatible = "renesas,hscif-r8a7794", "renesas,hscif";
 326                 reg = <0 0xe62d0000 0 96>;
 327                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
 329                 clock-names = "sci_ick";
 330                 status = "disabled";
 331         };
 332
 333         ether: ethernet@ee700000 {
 334                 compatible = "renesas,ether-r8a7794";
 335                 reg = <0 0xee700000 0 0x400>;
 336                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 338                 phy-mode = "rmii";
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 status = "disabled";
 342         };
 343
 344         sdhi0: sd@ee100000 {
 345                 compatible = "renesas,sdhi-r8a7794";
 346                 reg = <0 0xee100000 0 0x200>;
 347                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 349                 status = "disabled";
 350         };
 351
 352         sdhi1: sd@ee140000 {
 353                 compatible = "renesas,sdhi-r8a7794";
 354                 reg = <0 0xee140000 0 0x100>;
 355                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 357                 status = "disabled";
 358         };
 359
 360         sdhi2: sd@ee160000 {
 361                 compatible = "renesas,sdhi-r8a7794";
 362                 reg = <0 0xee160000 0 0x100>;
 363                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 365                 status = "disabled";
 366         };
 367
 368         clocks {
 369                 #address-cells = <2>;
 370                 #size-cells = <2>;
 371                 ranges;
 372
 373                 /* External root clock */
 374                 extal_clk: extal_clk {
 375                         compatible = "fixed-clock";
 376                         #clock-cells = <0>;
 377                         /* This value must be overriden by the board. */
 378                         clock-frequency = <0>;
 379                         clock-output-names = "extal";
 380                 };
 381
 382                 /* Special CPG clocks */
 383                 cpg_clocks: cpg_clocks@e6150000 {
 384                         compatible = "renesas,r8a7794-cpg-clocks",
 385                                      "renesas,rcar-gen2-cpg-clocks";
 386                         reg = <0 0xe6150000 0 0x1000>;
 387                         clocks = <&extal_clk>;
 388                         #clock-cells = <1>;
 389                         clock-output-names = "main", "pll0", "pll1", "pll3",
 390                                              "lb", "qspi", "sdh", "sd0", "z";
 391                 };
 392                 /* Variable factor clocks */
 393                 sd2_clk: sd2_clk@e6150078 {
 394                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 395                         reg = <0 0xe6150078 0 4>;
 396                         clocks = <&pll1_div2_clk>;
 397                         #clock-cells = <0>;
 398                         clock-output-names = "sd2";
 399                 };
 400                 sd3_clk: sd3_clk@e615026c {
 401                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 402                         reg = <0 0xe615026c 0 4>;
 403                         clocks = <&pll1_div2_clk>;
 404                         #clock-cells = <0>;
 405                         clock-output-names = "sd3";
 406                 };
 407                 mmc0_clk: mmc0_clk@e6150240 {
 408                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 409                         reg = <0 0xe6150240 0 4>;
 410                         clocks = <&pll1_div2_clk>;
 411                         #clock-cells = <0>;
 412                         clock-output-names = "mmc0";
 413                 };
 414
 415                 /* Fixed factor clocks */
 416                 pll1_div2_clk: pll1_div2_clk {
 417                         compatible = "fixed-factor-clock";
 418                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 419                         #clock-cells = <0>;
 420                         clock-div = <2>;
 421                         clock-mult = <1>;
 422                         clock-output-names = "pll1_div2";
 423                 };
 424                 zg_clk: zg_clk {
 425                         compatible = "fixed-factor-clock";
 426                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 427                         #clock-cells = <0>;
 428                         clock-div = <6>;
 429                         clock-mult = <1>;
 430                         clock-output-names = "zg";
 431                 };
 432                 zx_clk: zx_clk {
 433                         compatible = "fixed-factor-clock";
 434                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 435                         #clock-cells = <0>;
 436                         clock-div = <3>;
 437                         clock-mult = <1>;
 438                         clock-output-names = "zx";
 439                 };
 440                 zs_clk: zs_clk {
 441                         compatible = "fixed-factor-clock";
 442                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 443                         #clock-cells = <0>;
 444                         clock-div = <6>;
 445                         clock-mult = <1>;
 446                         clock-output-names = "zs";
 447                 };
 448                 hp_clk: hp_clk {
 449                         compatible = "fixed-factor-clock";
 450                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 451                         #clock-cells = <0>;
 452                         clock-div = <12>;
 453                         clock-mult = <1>;
 454                         clock-output-names = "hp";
 455                 };
 456                 i_clk: i_clk {
 457                         compatible = "fixed-factor-clock";
 458                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 459                         #clock-cells = <0>;
 460                         clock-div = <2>;
 461                         clock-mult = <1>;
 462                         clock-output-names = "i";
 463                 };
 464                 b_clk: b_clk {
 465                         compatible = "fixed-factor-clock";
 466                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 467                         #clock-cells = <0>;
 468                         clock-div = <12>;
 469                         clock-mult = <1>;
 470                         clock-output-names = "b";
 471                 };
 472                 p_clk: p_clk {
 473                         compatible = "fixed-factor-clock";
 474                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 475                         #clock-cells = <0>;
 476                         clock-div = <24>;
 477                         clock-mult = <1>;
 478                         clock-output-names = "p";
 479                 };
 480                 cl_clk: cl_clk {
 481                         compatible = "fixed-factor-clock";
 482                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 483                         #clock-cells = <0>;
 484                         clock-div = <48>;
 485                         clock-mult = <1>;
 486                         clock-output-names = "cl";
 487                 };
 488                 m2_clk: m2_clk {
 489                         compatible = "fixed-factor-clock";
 490                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 491                         #clock-cells = <0>;
 492                         clock-div = <8>;
 493                         clock-mult = <1>;
 494                         clock-output-names = "m2";
 495                 };
 496                 imp_clk: imp_clk {
 497                         compatible = "fixed-factor-clock";
 498                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 499                         #clock-cells = <0>;
 500                         clock-div = <4>;
 501                         clock-mult = <1>;
 502                         clock-output-names = "imp";
 503                 };
 504                 rclk_clk: rclk_clk {
 505                         compatible = "fixed-factor-clock";
 506                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 507                         #clock-cells = <0>;
 508                         clock-div = <(48 * 1024)>;
 509                         clock-mult = <1>;
 510                         clock-output-names = "rclk";
 511                 };
 512                 oscclk_clk: oscclk_clk {
 513                         compatible = "fixed-factor-clock";
 514                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 515                         #clock-cells = <0>;
 516                         clock-div = <(12 * 1024)>;
 517                         clock-mult = <1>;
 518                         clock-output-names = "oscclk";
 519                 };
 520                 zb3_clk: zb3_clk {
 521                         compatible = "fixed-factor-clock";
 522                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 523                         #clock-cells = <0>;
 524                         clock-div = <4>;
 525                         clock-mult = <1>;
 526                         clock-output-names = "zb3";
 527                 };
 528                 zb3d2_clk: zb3d2_clk {
 529                         compatible = "fixed-factor-clock";
 530                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 531                         #clock-cells = <0>;
 532                         clock-div = <8>;
 533                         clock-mult = <1>;
 534                         clock-output-names = "zb3d2";
 535                 };
 536                 ddr_clk: ddr_clk {
 537                         compatible = "fixed-factor-clock";
 538                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 539                         #clock-cells = <0>;
 540                         clock-div = <8>;
 541                         clock-mult = <1>;
 542                         clock-output-names = "ddr";
 543                 };
 544                 mp_clk: mp_clk {
 545                         compatible = "fixed-factor-clock";
 546                         clocks = <&pll1_div2_clk>;
 547                         #clock-cells = <0>;
 548                         clock-div = <15>;
 549                         clock-mult = <1>;
 550                         clock-output-names = "mp";
 551                 };
 552                 cp_clk: cp_clk {
 553                         compatible = "fixed-factor-clock";
 554                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 555                         #clock-cells = <0>;
 556                         clock-div = <48>;
 557                         clock-mult = <1>;
 558                         clock-output-names = "cp";
 559                 };
 560
 561                 acp_clk: acp_clk {
 562                         compatible = "fixed-factor-clock";
 563                         clocks = <&extal_clk>;
 564                         #clock-cells = <0>;
 565                         clock-div = <2>;
 566                         clock-mult = <1>;
 567                         clock-output-names = "acp";
 568                 };
 569
 570                 /* Gate clocks */
 571                 mstp0_clks: mstp0_clks@e6150130 {
 572                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 573                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 574                         clocks = <&mp_clk>;
 575                         #clock-cells = <1>;
 576                         clock-indices = <R8A7794_CLK_MSIOF0>;
 577                         clock-output-names = "msiof0";
 578                 };
 579                 mstp1_clks: mstp1_clks@e6150134 {
 580                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 581                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 582                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
 583                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 584                                  <&zs_clk>, <&zs_clk>;
 585                         #clock-cells = <1>;
 586                         clock-indices = <
 587                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
 588                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
 589                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
 590                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
 591                         >;
 592                         clock-output-names =
 593                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
 594                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
 595                 };
 596                 mstp2_clks: mstp2_clks@e6150138 {
 597                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 598                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 599                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 600                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 601                                  <&zs_clk>, <&zs_clk>;
 602                         #clock-cells = <1>;
 603                         clock-indices = <
 604                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
 605                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
 606                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
 607                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
 608                         >;
 609                         clock-output-names =
 610                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 611                                 "scifb1", "msiof1", "scifb2",
 612                                 "sys-dmac1", "sys-dmac0";
 613                 };
 614                 mstp3_clks: mstp3_clks@e615013c {
 615                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 616                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 617                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
 618                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 619                         #clock-cells = <1>;
 620                         clock-indices = <
 621                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
 622                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
 623                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
 624                         >;
 625                         clock-output-names =
 626                                 "sdhi2", "sdhi1", "sdhi0",
 627                                 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
 628                 };
 629                 mstp4_clks: mstp4_clks@e6150140 {
 630                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 631                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 632                         clocks = <&cp_clk>;
 633                         #clock-cells = <1>;
 634                         clock-indices = <R8A7794_CLK_IRQC>;
 635                         clock-output-names = "irqc";
 636                 };
 637                 mstp7_clks: mstp7_clks@e615014c {
 638                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 639                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 640                         clocks = <&mp_clk>, <&mp_clk>,
 641                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 642                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 643                         #clock-cells = <1>;
 644                         clock-indices = <
 645                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
 646                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
 647                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
 648                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
 649                                 R8A7794_CLK_SCIF0
 650                         >;
 651                         clock-output-names =
 652                                 "ehci", "hsusb",
 653                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 654                                 "scif3", "scif2", "scif1", "scif0";
 655                 };
 656                 mstp8_clks: mstp8_clks@e6150990 {
 657                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 658                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 659                         clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
 660                         #clock-cells = <1>;
 661                         clock-indices = <
 662                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
 663                         >;
 664                         clock-output-names =
 665                                 "vin1", "vin0", "ether";
 666                 };
 667                 mstp9_clks: mstp9_clks@e6150994 {
 668                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 669                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 670                         clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
 671                                 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 672                         #clock-cells = <1>;
 673                         clock-indices = <
 674                                 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
 675                                 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
 676                                 R8A7794_CLK_I2C0
 677                         >;
 678                         clock-output-names =
 679                                 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
 680                 };
 681                 mstp11_clks: mstp11_clks@e615099c {
 682                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 683                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 684                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 685                         #clock-cells = <1>;
 686                         clock-indices = <
 687                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
 688                         >;
 689                         clock-output-names = "scifa3", "scifa4", "scifa5";
 690                 };
 691         };
 692
 693         ipmmu_sy0: mmu@e6280000 {
 694                 compatible = "renesas,ipmmu-vmsa";
 695                 reg = <0 0xe6280000 0 0x1000>;
 696                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
 697                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
 698                 #iommu-cells = <1>;
 699                 status = "disabled";
 700         };
 701
 702         ipmmu_sy1: mmu@e6290000 {
 703                 compatible = "renesas,ipmmu-vmsa";
 704                 reg = <0 0xe6290000 0 0x1000>;
 705                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 706                 #iommu-cells = <1>;
 707                 status = "disabled";
 708         };
 709
 710         ipmmu_ds: mmu@e6740000 {
 711                 compatible = "renesas,ipmmu-vmsa";
 712                 reg = <0 0xe6740000 0 0x1000>;
 713                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 714                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
 715                 #iommu-cells = <1>;
 716         };
 717
 718         ipmmu_mp: mmu@ec680000 {
 719                 compatible = "renesas,ipmmu-vmsa";
 720                 reg = <0 0xec680000 0 0x1000>;
 721                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
 722                 #iommu-cells = <1>;
 723                 status = "disabled";
 724         };
 725
 726         ipmmu_mx: mmu@fe951000 {
 727                 compatible = "renesas,ipmmu-vmsa";
 728                 reg = <0 0xfe951000 0 0x1000>;
 729                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 730                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
 731                 #iommu-cells = <1>;
 732         };
 733
 734         ipmmu_gp: mmu@e62a0000 {
 735                 compatible = "renesas,ipmmu-vmsa";
 736                 reg = <0 0xe62a0000 0 0x1000>;
 737                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
 738                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
 739                 #iommu-cells = <1>;
 740                 status = "disabled";
 741         };
 742 };