2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include "skeleton.dtsi"
21 compatible = "rockchip,rk3288";
23 interrupt-parent = <&gic>;
52 compatible = "arm,cortex-a12";
69 clock-latency = <40000>;
70 clocks = <&cru ARMCLK>;
74 compatible = "arm,cortex-a12";
79 compatible = "arm,cortex-a12";
84 compatible = "arm,cortex-a12";
90 compatible = "arm,amba-bus";
95 dmac_peri: dma-controller@ff250000 {
96 compatible = "arm,pl330", "arm,primecell";
97 reg = <0xff250000 0x4000>;
98 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cru ACLK_DMAC2>;
102 clock-names = "apb_pclk";
105 dmac_bus_ns: dma-controller@ff600000 {
106 compatible = "arm,pl330", "arm,primecell";
107 reg = <0xff600000 0x4000>;
108 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&cru ACLK_DMAC1>;
112 clock-names = "apb_pclk";
116 dmac_bus_s: dma-controller@ffb20000 {
117 compatible = "arm,pl330", "arm,primecell";
118 reg = <0xffb20000 0x4000>;
119 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&cru ACLK_DMAC1>;
123 clock-names = "apb_pclk";
128 compatible = "fixed-clock";
129 clock-frequency = <24000000>;
130 clock-output-names = "xin24m";
135 compatible = "arm,armv7-timer";
136 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
137 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
138 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
139 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
140 clock-frequency = <24000000>;
143 sdmmc: dwmmc@ff0c0000 {
144 compatible = "rockchip,rk3288-dw-mshc";
145 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
146 clock-names = "biu", "ciu";
147 fifo-depth = <0x100>;
148 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0xff0c0000 0x4000>;
153 sdio0: dwmmc@ff0d0000 {
154 compatible = "rockchip,rk3288-dw-mshc";
155 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
156 clock-names = "biu", "ciu";
157 fifo-depth = <0x100>;
158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
159 reg = <0xff0d0000 0x4000>;
163 sdio1: dwmmc@ff0e0000 {
164 compatible = "rockchip,rk3288-dw-mshc";
165 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
166 clock-names = "biu", "ciu";
167 fifo-depth = <0x100>;
168 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
169 reg = <0xff0e0000 0x4000>;
173 emmc: dwmmc@ff0f0000 {
174 compatible = "rockchip,rk3288-dw-mshc";
175 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
176 clock-names = "biu", "ciu";
177 fifo-depth = <0x100>;
178 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
179 reg = <0xff0f0000 0x4000>;
183 saradc: saradc@ff100000 {
184 compatible = "rockchip,saradc";
185 reg = <0xff100000 0x100>;
186 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
187 #io-channel-cells = <1>;
188 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
189 clock-names = "saradc", "apb_pclk";
194 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
195 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
196 clock-names = "spiclk", "apb_pclk";
197 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
198 dma-names = "tx", "rx";
199 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
202 reg = <0xff110000 0x1000>;
203 #address-cells = <1>;
209 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
210 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
211 clock-names = "spiclk", "apb_pclk";
212 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
213 dma-names = "tx", "rx";
214 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
217 reg = <0xff120000 0x1000>;
218 #address-cells = <1>;
224 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
225 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
226 clock-names = "spiclk", "apb_pclk";
227 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
228 dma-names = "tx", "rx";
229 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
232 reg = <0xff130000 0x1000>;
233 #address-cells = <1>;
239 compatible = "rockchip,rk3288-i2c";
240 reg = <0xff140000 0x1000>;
241 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
242 #address-cells = <1>;
245 clocks = <&cru PCLK_I2C1>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&i2c1_xfer>;
252 compatible = "rockchip,rk3288-i2c";
253 reg = <0xff150000 0x1000>;
254 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
258 clocks = <&cru PCLK_I2C3>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&i2c3_xfer>;
265 compatible = "rockchip,rk3288-i2c";
266 reg = <0xff160000 0x1000>;
267 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
271 clocks = <&cru PCLK_I2C4>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c4_xfer>;
278 compatible = "rockchip,rk3288-i2c";
279 reg = <0xff170000 0x1000>;
280 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
284 clocks = <&cru PCLK_I2C5>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c5_xfer>;
290 uart0: serial@ff180000 {
291 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
292 reg = <0xff180000 0x100>;
293 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
297 clock-names = "baudclk", "apb_pclk";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart0_xfer>;
303 uart1: serial@ff190000 {
304 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
305 reg = <0xff190000 0x100>;
306 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart1_xfer>;
316 uart2: serial@ff690000 {
317 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
318 reg = <0xff690000 0x100>;
319 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
323 clock-names = "baudclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart2_xfer>;
329 uart3: serial@ff1b0000 {
330 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
331 reg = <0xff1b0000 0x100>;
332 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
336 clock-names = "baudclk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart3_xfer>;
342 uart4: serial@ff1c0000 {
343 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
344 reg = <0xff1c0000 0x100>;
345 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
349 clock-names = "baudclk", "apb_pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart4_xfer>;
355 usb_host0_ehci: usb@ff500000 {
356 compatible = "generic-ehci";
357 reg = <0xff500000 0x100>;
358 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cru HCLK_USBHOST0>;
360 clock-names = "usbhost";
364 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
366 usb_host1: usb@ff540000 {
367 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
369 reg = <0xff540000 0x40000>;
370 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cru HCLK_USBHOST1>;
376 usb_otg: usb@ff580000 {
377 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
379 reg = <0xff580000 0x40000>;
380 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cru HCLK_OTG0>;
386 usb_hsic: usb@ff5c0000 {
387 compatible = "generic-ehci";
388 reg = <0xff5c0000 0x100>;
389 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru HCLK_HSIC>;
391 clock-names = "usbhost";
396 compatible = "rockchip,rk3288-i2c";
397 reg = <0xff650000 0x1000>;
398 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
399 #address-cells = <1>;
402 clocks = <&cru PCLK_I2C0>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c0_xfer>;
409 compatible = "rockchip,rk3288-i2c";
410 reg = <0xff660000 0x1000>;
411 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
415 clocks = <&cru PCLK_I2C2>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c2_xfer>;
422 compatible = "rockchip,rk3288-pwm";
423 reg = <0xff680000 0x10>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pwm0_pin>;
427 clocks = <&cru PCLK_PWM>;
433 compatible = "rockchip,rk3288-pwm";
434 reg = <0xff680010 0x10>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pwm1_pin>;
438 clocks = <&cru PCLK_PWM>;
444 compatible = "rockchip,rk3288-pwm";
445 reg = <0xff680020 0x10>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pwm2_pin>;
449 clocks = <&cru PCLK_PWM>;
455 compatible = "rockchip,rk3288-pwm";
456 reg = <0xff680030 0x10>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pwm3_pin>;
460 clocks = <&cru PCLK_PWM>;
465 pmu: power-management@ff730000 {
466 compatible = "rockchip,rk3288-pmu", "syscon";
467 reg = <0xff730000 0x100>;
470 sgrf: syscon@ff740000 {
471 compatible = "rockchip,rk3288-sgrf", "syscon";
472 reg = <0xff740000 0x1000>;
475 cru: clock-controller@ff760000 {
476 compatible = "rockchip,rk3288-cru";
477 reg = <0xff760000 0x1000>;
478 rockchip,grf = <&grf>;
481 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
482 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
483 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
484 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
486 assigned-clock-rates = <594000000>, <400000000>,
487 <500000000>, <300000000>,
488 <150000000>, <75000000>,
489 <300000000>, <150000000>,
493 grf: syscon@ff770000 {
494 compatible = "rockchip,rk3288-grf", "syscon";
495 reg = <0xff770000 0x1000>;
498 wdt: watchdog@ff800000 {
499 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
500 reg = <0xff800000 0x100>;
501 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
506 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
507 reg = <0xff890000 0x10000>;
508 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
511 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
512 dma-names = "tx", "rx";
513 clock-names = "i2s_hclk", "i2s_clk";
514 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&i2s0_bus>;
520 gic: interrupt-controller@ffc01000 {
521 compatible = "arm,gic-400";
522 interrupt-controller;
523 #interrupt-cells = <3>;
524 #address-cells = <0>;
526 reg = <0xffc01000 0x1000>,
530 interrupts = <GIC_PPI 9 0xf04>;
534 compatible = "rockchip,rk3288-pinctrl";
535 rockchip,grf = <&grf>;
536 rockchip,pmu = <&pmu>;
537 #address-cells = <1>;
541 gpio0: gpio0@ff750000 {
542 compatible = "rockchip,gpio-bank";
543 reg = <0xff750000 0x100>;
544 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cru PCLK_GPIO0>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
554 gpio1: gpio1@ff780000 {
555 compatible = "rockchip,gpio-bank";
556 reg = <0xff780000 0x100>;
557 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cru PCLK_GPIO1>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
567 gpio2: gpio2@ff790000 {
568 compatible = "rockchip,gpio-bank";
569 reg = <0xff790000 0x100>;
570 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cru PCLK_GPIO2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
580 gpio3: gpio3@ff7a0000 {
581 compatible = "rockchip,gpio-bank";
582 reg = <0xff7a0000 0x100>;
583 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru PCLK_GPIO3>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
593 gpio4: gpio4@ff7b0000 {
594 compatible = "rockchip,gpio-bank";
595 reg = <0xff7b0000 0x100>;
596 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru PCLK_GPIO4>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
606 gpio5: gpio5@ff7c0000 {
607 compatible = "rockchip,gpio-bank";
608 reg = <0xff7c0000 0x100>;
609 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cru PCLK_GPIO5>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
619 gpio6: gpio6@ff7d0000 {
620 compatible = "rockchip,gpio-bank";
621 reg = <0xff7d0000 0x100>;
622 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&cru PCLK_GPIO6>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
632 gpio7: gpio7@ff7e0000 {
633 compatible = "rockchip,gpio-bank";
634 reg = <0xff7e0000 0x100>;
635 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&cru PCLK_GPIO7>;
641 interrupt-controller;
642 #interrupt-cells = <2>;
645 gpio8: gpio8@ff7f0000 {
646 compatible = "rockchip,gpio-bank";
647 reg = <0xff7f0000 0x100>;
648 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru PCLK_GPIO8>;
654 interrupt-controller;
655 #interrupt-cells = <2>;
658 pcfg_pull_up: pcfg-pull-up {
662 pcfg_pull_down: pcfg-pull-down {
666 pcfg_pull_none: pcfg-pull-none {
671 i2c0_xfer: i2c0-xfer {
672 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
673 <0 16 RK_FUNC_1 &pcfg_pull_none>;
678 i2c1_xfer: i2c1-xfer {
679 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
680 <8 5 RK_FUNC_1 &pcfg_pull_none>;
685 i2c2_xfer: i2c2-xfer {
686 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
687 <6 10 RK_FUNC_1 &pcfg_pull_none>;
692 i2c3_xfer: i2c3-xfer {
693 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
694 <2 17 RK_FUNC_1 &pcfg_pull_none>;
699 i2c4_xfer: i2c4-xfer {
700 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
701 <7 18 RK_FUNC_1 &pcfg_pull_none>;
706 i2c5_xfer: i2c5-xfer {
707 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
708 <7 20 RK_FUNC_1 &pcfg_pull_none>;
714 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
715 <6 1 RK_FUNC_1 &pcfg_pull_none>,
716 <6 2 RK_FUNC_1 &pcfg_pull_none>,
717 <6 3 RK_FUNC_1 &pcfg_pull_none>,
718 <6 4 RK_FUNC_1 &pcfg_pull_none>,
719 <6 8 RK_FUNC_1 &pcfg_pull_none>;
724 sdmmc_clk: sdmmc-clk {
725 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
728 sdmmc_cmd: sdmmc-cmd {
729 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
733 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
736 sdmmc_bus1: sdmmc-bus1 {
737 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
740 sdmmc_bus4: sdmmc-bus4 {
741 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
742 <6 17 RK_FUNC_1 &pcfg_pull_up>,
743 <6 18 RK_FUNC_1 &pcfg_pull_up>,
744 <6 19 RK_FUNC_1 &pcfg_pull_up>;
749 sdio0_bus1: sdio0-bus1 {
750 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
753 sdio0_bus4: sdio0-bus4 {
754 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
755 <4 21 RK_FUNC_1 &pcfg_pull_up>,
756 <4 22 RK_FUNC_1 &pcfg_pull_up>,
757 <4 23 RK_FUNC_1 &pcfg_pull_up>;
760 sdio0_cmd: sdio0-cmd {
761 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
764 sdio0_clk: sdio0-clk {
765 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
769 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
773 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
776 sdio0_pwr: sdio0-pwr {
777 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
780 sdio0_bkpwr: sdio0-bkpwr {
781 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
784 sdio0_int: sdio0-int {
785 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
790 sdio1_bus1: sdio1-bus1 {
791 rockchip,pins = <3 24 4 &pcfg_pull_up>;
794 sdio1_bus4: sdio1-bus4 {
795 rockchip,pins = <3 24 4 &pcfg_pull_up>,
796 <3 25 4 &pcfg_pull_up>,
797 <3 26 4 &pcfg_pull_up>,
798 <3 27 4 &pcfg_pull_up>;
802 rockchip,pins = <3 28 4 &pcfg_pull_up>;
806 rockchip,pins = <3 29 4 &pcfg_pull_up>;
809 sdio1_bkpwr: sdio1-bkpwr {
810 rockchip,pins = <3 30 4 &pcfg_pull_up>;
813 sdio1_int: sdio1-int {
814 rockchip,pins = <3 31 4 &pcfg_pull_up>;
817 sdio1_cmd: sdio1-cmd {
818 rockchip,pins = <4 6 4 &pcfg_pull_up>;
821 sdio1_clk: sdio1-clk {
822 rockchip,pins = <4 7 4 &pcfg_pull_none>;
825 sdio1_pwr: sdio1-pwr {
826 rockchip,pins = <4 9 4 &pcfg_pull_up>;
832 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
836 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
840 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
843 emmc_bus1: emmc-bus1 {
844 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
847 emmc_bus4: emmc-bus4 {
848 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
849 <3 1 RK_FUNC_2 &pcfg_pull_up>,
850 <3 2 RK_FUNC_2 &pcfg_pull_up>,
851 <3 3 RK_FUNC_2 &pcfg_pull_up>;
854 emmc_bus8: emmc-bus8 {
855 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
856 <3 1 RK_FUNC_2 &pcfg_pull_up>,
857 <3 2 RK_FUNC_2 &pcfg_pull_up>,
858 <3 3 RK_FUNC_2 &pcfg_pull_up>,
859 <3 4 RK_FUNC_2 &pcfg_pull_up>,
860 <3 5 RK_FUNC_2 &pcfg_pull_up>,
861 <3 6 RK_FUNC_2 &pcfg_pull_up>,
862 <3 7 RK_FUNC_2 &pcfg_pull_up>;
868 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
871 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
874 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
877 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
880 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
885 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
888 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
891 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
894 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
900 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
903 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
906 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
909 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
912 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
917 uart0_xfer: uart0-xfer {
918 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
919 <4 17 RK_FUNC_1 &pcfg_pull_none>;
922 uart0_cts: uart0-cts {
923 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
926 uart0_rts: uart0-rts {
927 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
932 uart1_xfer: uart1-xfer {
933 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
934 <5 9 RK_FUNC_1 &pcfg_pull_none>;
937 uart1_cts: uart1-cts {
938 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
941 uart1_rts: uart1-rts {
942 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
947 uart2_xfer: uart2-xfer {
948 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
949 <7 23 RK_FUNC_1 &pcfg_pull_none>;
951 /* no rts / cts for uart2 */
955 uart3_xfer: uart3-xfer {
956 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
957 <7 8 RK_FUNC_1 &pcfg_pull_none>;
960 uart3_cts: uart3-cts {
961 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
964 uart3_rts: uart3-rts {
965 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
970 uart4_xfer: uart4-xfer {
971 rockchip,pins = <5 12 3 &pcfg_pull_up>,
972 <5 13 3 &pcfg_pull_none>;
975 uart4_cts: uart4-cts {
976 rockchip,pins = <5 14 3 &pcfg_pull_none>;
979 uart4_rts: uart4-rts {
980 rockchip,pins = <5 15 3 &pcfg_pull_none>;
986 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
992 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
998 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1003 pwm3_pin: pwm3-pin {
1004 rockchip,pins = <7 23 3 &pcfg_pull_none>;