2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a12-pmu";
78 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 enable-method = "rockchip,rk3066-smp";
89 rockchip,pmu = <&pmu>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE0>;
111 #cooling-cells = <2>; /* min followed by max */
112 clock-latency = <40000>;
113 clocks = <&cru ARMCLK>;
117 compatible = "arm,cortex-a12";
119 resets = <&cru SRST_CORE1>;
123 compatible = "arm,cortex-a12";
125 resets = <&cru SRST_CORE2>;
129 compatible = "arm,cortex-a12";
131 resets = <&cru SRST_CORE3>;
136 compatible = "arm,amba-bus";
137 #address-cells = <1>;
141 dmac_peri: dma-controller@ff250000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0xff250000 0x4000>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&cru ACLK_DMAC2>;
148 clock-names = "apb_pclk";
151 dmac_bus_ns: dma-controller@ff600000 {
152 compatible = "arm,pl330", "arm,primecell";
153 reg = <0xff600000 0x4000>;
154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&cru ACLK_DMAC1>;
158 clock-names = "apb_pclk";
162 dmac_bus_s: dma-controller@ffb20000 {
163 compatible = "arm,pl330", "arm,primecell";
164 reg = <0xffb20000 0x4000>;
165 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cru ACLK_DMAC1>;
169 clock-names = "apb_pclk";
174 #address-cells = <1>;
179 * The rk3288 cannot use the memory area above 0xfe000000
180 * for dma operations for some reason. While there is
181 * probably a better solution available somewhere, we
182 * haven't found it yet and while devices with 2GB of ram
183 * are not affected, this issue prevents 4GB from booting.
184 * So to make these devices at least bootable, block
185 * this area for the time being until the real solution
188 dma-unusable@fe000000 {
189 reg = <0xfe000000 0x1000000>;
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
201 compatible = "arm,armv7-timer";
202 arm,cpu-registers-not-fw-configured;
203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
207 clock-frequency = <24000000>;
210 timer: timer@ff810000 {
211 compatible = "rockchip,rk3288-timer";
212 reg = <0xff810000 0x20>;
213 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&xin24m>, <&cru PCLK_TIMER>;
215 clock-names = "timer", "pclk";
219 compatible = "rockchip,display-subsystem";
220 ports = <&vopl_out>, <&vopb_out>;
223 sdmmc: dwmmc@ff0c0000 {
224 compatible = "rockchip,rk3288-dw-mshc";
225 clock-freq-min-max = <400000 150000000>;
226 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
227 clock-names = "biu", "ciu";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0xff0c0000 0x4000>;
234 sdio0: dwmmc@ff0d0000 {
235 compatible = "rockchip,rk3288-dw-mshc";
236 clock-freq-min-max = <400000 150000000>;
237 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
238 clock-names = "biu", "ciu";
239 fifo-depth = <0x100>;
240 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
241 reg = <0xff0d0000 0x4000>;
245 sdio1: dwmmc@ff0e0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 clock-freq-min-max = <400000 150000000>;
248 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
249 clock-names = "biu", "ciu";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
252 reg = <0xff0e0000 0x4000>;
256 emmc: dwmmc@ff0f0000 {
257 compatible = "rockchip,rk3288-dw-mshc";
258 clock-freq-min-max = <400000 150000000>;
259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
260 clock-names = "biu", "ciu";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0xff0f0000 0x4000>;
267 saradc: saradc@ff100000 {
268 compatible = "rockchip,saradc";
269 reg = <0xff100000 0x100>;
270 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";
278 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
279 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
280 clock-names = "spiclk", "apb_pclk";
281 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
282 dma-names = "tx", "rx";
283 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
286 reg = <0xff110000 0x1000>;
287 #address-cells = <1>;
293 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
294 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
295 clock-names = "spiclk", "apb_pclk";
296 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
297 dma-names = "tx", "rx";
298 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
301 reg = <0xff120000 0x1000>;
302 #address-cells = <1>;
308 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
309 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
310 clock-names = "spiclk", "apb_pclk";
311 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
312 dma-names = "tx", "rx";
313 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
316 reg = <0xff130000 0x1000>;
317 #address-cells = <1>;
323 compatible = "rockchip,rk3288-i2c";
324 reg = <0xff140000 0x1000>;
325 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
329 clocks = <&cru PCLK_I2C1>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c1_xfer>;
336 compatible = "rockchip,rk3288-i2c";
337 reg = <0xff150000 0x1000>;
338 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
342 clocks = <&cru PCLK_I2C3>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c3_xfer>;
349 compatible = "rockchip,rk3288-i2c";
350 reg = <0xff160000 0x1000>;
351 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
355 clocks = <&cru PCLK_I2C4>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c4_xfer>;
362 compatible = "rockchip,rk3288-i2c";
363 reg = <0xff170000 0x1000>;
364 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
368 clocks = <&cru PCLK_I2C5>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c5_xfer>;
374 uart0: serial@ff180000 {
375 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
376 reg = <0xff180000 0x100>;
377 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
381 clock-names = "baudclk", "apb_pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&uart0_xfer>;
387 uart1: serial@ff190000 {
388 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
389 reg = <0xff190000 0x100>;
390 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
394 clock-names = "baudclk", "apb_pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart1_xfer>;
400 uart2: serial@ff690000 {
401 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
402 reg = <0xff690000 0x100>;
403 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
407 clock-names = "baudclk", "apb_pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&uart2_xfer>;
413 uart3: serial@ff1b0000 {
414 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
415 reg = <0xff1b0000 0x100>;
416 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
420 clock-names = "baudclk", "apb_pclk";
421 pinctrl-names = "default";
422 pinctrl-0 = <&uart3_xfer>;
426 uart4: serial@ff1c0000 {
427 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
428 reg = <0xff1c0000 0x100>;
429 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
433 clock-names = "baudclk", "apb_pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&uart4_xfer>;
440 #include "rk3288-thermal.dtsi"
443 tsadc: tsadc@ff280000 {
444 compatible = "rockchip,rk3288-tsadc";
445 reg = <0xff280000 0x100>;
446 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
448 clock-names = "tsadc", "apb_pclk";
449 resets = <&cru SRST_TSADC>;
450 reset-names = "tsadc-apb";
451 pinctrl-names = "default";
452 pinctrl-0 = <&otp_out>;
453 #thermal-sensor-cells = <1>;
454 rockchip,hw-tshut-temp = <95000>;
458 gmac: ethernet@ff290000 {
459 compatible = "rockchip,rk3288-gmac";
460 reg = <0xff290000 0x10000>;
461 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "macirq";
463 rockchip,grf = <&grf>;
464 clocks = <&cru SCLK_MAC>,
465 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
466 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
467 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
468 clock-names = "stmmaceth",
469 "mac_clk_rx", "mac_clk_tx",
470 "clk_mac_ref", "clk_mac_refout",
471 "aclk_mac", "pclk_mac";
472 resets = <&cru SRST_MAC>;
473 reset-names = "stmmaceth";
477 usb_host0_ehci: usb@ff500000 {
478 compatible = "generic-ehci";
479 reg = <0xff500000 0x100>;
480 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_USBHOST0>;
482 clock-names = "usbhost";
488 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
490 usb_host1: usb@ff540000 {
491 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
493 reg = <0xff540000 0x40000>;
494 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cru HCLK_USBHOST1>;
499 phy-names = "usb2-phy";
503 usb_otg: usb@ff580000 {
504 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
506 reg = <0xff580000 0x40000>;
507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru HCLK_OTG0>;
511 g-np-tx-fifo-size = <16>;
512 g-rx-fifo-size = <275>;
513 g-tx-fifo-size = <256 128 128 64 64 32>;
516 phy-names = "usb2-phy";
520 usb_hsic: usb@ff5c0000 {
521 compatible = "generic-ehci";
522 reg = <0xff5c0000 0x100>;
523 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_HSIC>;
525 clock-names = "usbhost";
530 compatible = "rockchip,rk3288-i2c";
531 reg = <0xff650000 0x1000>;
532 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
536 clocks = <&cru PCLK_I2C0>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c0_xfer>;
543 compatible = "rockchip,rk3288-i2c";
544 reg = <0xff660000 0x1000>;
545 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
549 clocks = <&cru PCLK_I2C2>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c2_xfer>;
556 compatible = "rockchip,rk3288-pwm";
557 reg = <0xff680000 0x10>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm0_pin>;
561 clocks = <&cru PCLK_PWM>;
567 compatible = "rockchip,rk3288-pwm";
568 reg = <0xff680010 0x10>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pwm1_pin>;
572 clocks = <&cru PCLK_PWM>;
578 compatible = "rockchip,rk3288-pwm";
579 reg = <0xff680020 0x10>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pwm2_pin>;
583 clocks = <&cru PCLK_PWM>;
589 compatible = "rockchip,rk3288-pwm";
590 reg = <0xff680030 0x10>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&pwm3_pin>;
594 clocks = <&cru PCLK_PWM>;
599 bus_intmem@ff700000 {
600 compatible = "mmio-sram";
601 reg = <0xff700000 0x18000>;
602 #address-cells = <1>;
604 ranges = <0 0xff700000 0x18000>;
606 compatible = "rockchip,rk3066-smp-sram";
612 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
613 reg = <0xff720000 0x1000>;
616 pmu: power-management@ff730000 {
617 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
618 reg = <0xff730000 0x100>;
620 power: power-controller {
621 compatible = "rockchip,rk3288-power-controller";
622 #power-domain-cells = <1>;
623 #address-cells = <1>;
627 * Note: Although SCLK_* are the working clocks
628 * of device without including on the NOC, needed for
631 * The clocks on the which NOC:
632 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
633 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
634 * ACLK_RGA is on ACLK_RGA_NIU.
635 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
637 * Which clock are device clocks:
639 * *_IEP IEP:Image Enhancement Processor
640 * *_ISP ISP:Image Signal Processing
641 * *_VIP VIP:Video Input Processor
642 * *_VOP* VOP:Visual Output Processor
650 reg = <RK3288_PD_VIO>;
651 clocks = <&cru ACLK_IEP>,
665 <&cru PCLK_EDP_CTRL>,
666 <&cru PCLK_HDMI_CTRL>,
667 <&cru PCLK_LVDS_PHY>,
668 <&cru PCLK_MIPI_CSI>,
669 <&cru PCLK_MIPI_DSI0>,
670 <&cru PCLK_MIPI_DSI1>,
679 * Note: The following 3 are HEVC(H.265) clocks,
680 * and on the ACLK_HEVC_NIU (NOC).
683 reg = <RK3288_PD_HEVC>;
684 clocks = <&cru ACLK_HEVC>,
685 <&cru SCLK_HEVC_CABAC>,
686 <&cru SCLK_HEVC_CORE>;
690 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
691 * (video endecoder & decoder) clocks that on the
692 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
695 reg = <RK3288_PD_VIDEO>;
696 clocks = <&cru ACLK_VCODEC>,
701 * Note: ACLK_GPU is the GPU clock,
702 * and on the ACLK_GPU_NIU (NOC).
705 reg = <RK3288_PD_GPU>;
706 clocks = <&cru ACLK_GPU>;
711 sgrf: syscon@ff740000 {
712 compatible = "rockchip,rk3288-sgrf", "syscon";
713 reg = <0xff740000 0x1000>;
716 cru: clock-controller@ff760000 {
717 compatible = "rockchip,rk3288-cru";
718 reg = <0xff760000 0x1000>;
719 rockchip,grf = <&grf>;
722 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
723 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
724 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
725 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
727 assigned-clock-rates = <594000000>, <400000000>,
728 <500000000>, <300000000>,
729 <150000000>, <75000000>,
730 <300000000>, <150000000>,
734 grf: syscon@ff770000 {
735 compatible = "rockchip,rk3288-grf", "syscon";
736 reg = <0xff770000 0x1000>;
739 wdt: watchdog@ff800000 {
740 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
741 reg = <0xff800000 0x100>;
742 clocks = <&cru PCLK_WDT>;
743 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
747 spdif: sound@ff88b0000 {
748 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
749 reg = <0xff8b0000 0x10000>;
750 #sound-dai-cells = <0>;
751 clock-names = "hclk", "mclk";
752 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
753 dmas = <&dmac_bus_s 3>;
755 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&spdif_tx>;
758 rockchip,grf = <&grf>;
763 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
764 reg = <0xff890000 0x10000>;
765 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
766 #address-cells = <1>;
768 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
769 dma-names = "tx", "rx";
770 clock-names = "i2s_hclk", "i2s_clk";
771 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
772 pinctrl-names = "default";
773 pinctrl-0 = <&i2s0_bus>;
778 compatible = "rockchip,rk3288-vop";
779 reg = <0xff930000 0x19c>;
780 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
782 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
783 power-domains = <&power RK3288_PD_VIO>;
784 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
785 reset-names = "axi", "ahb", "dclk";
786 iommus = <&vopb_mmu>;
790 #address-cells = <1>;
793 vopb_out_hdmi: endpoint@0 {
795 remote-endpoint = <&hdmi_in_vopb>;
800 vopb_mmu: iommu@ff930300 {
801 compatible = "rockchip,iommu";
802 reg = <0xff930300 0x100>;
803 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
804 interrupt-names = "vopb_mmu";
805 power-domains = <&power RK3288_PD_VIO>;
811 compatible = "rockchip,rk3288-vop";
812 reg = <0xff940000 0x19c>;
813 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
815 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
816 power-domains = <&power RK3288_PD_VIO>;
817 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
818 reset-names = "axi", "ahb", "dclk";
819 iommus = <&vopl_mmu>;
823 #address-cells = <1>;
826 vopl_out_hdmi: endpoint@0 {
828 remote-endpoint = <&hdmi_in_vopl>;
833 vopl_mmu: iommu@ff940300 {
834 compatible = "rockchip,iommu";
835 reg = <0xff940300 0x100>;
836 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
837 interrupt-names = "vopl_mmu";
838 power-domains = <&power RK3288_PD_VIO>;
843 hdmi: hdmi@ff980000 {
844 compatible = "rockchip,rk3288-dw-hdmi";
845 reg = <0xff980000 0x20000>;
847 rockchip,grf = <&grf>;
848 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
850 clock-names = "iahb", "isfr";
851 power-domains = <&power RK3288_PD_VIO>;
856 #address-cells = <1>;
858 hdmi_in_vopb: endpoint@0 {
860 remote-endpoint = <&vopb_out_hdmi>;
862 hdmi_in_vopl: endpoint@1 {
864 remote-endpoint = <&vopl_out_hdmi>;
870 gic: interrupt-controller@ffc01000 {
871 compatible = "arm,gic-400";
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 #address-cells = <0>;
876 reg = <0xffc01000 0x1000>,
880 interrupts = <GIC_PPI 9 0xf04>;
884 compatible = "rockchip,rk3288-usb-phy";
885 rockchip,grf = <&grf>;
886 #address-cells = <1>;
893 clocks = <&cru SCLK_OTGPHY0>;
894 clock-names = "phyclk";
900 clocks = <&cru SCLK_OTGPHY1>;
901 clock-names = "phyclk";
907 clocks = <&cru SCLK_OTGPHY2>;
908 clock-names = "phyclk";
913 compatible = "rockchip,rk3288-pinctrl";
914 rockchip,grf = <&grf>;
915 rockchip,pmu = <&pmu>;
916 #address-cells = <1>;
920 gpio0: gpio0@ff750000 {
921 compatible = "rockchip,gpio-bank";
922 reg = <0xff750000 0x100>;
923 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&cru PCLK_GPIO0>;
929 interrupt-controller;
930 #interrupt-cells = <2>;
933 gpio1: gpio1@ff780000 {
934 compatible = "rockchip,gpio-bank";
935 reg = <0xff780000 0x100>;
936 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&cru PCLK_GPIO1>;
942 interrupt-controller;
943 #interrupt-cells = <2>;
946 gpio2: gpio2@ff790000 {
947 compatible = "rockchip,gpio-bank";
948 reg = <0xff790000 0x100>;
949 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cru PCLK_GPIO2>;
955 interrupt-controller;
956 #interrupt-cells = <2>;
959 gpio3: gpio3@ff7a0000 {
960 compatible = "rockchip,gpio-bank";
961 reg = <0xff7a0000 0x100>;
962 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru PCLK_GPIO3>;
968 interrupt-controller;
969 #interrupt-cells = <2>;
972 gpio4: gpio4@ff7b0000 {
973 compatible = "rockchip,gpio-bank";
974 reg = <0xff7b0000 0x100>;
975 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&cru PCLK_GPIO4>;
981 interrupt-controller;
982 #interrupt-cells = <2>;
985 gpio5: gpio5@ff7c0000 {
986 compatible = "rockchip,gpio-bank";
987 reg = <0xff7c0000 0x100>;
988 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cru PCLK_GPIO5>;
994 interrupt-controller;
995 #interrupt-cells = <2>;
998 gpio6: gpio6@ff7d0000 {
999 compatible = "rockchip,gpio-bank";
1000 reg = <0xff7d0000 0x100>;
1001 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru PCLK_GPIO6>;
1007 interrupt-controller;
1008 #interrupt-cells = <2>;
1011 gpio7: gpio7@ff7e0000 {
1012 compatible = "rockchip,gpio-bank";
1013 reg = <0xff7e0000 0x100>;
1014 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cru PCLK_GPIO7>;
1020 interrupt-controller;
1021 #interrupt-cells = <2>;
1024 gpio8: gpio8@ff7f0000 {
1025 compatible = "rockchip,gpio-bank";
1026 reg = <0xff7f0000 0x100>;
1027 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&cru PCLK_GPIO8>;
1033 interrupt-controller;
1034 #interrupt-cells = <2>;
1038 hdmi_ddc: hdmi-ddc {
1039 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1040 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1044 pcfg_pull_up: pcfg-pull-up {
1048 pcfg_pull_down: pcfg-pull-down {
1052 pcfg_pull_none: pcfg-pull-none {
1056 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1058 drive-strength = <12>;
1062 global_pwroff: global-pwroff {
1063 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1066 ddrio_pwroff: ddrio-pwroff {
1067 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1070 ddr0_retention: ddr0-retention {
1071 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1074 ddr1_retention: ddr1-retention {
1075 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1080 i2c0_xfer: i2c0-xfer {
1081 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1082 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1087 i2c1_xfer: i2c1-xfer {
1088 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1089 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1094 i2c2_xfer: i2c2-xfer {
1095 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1096 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1101 i2c3_xfer: i2c3-xfer {
1102 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1103 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1108 i2c4_xfer: i2c4-xfer {
1109 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1110 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1115 i2c5_xfer: i2c5-xfer {
1116 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1117 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1122 i2s0_bus: i2s0-bus {
1123 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1124 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1125 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1126 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1127 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1128 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1133 sdmmc_clk: sdmmc-clk {
1134 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1137 sdmmc_cmd: sdmmc-cmd {
1138 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1141 sdmmc_cd: sdmcc-cd {
1142 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1145 sdmmc_bus1: sdmmc-bus1 {
1146 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1149 sdmmc_bus4: sdmmc-bus4 {
1150 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1151 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1152 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1153 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1158 sdio0_bus1: sdio0-bus1 {
1159 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1162 sdio0_bus4: sdio0-bus4 {
1163 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1164 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1165 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1166 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1169 sdio0_cmd: sdio0-cmd {
1170 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1173 sdio0_clk: sdio0-clk {
1174 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1177 sdio0_cd: sdio0-cd {
1178 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1181 sdio0_wp: sdio0-wp {
1182 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1185 sdio0_pwr: sdio0-pwr {
1186 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1189 sdio0_bkpwr: sdio0-bkpwr {
1190 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1193 sdio0_int: sdio0-int {
1194 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1199 sdio1_bus1: sdio1-bus1 {
1200 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1203 sdio1_bus4: sdio1-bus4 {
1204 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1205 <3 25 4 &pcfg_pull_up>,
1206 <3 26 4 &pcfg_pull_up>,
1207 <3 27 4 &pcfg_pull_up>;
1210 sdio1_cd: sdio1-cd {
1211 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1214 sdio1_wp: sdio1-wp {
1215 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1218 sdio1_bkpwr: sdio1-bkpwr {
1219 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1222 sdio1_int: sdio1-int {
1223 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1226 sdio1_cmd: sdio1-cmd {
1227 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1230 sdio1_clk: sdio1-clk {
1231 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1234 sdio1_pwr: sdio1-pwr {
1235 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1240 emmc_clk: emmc-clk {
1241 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1244 emmc_cmd: emmc-cmd {
1245 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1248 emmc_pwr: emmc-pwr {
1249 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1252 emmc_bus1: emmc-bus1 {
1253 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1256 emmc_bus4: emmc-bus4 {
1257 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1258 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1259 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1260 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1263 emmc_bus8: emmc-bus8 {
1264 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1265 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1266 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1267 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1268 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1269 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1270 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1271 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1276 spi0_clk: spi0-clk {
1277 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1279 spi0_cs0: spi0-cs0 {
1280 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1283 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1286 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1288 spi0_cs1: spi0-cs1 {
1289 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1293 spi1_clk: spi1-clk {
1294 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1296 spi1_cs0: spi1-cs0 {
1297 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1300 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1303 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1308 spi2_cs1: spi2-cs1 {
1309 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1311 spi2_clk: spi2-clk {
1312 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1314 spi2_cs0: spi2-cs0 {
1315 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1318 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1321 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1326 uart0_xfer: uart0-xfer {
1327 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1328 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1331 uart0_cts: uart0-cts {
1332 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1335 uart0_rts: uart0-rts {
1336 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1341 uart1_xfer: uart1-xfer {
1342 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1343 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1346 uart1_cts: uart1-cts {
1347 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1350 uart1_rts: uart1-rts {
1351 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1356 uart2_xfer: uart2-xfer {
1357 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1358 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1360 /* no rts / cts for uart2 */
1364 uart3_xfer: uart3-xfer {
1365 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1366 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1369 uart3_cts: uart3-cts {
1370 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1373 uart3_rts: uart3-rts {
1374 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1379 uart4_xfer: uart4-xfer {
1380 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1381 <5 13 3 &pcfg_pull_none>;
1384 uart4_cts: uart4-cts {
1385 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1388 uart4_rts: uart4-rts {
1389 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1395 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1400 pwm0_pin: pwm0-pin {
1401 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1406 pwm1_pin: pwm1-pin {
1407 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1412 pwm2_pin: pwm2-pin {
1413 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1418 pwm3_pin: pwm3-pin {
1419 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1424 rgmii_pins: rgmii-pins {
1425 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1426 <3 31 3 &pcfg_pull_none>,
1427 <3 26 3 &pcfg_pull_none>,
1428 <3 27 3 &pcfg_pull_none>,
1429 <3 28 3 &pcfg_pull_none_12ma>,
1430 <3 29 3 &pcfg_pull_none_12ma>,
1431 <3 24 3 &pcfg_pull_none_12ma>,
1432 <3 25 3 &pcfg_pull_none_12ma>,
1433 <4 0 3 &pcfg_pull_none>,
1434 <4 5 3 &pcfg_pull_none>,
1435 <4 6 3 &pcfg_pull_none>,
1436 <4 9 3 &pcfg_pull_none_12ma>,
1437 <4 4 3 &pcfg_pull_none_12ma>,
1438 <4 1 3 &pcfg_pull_none>,
1439 <4 3 3 &pcfg_pull_none>;
1442 rmii_pins: rmii-pins {
1443 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1444 <3 31 3 &pcfg_pull_none>,
1445 <3 28 3 &pcfg_pull_none>,
1446 <3 29 3 &pcfg_pull_none>,
1447 <4 0 3 &pcfg_pull_none>,
1448 <4 5 3 &pcfg_pull_none>,
1449 <4 4 3 &pcfg_pull_none>,
1450 <4 1 3 &pcfg_pull_none>,
1451 <4 2 3 &pcfg_pull_none>,
1452 <4 3 3 &pcfg_pull_none>;
1457 spdif_tx: spdif-tx {
1458 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;