arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53 #include <dt-bindings/thermal/thermal.h>
  54
  55 #include <dt-bindings/pinctrl/sun4i-a10.h>
  56
  57 / {
  58         interrupt-parent = <&gic>;
  59
  60         aliases {
  61                 ethernet0 = &gmac;
  62         };
  63
  64         chosen {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 ranges;
  68
  69                 framebuffer@0 {
  70                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  71                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  72                         clocks = <&pll6 0>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer@1 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&pll6 0>;
  81                         status = "disabled";
  82                 };
  83         };
  84
  85         timer {
  86                 compatible = "arm,armv7-timer";
  87                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  89                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  91                 clock-frequency = <24000000>;
  92                 arm,cpu-registers-not-fw-configured;
  93         };
  94
  95         cpus {
  96                 enable-method = "allwinner,sun6i-a31";
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 cpu0: cpu@0 {
 101                         compatible = "arm,cortex-a7";
 102                         device_type = "cpu";
 103                         reg = <0>;
 104                         clocks = <&cpu>;
 105                         clock-latency = <244144>; /* 8 32k periods */
 106                         operating-points = <
 107                                 /* kHz    uV */
 108                                 1008000 1200000
 109                                 864000  1200000
 110                                 720000  1100000
 111                                 480000  1000000
 112                                 >;
 113                         #cooling-cells = <2>;
 114                         cooling-min-level = <0>;
 115                         cooling-max-level = <3>;
 116                 };
 117
 118                 cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                 };
 123
 124                 cpu@2 {
 125                         compatible = "arm,cortex-a7";
 126                         device_type = "cpu";
 127                         reg = <2>;
 128                 };
 129
 130                 cpu@3 {
 131                         compatible = "arm,cortex-a7";
 132                         device_type = "cpu";
 133                         reg = <3>;
 134                 };
 135         };
 136
 137         thermal-zones {
 138                 cpu_thermal {
 139                         /* milliseconds */
 140                         polling-delay-passive = <250>;
 141                         polling-delay = <1000>;
 142                         thermal-sensors = <&rtp>;
 143
 144                         cooling-maps {
 145                                 map0 {
 146                                         trip = <&cpu_alert0>;
 147                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 148                                 };
 149                         };
 150
 151                         trips {
 152                                 cpu_alert0: cpu_alert0 {
 153                                         /* milliCelsius */
 154                                         temperature = <70000>;
 155                                         hysteresis = <2000>;
 156                                         type = "passive";
 157                                 };
 158
 159                                 cpu_crit: cpu_crit {
 160                                         /* milliCelsius */
 161                                         temperature = <100000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166                 };
 167         };
 168
 169         memory {
 170                 reg = <0x40000000 0x80000000>;
 171         };
 172
 173         pmu {
 174                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 175                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 179         };
 180
 181         clocks {
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184                 ranges;
 185
 186                 osc24M: osc24M {
 187                         #clock-cells = <0>;
 188                         compatible = "fixed-clock";
 189                         clock-frequency = <24000000>;
 190                 };
 191
 192                 osc32k: clk@0 {
 193                         #clock-cells = <0>;
 194                         compatible = "fixed-clock";
 195                         clock-frequency = <32768>;
 196                         clock-output-names = "osc32k";
 197                 };
 198
 199                 pll1: clk@01c20000 {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun6i-a31-pll1-clk";
 202                         reg = <0x01c20000 0x4>;
 203                         clocks = <&osc24M>;
 204                         clock-output-names = "pll1";
 205                 };
 206
 207                 pll6: clk@01c20028 {
 208                         #clock-cells = <1>;
 209                         compatible = "allwinner,sun6i-a31-pll6-clk";
 210                         reg = <0x01c20028 0x4>;
 211                         clocks = <&osc24M>;
 212                         clock-output-names = "pll6", "pll6x2";
 213                 };
 214
 215                 cpu: cpu@01c20050 {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun4i-a10-cpu-clk";
 218                         reg = <0x01c20050 0x4>;
 219
 220                         /*
 221                          * PLL1 is listed twice here.
 222                          * While it looks suspicious, it's actually documented
 223                          * that way both in the datasheet and in the code from
 224                          * Allwinner.
 225                          */
 226                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 227                         clock-output-names = "cpu";
 228                 };
 229
 230                 axi: axi@01c20050 {
 231                         #clock-cells = <0>;
 232                         compatible = "allwinner,sun4i-a10-axi-clk";
 233                         reg = <0x01c20050 0x4>;
 234                         clocks = <&cpu>;
 235                         clock-output-names = "axi";
 236                 };
 237
 238                 ahb1: ahb1@01c20054 {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 241                         reg = <0x01c20054 0x4>;
 242                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 243                         clock-output-names = "ahb1";
 244
 245                         /*
 246                          * Clock AHB1 from PLL6, instead of CPU/AXI which
 247                          * has rate changes due to cpufreq. Also the DMA
 248                          * controller requires AHB1 clocked from PLL6.
 249                          */
 250                         assigned-clocks = <&ahb1>;
 251                         assigned-clock-parents = <&pll6 0>;
 252                 };
 253
 254                 ahb1_gates: clk@01c20060 {
 255                         #clock-cells = <1>;
 256                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 257                         reg = <0x01c20060 0x8>;
 258                         clocks = <&ahb1>;
 259                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 260                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 261                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 262                                         "ahb1_nand0", "ahb1_sdram",
 263                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 264                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 265                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 266                                         "ahb1_ehci1", "ahb1_ohci0",
 267                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 268                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 269                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 270                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 271                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 272                                         "ahb1_drc0", "ahb1_drc1";
 273                 };
 274
 275                 apb1: apb1@01c20054 {
 276                         #clock-cells = <0>;
 277                         compatible = "allwinner,sun4i-a10-apb0-clk";
 278                         reg = <0x01c20054 0x4>;
 279                         clocks = <&ahb1>;
 280                         clock-output-names = "apb1";
 281                 };
 282
 283                 apb1_gates: clk@01c20068 {
 284                         #clock-cells = <1>;
 285                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 286                         reg = <0x01c20068 0x4>;
 287                         clocks = <&apb1>;
 288                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 289                                         "apb1_pio", "apb1_daudio0",
 290                                         "apb1_daudio1";
 291                 };
 292
 293                 apb2: clk@01c20058 {
 294                         #clock-cells = <0>;
 295                         compatible = "allwinner,sun4i-a10-apb1-clk";
 296                         reg = <0x01c20058 0x4>;
 297                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 298                         clock-output-names = "apb2";
 299                 };
 300
 301                 apb2_gates: clk@01c2006c {
 302                         #clock-cells = <1>;
 303                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 304                         reg = <0x01c2006c 0x4>;
 305                         clocks = <&apb2>;
 306                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 307                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 308                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 309                                         "apb2_uart4", "apb2_uart5";
 310                 };
 311
 312                 mmc0_clk: clk@01c20088 {
 313                         #clock-cells = <1>;
 314                         compatible = "allwinner,sun4i-a10-mmc-clk";
 315                         reg = <0x01c20088 0x4>;
 316                         clocks = <&osc24M>, <&pll6 0>;
 317                         clock-output-names = "mmc0",
 318                                              "mmc0_output",
 319                                              "mmc0_sample";
 320                 };
 321
 322                 mmc1_clk: clk@01c2008c {
 323                         #clock-cells = <1>;
 324                         compatible = "allwinner,sun4i-a10-mmc-clk";
 325                         reg = <0x01c2008c 0x4>;
 326                         clocks = <&osc24M>, <&pll6 0>;
 327                         clock-output-names = "mmc1",
 328                                              "mmc1_output",
 329                                              "mmc1_sample";
 330                 };
 331
 332                 mmc2_clk: clk@01c20090 {
 333                         #clock-cells = <1>;
 334                         compatible = "allwinner,sun4i-a10-mmc-clk";
 335                         reg = <0x01c20090 0x4>;
 336                         clocks = <&osc24M>, <&pll6 0>;
 337                         clock-output-names = "mmc2",
 338                                              "mmc2_output",
 339                                              "mmc2_sample";
 340                 };
 341
 342                 mmc3_clk: clk@01c20094 {
 343                         #clock-cells = <1>;
 344                         compatible = "allwinner,sun4i-a10-mmc-clk";
 345                         reg = <0x01c20094 0x4>;
 346                         clocks = <&osc24M>, <&pll6 0>;
 347                         clock-output-names = "mmc3",
 348                                              "mmc3_output",
 349                                              "mmc3_sample";
 350                 };
 351
 352                 spi0_clk: clk@01c200a0 {
 353                         #clock-cells = <0>;
 354                         compatible = "allwinner,sun4i-a10-mod0-clk";
 355                         reg = <0x01c200a0 0x4>;
 356                         clocks = <&osc24M>, <&pll6 0>;
 357                         clock-output-names = "spi0";
 358                 };
 359
 360                 spi1_clk: clk@01c200a4 {
 361                         #clock-cells = <0>;
 362                         compatible = "allwinner,sun4i-a10-mod0-clk";
 363                         reg = <0x01c200a4 0x4>;
 364                         clocks = <&osc24M>, <&pll6 0>;
 365                         clock-output-names = "spi1";
 366                 };
 367
 368                 spi2_clk: clk@01c200a8 {
 369                         #clock-cells = <0>;
 370                         compatible = "allwinner,sun4i-a10-mod0-clk";
 371                         reg = <0x01c200a8 0x4>;
 372                         clocks = <&osc24M>, <&pll6 0>;
 373                         clock-output-names = "spi2";
 374                 };
 375
 376                 spi3_clk: clk@01c200ac {
 377                         #clock-cells = <0>;
 378                         compatible = "allwinner,sun4i-a10-mod0-clk";
 379                         reg = <0x01c200ac 0x4>;
 380                         clocks = <&osc24M>, <&pll6 0>;
 381                         clock-output-names = "spi3";
 382                 };
 383
 384                 usb_clk: clk@01c200cc {
 385                         #clock-cells = <1>;
 386                         #reset-cells = <1>;
 387                         compatible = "allwinner,sun6i-a31-usb-clk";
 388                         reg = <0x01c200cc 0x4>;
 389                         clocks = <&osc24M>;
 390                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 391                                              "usb_ohci0", "usb_ohci1",
 392                                              "usb_ohci2";
 393                 };
 394
 395                 /*
 396                  * The following two are dummy clocks, placeholders used in the gmac_tx
 397                  * clock. The gmac driver will choose one parent depending on the PHY
 398                  * interface mode, using clk_set_rate auto-reparenting.
 399                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 400                  */
 401                 mii_phy_tx_clk: clk@1 {
 402                         #clock-cells = <0>;
 403                         compatible = "fixed-clock";
 404                         clock-frequency = <25000000>;
 405                         clock-output-names = "mii_phy_tx";
 406                 };
 407
 408                 gmac_int_tx_clk: clk@2 {
 409                         #clock-cells = <0>;
 410                         compatible = "fixed-clock";
 411                         clock-frequency = <125000000>;
 412                         clock-output-names = "gmac_int_tx";
 413                 };
 414
 415                 gmac_tx_clk: clk@01c200d0 {
 416                         #clock-cells = <0>;
 417                         compatible = "allwinner,sun7i-a20-gmac-clk";
 418                         reg = <0x01c200d0 0x4>;
 419                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 420                         clock-output-names = "gmac_tx";
 421                 };
 422         };
 423
 424         soc@01c00000 {
 425                 compatible = "simple-bus";
 426                 #address-cells = <1>;
 427                 #size-cells = <1>;
 428                 ranges;
 429
 430                 dma: dma-controller@01c02000 {
 431                         compatible = "allwinner,sun6i-a31-dma";
 432                         reg = <0x01c02000 0x1000>;
 433                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&ahb1_gates 6>;
 435                         resets = <&ahb1_rst 6>;
 436                         #dma-cells = <1>;
 437                 };
 438
 439                 mmc0: mmc@01c0f000 {
 440                         compatible = "allwinner,sun5i-a13-mmc";
 441                         reg = <0x01c0f000 0x1000>;
 442                         clocks = <&ahb1_gates 8>,
 443                                  <&mmc0_clk 0>,
 444                                  <&mmc0_clk 1>,
 445                                  <&mmc0_clk 2>;
 446                         clock-names = "ahb",
 447                                       "mmc",
 448                                       "output",
 449                                       "sample";
 450                         resets = <&ahb1_rst 8>;
 451                         reset-names = "ahb";
 452                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 453                         status = "disabled";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                 };
 457
 458                 mmc1: mmc@01c10000 {
 459                         compatible = "allwinner,sun5i-a13-mmc";
 460                         reg = <0x01c10000 0x1000>;
 461                         clocks = <&ahb1_gates 9>,
 462                                  <&mmc1_clk 0>,
 463                                  <&mmc1_clk 1>,
 464                                  <&mmc1_clk 2>;
 465                         clock-names = "ahb",
 466                                       "mmc",
 467                                       "output",
 468                                       "sample";
 469                         resets = <&ahb1_rst 9>;
 470                         reset-names = "ahb";
 471                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 472                         status = "disabled";
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                 };
 476
 477                 mmc2: mmc@01c11000 {
 478                         compatible = "allwinner,sun5i-a13-mmc";
 479                         reg = <0x01c11000 0x1000>;
 480                         clocks = <&ahb1_gates 10>,
 481                                  <&mmc2_clk 0>,
 482                                  <&mmc2_clk 1>,
 483                                  <&mmc2_clk 2>;
 484                         clock-names = "ahb",
 485                                       "mmc",
 486                                       "output",
 487                                       "sample";
 488                         resets = <&ahb1_rst 10>;
 489                         reset-names = "ahb";
 490                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 491                         status = "disabled";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                 };
 495
 496                 mmc3: mmc@01c12000 {
 497                         compatible = "allwinner,sun5i-a13-mmc";
 498                         reg = <0x01c12000 0x1000>;
 499                         clocks = <&ahb1_gates 11>,
 500                                  <&mmc3_clk 0>,
 501                                  <&mmc3_clk 1>,
 502                                  <&mmc3_clk 2>;
 503                         clock-names = "ahb",
 504                                       "mmc",
 505                                       "output",
 506                                       "sample";
 507                         resets = <&ahb1_rst 11>;
 508                         reset-names = "ahb";
 509                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                         status = "disabled";
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                 };
 514
 515                 usbphy: phy@01c19400 {
 516                         compatible = "allwinner,sun6i-a31-usb-phy";
 517                         reg = <0x01c19400 0x10>,
 518                               <0x01c1a800 0x4>,
 519                               <0x01c1b800 0x4>;
 520                         reg-names = "phy_ctrl",
 521                                     "pmu1",
 522                                     "pmu2";
 523                         clocks = <&usb_clk 8>,
 524                                  <&usb_clk 9>,
 525                                  <&usb_clk 10>;
 526                         clock-names = "usb0_phy",
 527                                       "usb1_phy",
 528                                       "usb2_phy";
 529                         resets = <&usb_clk 0>,
 530                                  <&usb_clk 1>,
 531                                  <&usb_clk 2>;
 532                         reset-names = "usb0_reset",
 533                                       "usb1_reset",
 534                                       "usb2_reset";
 535                         status = "disabled";
 536                         #phy-cells = <1>;
 537                 };
 538
 539                 ehci0: usb@01c1a000 {
 540                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 541                         reg = <0x01c1a000 0x100>;
 542                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&ahb1_gates 26>;
 544                         resets = <&ahb1_rst 26>;
 545                         phys = <&usbphy 1>;
 546                         phy-names = "usb";
 547                         status = "disabled";
 548                 };
 549
 550                 ohci0: usb@01c1a400 {
 551                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 552                         reg = <0x01c1a400 0x100>;
 553                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 555                         resets = <&ahb1_rst 29>;
 556                         phys = <&usbphy 1>;
 557                         phy-names = "usb";
 558                         status = "disabled";
 559                 };
 560
 561                 ehci1: usb@01c1b000 {
 562                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 563                         reg = <0x01c1b000 0x100>;
 564                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&ahb1_gates 27>;
 566                         resets = <&ahb1_rst 27>;
 567                         phys = <&usbphy 2>;
 568                         phy-names = "usb";
 569                         status = "disabled";
 570                 };
 571
 572                 ohci1: usb@01c1b400 {
 573                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 574                         reg = <0x01c1b400 0x100>;
 575                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 577                         resets = <&ahb1_rst 30>;
 578                         phys = <&usbphy 2>;
 579                         phy-names = "usb";
 580                         status = "disabled";
 581                 };
 582
 583                 ohci2: usb@01c1c400 {
 584                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 585                         reg = <0x01c1c400 0x100>;
 586                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 588                         resets = <&ahb1_rst 31>;
 589                         status = "disabled";
 590                 };
 591
 592                 pio: pinctrl@01c20800 {
 593                         compatible = "allwinner,sun6i-a31-pinctrl";
 594                         reg = <0x01c20800 0x400>;
 595                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&apb1_gates 5>;
 600                         gpio-controller;
 601                         interrupt-controller;
 602                         #interrupt-cells = <2>;
 603                         #size-cells = <0>;
 604                         #gpio-cells = <3>;
 605
 606                         uart0_pins_a: uart0@0 {
 607                                 allwinner,pins = "PH20", "PH21";
 608                                 allwinner,function = "uart0";
 609                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 610                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 611                         };
 612
 613                         i2c0_pins_a: i2c0@0 {
 614                                 allwinner,pins = "PH14", "PH15";
 615                                 allwinner,function = "i2c0";
 616                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 617                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 618                         };
 619
 620                         i2c1_pins_a: i2c1@0 {
 621                                 allwinner,pins = "PH16", "PH17";
 622                                 allwinner,function = "i2c1";
 623                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 624                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 625                         };
 626
 627                         i2c2_pins_a: i2c2@0 {
 628                                 allwinner,pins = "PH18", "PH19";
 629                                 allwinner,function = "i2c2";
 630                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 631                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 632                         };
 633
 634                         mmc0_pins_a: mmc0@0 {
 635                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 636                                 allwinner,function = "mmc0";
 637                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 638                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 639                         };
 640
 641                         mmc1_pins_a: mmc1@0 {
 642                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 643                                                  "PG4", "PG5";
 644                                 allwinner,function = "mmc1";
 645                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 646                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 647                         };
 648
 649                         gmac_pins_mii_a: gmac_mii@0 {
 650                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 651                                                 "PA8", "PA9", "PA11",
 652                                                 "PA12", "PA13", "PA14", "PA19",
 653                                                 "PA20", "PA21", "PA22", "PA23",
 654                                                 "PA24", "PA26", "PA27";
 655                                 allwinner,function = "gmac";
 656                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 657                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 658                         };
 659
 660                         gmac_pins_gmii_a: gmac_gmii@0 {
 661                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 662                                                 "PA4", "PA5", "PA6", "PA7",
 663                                                 "PA8", "PA9", "PA10", "PA11",
 664                                                 "PA12", "PA13", "PA14", "PA15",
 665                                                 "PA16", "PA17", "PA18", "PA19",
 666                                                 "PA20", "PA21", "PA22", "PA23",
 667                                                 "PA24", "PA25", "PA26", "PA27";
 668                                 allwinner,function = "gmac";
 669                                 /*
 670                                  * data lines in GMII mode run at 125MHz and
 671                                  * might need a higher signal drive strength
 672                                  */
 673                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 674                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 675                         };
 676
 677                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 678                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 679                                                 "PA9", "PA10", "PA11",
 680                                                 "PA12", "PA13", "PA14", "PA19",
 681                                                 "PA20", "PA25", "PA26", "PA27";
 682                                 allwinner,function = "gmac";
 683                                 /*
 684                                  * data lines in RGMII mode use DDR mode
 685                                  * and need a higher signal drive strength
 686                                  */
 687                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 688                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 689                         };
 690                 };
 691
 692                 ahb1_rst: reset@01c202c0 {
 693                         #reset-cells = <1>;
 694                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 695                         reg = <0x01c202c0 0xc>;
 696                 };
 697
 698                 apb1_rst: reset@01c202d0 {
 699                         #reset-cells = <1>;
 700                         compatible = "allwinner,sun6i-a31-clock-reset";
 701                         reg = <0x01c202d0 0x4>;
 702                 };
 703
 704                 apb2_rst: reset@01c202d8 {
 705                         #reset-cells = <1>;
 706                         compatible = "allwinner,sun6i-a31-clock-reset";
 707                         reg = <0x01c202d8 0x4>;
 708                 };
 709
 710                 timer@01c20c00 {
 711                         compatible = "allwinner,sun4i-a10-timer";
 712                         reg = <0x01c20c00 0xa0>;
 713                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&osc24M>;
 719                 };
 720
 721                 wdt1: watchdog@01c20ca0 {
 722                         compatible = "allwinner,sun6i-a31-wdt";
 723                         reg = <0x01c20ca0 0x20>;
 724                 };
 725
 726                 rtp: rtp@01c25000 {
 727                         compatible = "allwinner,sun6i-a31-ts";
 728                         reg = <0x01c25000 0x100>;
 729                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 730                         #thermal-sensor-cells = <0>;
 731                 };
 732
 733                 uart0: serial@01c28000 {
 734                         compatible = "snps,dw-apb-uart";
 735                         reg = <0x01c28000 0x400>;
 736                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 737                         reg-shift = <2>;
 738                         reg-io-width = <4>;
 739                         clocks = <&apb2_gates 16>;
 740                         resets = <&apb2_rst 16>;
 741                         dmas = <&dma 6>, <&dma 6>;
 742                         dma-names = "rx", "tx";
 743                         status = "disabled";
 744                 };
 745
 746                 uart1: serial@01c28400 {
 747                         compatible = "snps,dw-apb-uart";
 748                         reg = <0x01c28400 0x400>;
 749                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 750                         reg-shift = <2>;
 751                         reg-io-width = <4>;
 752                         clocks = <&apb2_gates 17>;
 753                         resets = <&apb2_rst 17>;
 754                         dmas = <&dma 7>, <&dma 7>;
 755                         dma-names = "rx", "tx";
 756                         status = "disabled";
 757                 };
 758
 759                 uart2: serial@01c28800 {
 760                         compatible = "snps,dw-apb-uart";
 761                         reg = <0x01c28800 0x400>;
 762                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 763                         reg-shift = <2>;
 764                         reg-io-width = <4>;
 765                         clocks = <&apb2_gates 18>;
 766                         resets = <&apb2_rst 18>;
 767                         dmas = <&dma 8>, <&dma 8>;
 768                         dma-names = "rx", "tx";
 769                         status = "disabled";
 770                 };
 771
 772                 uart3: serial@01c28c00 {
 773                         compatible = "snps,dw-apb-uart";
 774                         reg = <0x01c28c00 0x400>;
 775                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 776                         reg-shift = <2>;
 777                         reg-io-width = <4>;
 778                         clocks = <&apb2_gates 19>;
 779                         resets = <&apb2_rst 19>;
 780                         dmas = <&dma 9>, <&dma 9>;
 781                         dma-names = "rx", "tx";
 782                         status = "disabled";
 783                 };
 784
 785                 uart4: serial@01c29000 {
 786                         compatible = "snps,dw-apb-uart";
 787                         reg = <0x01c29000 0x400>;
 788                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 789                         reg-shift = <2>;
 790                         reg-io-width = <4>;
 791                         clocks = <&apb2_gates 20>;
 792                         resets = <&apb2_rst 20>;
 793                         dmas = <&dma 10>, <&dma 10>;
 794                         dma-names = "rx", "tx";
 795                         status = "disabled";
 796                 };
 797
 798                 uart5: serial@01c29400 {
 799                         compatible = "snps,dw-apb-uart";
 800                         reg = <0x01c29400 0x400>;
 801                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 802                         reg-shift = <2>;
 803                         reg-io-width = <4>;
 804                         clocks = <&apb2_gates 21>;
 805                         resets = <&apb2_rst 21>;
 806                         dmas = <&dma 22>, <&dma 22>;
 807                         dma-names = "rx", "tx";
 808                         status = "disabled";
 809                 };
 810
 811                 i2c0: i2c@01c2ac00 {
 812                         compatible = "allwinner,sun6i-a31-i2c";
 813                         reg = <0x01c2ac00 0x400>;
 814                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 815                         clocks = <&apb2_gates 0>;
 816                         resets = <&apb2_rst 0>;
 817                         status = "disabled";
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820                 };
 821
 822                 i2c1: i2c@01c2b000 {
 823                         compatible = "allwinner,sun6i-a31-i2c";
 824                         reg = <0x01c2b000 0x400>;
 825                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 826                         clocks = <&apb2_gates 1>;
 827                         resets = <&apb2_rst 1>;
 828                         status = "disabled";
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831                 };
 832
 833                 i2c2: i2c@01c2b400 {
 834                         compatible = "allwinner,sun6i-a31-i2c";
 835                         reg = <0x01c2b400 0x400>;
 836                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 837                         clocks = <&apb2_gates 2>;
 838                         resets = <&apb2_rst 2>;
 839                         status = "disabled";
 840                         #address-cells = <1>;
 841                         #size-cells = <0>;
 842                 };
 843
 844                 i2c3: i2c@01c2b800 {
 845                         compatible = "allwinner,sun6i-a31-i2c";
 846                         reg = <0x01c2b800 0x400>;
 847                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 848                         clocks = <&apb2_gates 3>;
 849                         resets = <&apb2_rst 3>;
 850                         status = "disabled";
 851                         #address-cells = <1>;
 852                         #size-cells = <0>;
 853                 };
 854
 855                 gmac: ethernet@01c30000 {
 856                         compatible = "allwinner,sun7i-a20-gmac";
 857                         reg = <0x01c30000 0x1054>;
 858                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 859                         interrupt-names = "macirq";
 860                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 861                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 862                         resets = <&ahb1_rst 17>;
 863                         reset-names = "stmmaceth";
 864                         snps,pbl = <2>;
 865                         snps,fixed-burst;
 866                         snps,force_sf_dma_mode;
 867                         status = "disabled";
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870                 };
 871
 872                 timer@01c60000 {
 873                         compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
 874                         reg = <0x01c60000 0x1000>;
 875                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 876                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 877                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 878                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 879                         clocks = <&ahb1_gates 19>;
 880                         resets = <&ahb1_rst 19>;
 881                 };
 882
 883                 spi0: spi@01c68000 {
 884                         compatible = "allwinner,sun6i-a31-spi";
 885                         reg = <0x01c68000 0x1000>;
 886                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 888                         clock-names = "ahb", "mod";
 889                         dmas = <&dma 23>, <&dma 23>;
 890                         dma-names = "rx", "tx";
 891                         resets = <&ahb1_rst 20>;
 892                         status = "disabled";
 893                 };
 894
 895                 spi1: spi@01c69000 {
 896                         compatible = "allwinner,sun6i-a31-spi";
 897                         reg = <0x01c69000 0x1000>;
 898                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 900                         clock-names = "ahb", "mod";
 901                         dmas = <&dma 24>, <&dma 24>;
 902                         dma-names = "rx", "tx";
 903                         resets = <&ahb1_rst 21>;
 904                         status = "disabled";
 905                 };
 906
 907                 spi2: spi@01c6a000 {
 908                         compatible = "allwinner,sun6i-a31-spi";
 909                         reg = <0x01c6a000 0x1000>;
 910                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 912                         clock-names = "ahb", "mod";
 913                         dmas = <&dma 25>, <&dma 25>;
 914                         dma-names = "rx", "tx";
 915                         resets = <&ahb1_rst 22>;
 916                         status = "disabled";
 917                 };
 918
 919                 spi3: spi@01c6b000 {
 920                         compatible = "allwinner,sun6i-a31-spi";
 921                         reg = <0x01c6b000 0x1000>;
 922                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 923                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 924                         clock-names = "ahb", "mod";
 925                         dmas = <&dma 26>, <&dma 26>;
 926                         dma-names = "rx", "tx";
 927                         resets = <&ahb1_rst 23>;
 928                         status = "disabled";
 929                 };
 930
 931                 gic: interrupt-controller@01c81000 {
 932                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 933                         reg = <0x01c81000 0x1000>,
 934                               <0x01c82000 0x1000>,
 935                               <0x01c84000 0x2000>,
 936                               <0x01c86000 0x2000>;
 937                         interrupt-controller;
 938                         #interrupt-cells = <3>;
 939                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 940                 };
 941
 942                 rtc: rtc@01f00000 {
 943                         compatible = "allwinner,sun6i-a31-rtc";
 944                         reg = <0x01f00000 0x54>;
 945                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 947                 };
 948
 949                 nmi_intc: interrupt-controller@01f00c0c {
 950                         compatible = "allwinner,sun6i-a31-sc-nmi";
 951                         interrupt-controller;
 952                         #interrupt-cells = <2>;
 953                         reg = <0x01f00c0c 0x38>;
 954                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 955                 };
 956
 957                 prcm@01f01400 {
 958                         compatible = "allwinner,sun6i-a31-prcm";
 959                         reg = <0x01f01400 0x200>;
 960
 961                         ar100: ar100_clk {
 962                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 963                                 #clock-cells = <0>;
 964                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 965                                 clock-output-names = "ar100";
 966                         };
 967
 968                         ahb0: ahb0_clk {
 969                                 compatible = "fixed-factor-clock";
 970                                 #clock-cells = <0>;
 971                                 clock-div = <1>;
 972                                 clock-mult = <1>;
 973                                 clocks = <&ar100>;
 974                                 clock-output-names = "ahb0";
 975                         };
 976
 977                         apb0: apb0_clk {
 978                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 979                                 #clock-cells = <0>;
 980                                 clocks = <&ahb0>;
 981                                 clock-output-names = "apb0";
 982                         };
 983
 984                         apb0_gates: apb0_gates_clk {
 985                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 986                                 #clock-cells = <1>;
 987                                 clocks = <&apb0>;
 988                                 clock-output-names = "apb0_pio", "apb0_ir",
 989                                                 "apb0_timer", "apb0_p2wi",
 990                                                 "apb0_uart", "apb0_1wire",
 991                                                 "apb0_i2c";
 992                         };
 993
 994                         ir_clk: ir_clk {
 995                                 #clock-cells = <0>;
 996                                 compatible = "allwinner,sun4i-a10-mod0-clk";
 997                                 clocks = <&osc32k>, <&osc24M>;
 998                                 clock-output-names = "ir";
 999                         };
1000
1001                         apb0_rst: apb0_rst {
1002                                 compatible = "allwinner,sun6i-a31-clock-reset";
1003                                 #reset-cells = <1>;
1004                         };
1005                 };
1006
1007                 cpucfg@01f01c00 {
1008                         compatible = "allwinner,sun6i-a31-cpuconfig";
1009                         reg = <0x01f01c00 0x300>;
1010                 };
1011
1012                 ir: ir@01f02000 {
1013                         compatible = "allwinner,sun5i-a13-ir";
1014                         clocks = <&apb0_gates 1>, <&ir_clk>;
1015                         clock-names = "apb", "ir";
1016                         resets = <&apb0_rst 1>;
1017                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1018                         reg = <0x01f02000 0x40>;
1019                         status = "disabled";
1020                 };
1021
1022                 r_pio: pinctrl@01f02c00 {
1023                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1024                         reg = <0x01f02c00 0x400>;
1025                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&apb0_gates 0>;
1028                         resets = <&apb0_rst 0>;
1029                         gpio-controller;
1030                         interrupt-controller;
1031                         #interrupt-cells = <2>;
1032                         #size-cells = <0>;
1033                         #gpio-cells = <3>;
1034
1035                         ir_pins_a: ir@0 {
1036                                 allwinner,pins = "PL4";
1037                                 allwinner,function = "s_ir";
1038                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1039                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1040                         };
1041
1042                         p2wi_pins: p2wi {
1043                                 allwinner,pins = "PL0", "PL1";
1044                                 allwinner,function = "s_p2wi";
1045                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1046                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1047                         };
1048                 };
1049
1050                 p2wi: i2c@01f03400 {
1051                         compatible = "allwinner,sun6i-a31-p2wi";
1052                         reg = <0x01f03400 0x400>;
1053                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1054                         clocks = <&apb0_gates 3>;
1055                         clock-frequency = <100000>;
1056                         resets = <&apb0_rst 3>;
1057                         pinctrl-names = "default";
1058                         pinctrl-0 = <&p2wi_pins>;
1059                         status = "disabled";
1060                         #address-cells = <1>;
1061                         #size-cells = <0>;
1062                 };
1063         };
1064 };