2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
50 /include/ "skeleton64.dtsi"
53 interrupt-parent = <&gic>;
60 compatible = "arm,cortex-a7";
66 compatible = "arm,cortex-a7";
72 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a15";
90 compatible = "arm,cortex-a15";
96 compatible = "arm,cortex-a15";
102 compatible = "arm,cortex-a15";
109 /* 8GB max. with LPAE */
110 reg = <0 0x20000000 0x02 0>;
114 #address-cells = <1>;
117 * map 64 bit address range down to 32 bits,
118 * as the peripherals are all under 512MB.
120 ranges = <0 0 0 0x20000000>;
124 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "osc24M";
131 compatible = "fixed-clock";
132 clock-frequency = <32768>;
133 clock-output-names = "osc32k";
138 compatible = "allwinner,sun9i-a80-pll4-clk";
139 reg = <0x0600000c 0x4>;
141 clock-output-names = "pll4";
144 pll12: clk@0600002c {
146 compatible = "allwinner,sun9i-a80-pll4-clk";
147 reg = <0x0600002c 0x4>;
149 clock-output-names = "pll12";
152 gt_clk: clk@0600005c {
154 compatible = "allwinner,sun9i-a80-gt-clk";
155 reg = <0x0600005c 0x4>;
156 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
157 clock-output-names = "gt";
162 compatible = "allwinner,sun9i-a80-ahb-clk";
163 reg = <0x06000060 0x4>;
164 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
165 clock-output-names = "ahb0";
170 compatible = "allwinner,sun9i-a80-ahb-clk";
171 reg = <0x06000064 0x4>;
172 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
173 clock-output-names = "ahb1";
178 compatible = "allwinner,sun9i-a80-ahb-clk";
179 reg = <0x06000068 0x4>;
180 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
181 clock-output-names = "ahb2";
186 compatible = "allwinner,sun9i-a80-apb0-clk";
187 reg = <0x06000070 0x4>;
188 clocks = <&osc24M>, <&pll4>;
189 clock-output-names = "apb0";
194 compatible = "allwinner,sun9i-a80-apb1-clk";
195 reg = <0x06000074 0x4>;
196 clocks = <&osc24M>, <&pll4>;
197 clock-output-names = "apb1";
200 cci400_clk: clk@06000078 {
202 compatible = "allwinner,sun9i-a80-gt-clk";
203 reg = <0x06000078 0x4>;
204 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
205 clock-output-names = "cci400";
208 ahb0_gates: clk@06000580 {
210 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
211 reg = <0x06000580 0x4>;
213 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
214 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
215 "ahb0_nand0", "ahb0_sdram",
216 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
217 "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
221 ahb1_gates: clk@06000584 {
223 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
224 reg = <0x06000584 0x4>;
226 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
227 "ahb1_gmac", "ahb1_msgbox",
228 "ahb1_spinlock", "ahb1_hstimer",
232 ahb2_gates: clk@06000588 {
234 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
235 reg = <0x06000588 0x4>;
237 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
238 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
239 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
242 apb0_gates: clk@06000590 {
244 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
245 reg = <0x06000590 0x4>;
247 clock-output-names = "apb0_spdif", "apb0_pio",
248 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
249 "apb0_lradc", "apb0_gpadc", "apb0_twd",
253 apb1_gates: clk@06000594 {
255 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
256 reg = <0x06000594 0x4>;
258 clock-output-names = "apb1_i2c0", "apb1_i2c1",
259 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
260 "apb1_uart0", "apb1_uart1",
261 "apb1_uart2", "apb1_uart3",
262 "apb1_uart4", "apb1_uart5";
267 compatible = "simple-bus";
268 #address-cells = <1>;
271 * map 64 bit address range down to 32 bits,
272 * as the peripherals are all under 512MB.
274 ranges = <0 0 0 0x20000000>;
276 gic: interrupt-controller@01c41000 {
277 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
278 reg = <0x01c41000 0x1000>,
282 interrupt-controller;
283 #interrupt-cells = <3>;
284 interrupts = <1 9 0xf04>;
287 ahb0_resets: reset@060005a0 {
289 compatible = "allwinner,sun6i-a31-clock-reset";
290 reg = <0x060005a0 0x4>;
293 ahb1_resets: reset@060005a4 {
295 compatible = "allwinner,sun6i-a31-clock-reset";
296 reg = <0x060005a4 0x4>;
299 ahb2_resets: reset@060005a8 {
301 compatible = "allwinner,sun6i-a31-clock-reset";
302 reg = <0x060005a8 0x4>;
305 apb0_resets: reset@060005b0 {
307 compatible = "allwinner,sun6i-a31-clock-reset";
308 reg = <0x060005b0 0x4>;
311 apb1_resets: reset@060005b4 {
313 compatible = "allwinner,sun6i-a31-clock-reset";
314 reg = <0x060005b4 0x4>;
318 compatible = "allwinner,sun4i-a10-timer";
319 reg = <0x06000c00 0xa0>;
320 interrupts = <0 18 4>,
330 pio: pinctrl@06000800 {
331 compatible = "allwinner,sun9i-a80-pinctrl";
332 reg = <0x06000800 0x400>;
333 interrupts = <0 11 4>,
338 clocks = <&apb0_gates 5>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
345 i2c3_pins_a: i2c3@0 {
346 allwinner,pins = "PG10", "PG11";
347 allwinner,function = "i2c3";
348 allwinner,drive = <0>;
349 allwinner,pull = <0>;
352 uart0_pins_a: uart0@0 {
353 allwinner,pins = "PH12", "PH13";
354 allwinner,function = "uart0";
355 allwinner,drive = <0>;
356 allwinner,pull = <0>;
359 uart4_pins_a: uart4@0 {
360 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
361 allwinner,function = "uart4";
362 allwinner,drive = <0>;
363 allwinner,pull = <0>;
367 uart0: serial@07000000 {
368 compatible = "snps,dw-apb-uart";
369 reg = <0x07000000 0x400>;
370 interrupts = <0 0 4>;
373 clocks = <&apb1_gates 16>;
374 resets = <&apb1_resets 16>;
378 uart1: serial@07000400 {
379 compatible = "snps,dw-apb-uart";
380 reg = <0x07000400 0x400>;
381 interrupts = <0 1 4>;
384 clocks = <&apb1_gates 17>;
385 resets = <&apb1_resets 17>;
389 uart2: serial@07000800 {
390 compatible = "snps,dw-apb-uart";
391 reg = <0x07000800 0x400>;
392 interrupts = <0 2 4>;
395 clocks = <&apb1_gates 18>;
396 resets = <&apb1_resets 18>;
400 uart3: serial@07000c00 {
401 compatible = "snps,dw-apb-uart";
402 reg = <0x07000c00 0x400>;
403 interrupts = <0 3 4>;
406 clocks = <&apb1_gates 19>;
407 resets = <&apb1_resets 19>;
411 uart4: serial@07001000 {
412 compatible = "snps,dw-apb-uart";
413 reg = <0x07001000 0x400>;
414 interrupts = <0 4 4>;
417 clocks = <&apb1_gates 20>;
418 resets = <&apb1_resets 20>;
422 uart5: serial@07001400 {
423 compatible = "snps,dw-apb-uart";
424 reg = <0x07001400 0x400>;
425 interrupts = <0 5 4>;
428 clocks = <&apb1_gates 21>;
429 resets = <&apb1_resets 21>;
434 compatible = "allwinner,sun6i-a31-i2c";
435 reg = <0x07002800 0x400>;
436 interrupts = <0 6 4>;
437 clocks = <&apb1_gates 0>;
438 resets = <&apb1_resets 0>;
440 #address-cells = <1>;
445 compatible = "allwinner,sun6i-a31-i2c";
446 reg = <0x07002c00 0x400>;
447 interrupts = <0 7 4>;
448 clocks = <&apb1_gates 1>;
449 resets = <&apb1_resets 1>;
451 #address-cells = <1>;
456 compatible = "allwinner,sun6i-a31-i2c";
457 reg = <0x07003000 0x400>;
458 interrupts = <0 8 4>;
459 clocks = <&apb1_gates 2>;
460 resets = <&apb1_resets 2>;
462 #address-cells = <1>;
467 compatible = "allwinner,sun6i-a31-i2c";
468 reg = <0x07003400 0x400>;
469 interrupts = <0 9 4>;
470 clocks = <&apb1_gates 3>;
471 resets = <&apb1_resets 3>;
473 #address-cells = <1>;
478 compatible = "allwinner,sun6i-a31-i2c";
479 reg = <0x07003800 0x400>;
480 interrupts = <0 10 4>;
481 clocks = <&apb1_gates 4>;
482 resets = <&apb1_resets 4>;
484 #address-cells = <1>;
488 r_wdt: watchdog@08001000 {
489 compatible = "allwinner,sun6i-a31-wdt";
490 reg = <0x08001000 0x20>;
491 interrupts = <0 36 4>;
494 r_uart: serial@08002800 {
495 compatible = "snps,dw-apb-uart";
496 reg = <0x08002800 0x400>;
497 interrupts = <0 38 4>;