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[karo-tx-linux.git] / arch / arm / boot / dts / sun9i-a80.dtsi
1 /*
2  * Copyright 2014 Chen-Yu Tsai
3  *
4  * Chen-Yu Tsai <wens@csie.org>
5  *
6  * This file is dual-licensed: you can use it either under the terms
7  * of the GPL or the X11 license, at your option. Note that this dual
8  * licensing only applies to this file, and not this project as a
9  * whole.
10  *
11  *  a) This file is free software; you can redistribute it and/or
12  *     modify it under the terms of the GNU General Public License as
13  *     published by the Free Software Foundation; either version 2 of the
14  *     License, or (at your option) any later version.
15  *
16  *     This file is distributed in the hope that it will be useful,
17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *     GNU General Public License for more details.
20  *
21  *     You should have received a copy of the GNU General Public
22  *     License along with this file; if not, write to the Free
23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24  *     MA 02110-1301 USA
25  *
26  * Or, alternatively,
27  *
28  *  b) Permission is hereby granted, free of charge, to any person
29  *     obtaining a copy of this software and associated documentation
30  *     files (the "Software"), to deal in the Software without
31  *     restriction, including without limitation the rights to use,
32  *     copy, modify, merge, publish, distribute, sublicense, and/or
33  *     sell copies of the Software, and to permit persons to whom the
34  *     Software is furnished to do so, subject to the following
35  *     conditions:
36  *
37  *     The above copyright notice and this permission notice shall be
38  *     included in all copies or substantial portions of the Software.
39  *
40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47  *     OTHER DEALINGS IN THE SOFTWARE.
48  */
49
50 /include/ "skeleton64.dtsi"
51
52 / {
53         interrupt-parent = <&gic>;
54
55         aliases {
56                 serial0 = &uart0;
57                 serial1 = &uart1;
58                 serial2 = &uart2;
59                 serial3 = &uart3;
60                 serial4 = &uart4;
61                 serial5 = &uart5;
62                 serial6 = &r_uart;
63         };
64
65         cpus {
66                 #address-cells = <1>;
67                 #size-cells = <0>;
68
69                 cpu0: cpu@0 {
70                         compatible = "arm,cortex-a7";
71                         device_type = "cpu";
72                         reg = <0x0>;
73                 };
74
75                 cpu1: cpu@1 {
76                         compatible = "arm,cortex-a7";
77                         device_type = "cpu";
78                         reg = <0x1>;
79                 };
80
81                 cpu2: cpu@2 {
82                         compatible = "arm,cortex-a7";
83                         device_type = "cpu";
84                         reg = <0x2>;
85                 };
86
87                 cpu3: cpu@3 {
88                         compatible = "arm,cortex-a7";
89                         device_type = "cpu";
90                         reg = <0x3>;
91                 };
92
93                 cpu4: cpu@100 {
94                         compatible = "arm,cortex-a15";
95                         device_type = "cpu";
96                         reg = <0x100>;
97                 };
98
99                 cpu5: cpu@101 {
100                         compatible = "arm,cortex-a15";
101                         device_type = "cpu";
102                         reg = <0x101>;
103                 };
104
105                 cpu6: cpu@102 {
106                         compatible = "arm,cortex-a15";
107                         device_type = "cpu";
108                         reg = <0x102>;
109                 };
110
111                 cpu7: cpu@103 {
112                         compatible = "arm,cortex-a15";
113                         device_type = "cpu";
114                         reg = <0x103>;
115                 };
116         };
117
118         memory {
119                 /* 8GB max. with LPAE */
120                 reg = <0 0x20000000 0x02 0>;
121         };
122
123         clocks {
124                 #address-cells = <1>;
125                 #size-cells = <1>;
126                 /*
127                  * map 64 bit address range down to 32 bits,
128                  * as the peripherals are all under 512MB.
129                  */
130                 ranges = <0 0 0 0x20000000>;
131
132                 osc24M: osc24M_clk {
133                         #clock-cells = <0>;
134                         compatible = "fixed-clock";
135                         clock-frequency = <24000000>;
136                         clock-output-names = "osc24M";
137                 };
138
139                 osc32k: osc32k_clk {
140                         #clock-cells = <0>;
141                         compatible = "fixed-clock";
142                         clock-frequency = <32768>;
143                         clock-output-names = "osc32k";
144                 };
145
146                 pll4: clk@0600000c {
147                         #clock-cells = <0>;
148                         compatible = "allwinner,sun9i-a80-pll4-clk";
149                         reg = <0x0600000c 0x4>;
150                         clocks = <&osc24M>;
151                         clock-output-names = "pll4";
152                 };
153
154                 pll12: clk@0600002c {
155                         #clock-cells = <0>;
156                         compatible = "allwinner,sun9i-a80-pll4-clk";
157                         reg = <0x0600002c 0x4>;
158                         clocks = <&osc24M>;
159                         clock-output-names = "pll12";
160                 };
161
162                 gt_clk: clk@0600005c {
163                         #clock-cells = <0>;
164                         compatible = "allwinner,sun9i-a80-gt-clk";
165                         reg = <0x0600005c 0x4>;
166                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
167                         clock-output-names = "gt";
168                 };
169
170                 ahb0: clk@06000060 {
171                         #clock-cells = <0>;
172                         compatible = "allwinner,sun9i-a80-ahb-clk";
173                         reg = <0x06000060 0x4>;
174                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
175                         clock-output-names = "ahb0";
176                 };
177
178                 ahb1: clk@06000064 {
179                         #clock-cells = <0>;
180                         compatible = "allwinner,sun9i-a80-ahb-clk";
181                         reg = <0x06000064 0x4>;
182                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
183                         clock-output-names = "ahb1";
184                 };
185
186                 ahb2: clk@06000068 {
187                         #clock-cells = <0>;
188                         compatible = "allwinner,sun9i-a80-ahb-clk";
189                         reg = <0x06000068 0x4>;
190                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
191                         clock-output-names = "ahb2";
192                 };
193
194                 apb0: clk@06000070 {
195                         #clock-cells = <0>;
196                         compatible = "allwinner,sun9i-a80-apb0-clk";
197                         reg = <0x06000070 0x4>;
198                         clocks = <&osc24M>, <&pll4>;
199                         clock-output-names = "apb0";
200                 };
201
202                 apb1: clk@06000074 {
203                         #clock-cells = <0>;
204                         compatible = "allwinner,sun9i-a80-apb1-clk";
205                         reg = <0x06000074 0x4>;
206                         clocks = <&osc24M>, <&pll4>;
207                         clock-output-names = "apb1";
208                 };
209
210                 cci400_clk: clk@06000078 {
211                         #clock-cells = <0>;
212                         compatible = "allwinner,sun9i-a80-gt-clk";
213                         reg = <0x06000078 0x4>;
214                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
215                         clock-output-names = "cci400";
216                 };
217
218                 ahb0_gates: clk@06000580 {
219                         #clock-cells = <1>;
220                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
221                         reg = <0x06000580 0x4>;
222                         clocks = <&ahb0>;
223                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
224                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
225                                         "ahb0_nand0", "ahb0_sdram",
226                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
227                                         "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
228                                         "ahb0_spi3";
229                 };
230
231                 ahb1_gates: clk@06000584 {
232                         #clock-cells = <1>;
233                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
234                         reg = <0x06000584 0x4>;
235                         clocks = <&ahb1>;
236                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
237                                         "ahb1_gmac", "ahb1_msgbox",
238                                         "ahb1_spinlock", "ahb1_hstimer",
239                                         "ahb1_dma";
240                 };
241
242                 ahb2_gates: clk@06000588 {
243                         #clock-cells = <1>;
244                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
245                         reg = <0x06000588 0x4>;
246                         clocks = <&ahb2>;
247                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
248                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
249                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
250                 };
251
252                 apb0_gates: clk@06000590 {
253                         #clock-cells = <1>;
254                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
255                         reg = <0x06000590 0x4>;
256                         clocks = <&apb0>;
257                         clock-output-names = "apb0_spdif", "apb0_pio",
258                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
259                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
260                                         "apb0_cirtx";
261                 };
262
263                 apb1_gates: clk@06000594 {
264                         #clock-cells = <1>;
265                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
266                         reg = <0x06000594 0x4>;
267                         clocks = <&apb1>;
268                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
269                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
270                                         "apb1_uart0", "apb1_uart1",
271                                         "apb1_uart2", "apb1_uart3",
272                                         "apb1_uart4", "apb1_uart5";
273                 };
274         };
275
276         soc {
277                 compatible = "simple-bus";
278                 #address-cells = <1>;
279                 #size-cells = <1>;
280                 /*
281                  * map 64 bit address range down to 32 bits,
282                  * as the peripherals are all under 512MB.
283                  */
284                 ranges = <0 0 0 0x20000000>;
285
286                 gic: interrupt-controller@01c41000 {
287                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
288                         reg = <0x01c41000 0x1000>,
289                               <0x01c42000 0x1000>,
290                               <0x01c44000 0x2000>,
291                               <0x01c46000 0x2000>;
292                         interrupt-controller;
293                         #interrupt-cells = <3>;
294                         interrupts = <1 9 0xf04>;
295                 };
296
297                 ahb0_resets: reset@060005a0 {
298                         #reset-cells = <1>;
299                         compatible = "allwinner,sun6i-a31-clock-reset";
300                         reg = <0x060005a0 0x4>;
301                 };
302
303                 ahb1_resets: reset@060005a4 {
304                         #reset-cells = <1>;
305                         compatible = "allwinner,sun6i-a31-clock-reset";
306                         reg = <0x060005a4 0x4>;
307                 };
308
309                 ahb2_resets: reset@060005a8 {
310                         #reset-cells = <1>;
311                         compatible = "allwinner,sun6i-a31-clock-reset";
312                         reg = <0x060005a8 0x4>;
313                 };
314
315                 apb0_resets: reset@060005b0 {
316                         #reset-cells = <1>;
317                         compatible = "allwinner,sun6i-a31-clock-reset";
318                         reg = <0x060005b0 0x4>;
319                 };
320
321                 apb1_resets: reset@060005b4 {
322                         #reset-cells = <1>;
323                         compatible = "allwinner,sun6i-a31-clock-reset";
324                         reg = <0x060005b4 0x4>;
325                 };
326
327                 timer@06000c00 {
328                         compatible = "allwinner,sun4i-a10-timer";
329                         reg = <0x06000c00 0xa0>;
330                         interrupts = <0 18 4>,
331                                      <0 19 4>,
332                                      <0 20 4>,
333                                      <0 21 4>,
334                                      <0 22 4>,
335                                      <0 23 4>;
336
337                         clocks = <&osc24M>;
338                 };
339
340                 pio: pinctrl@06000800 {
341                         compatible = "allwinner,sun9i-a80-pinctrl";
342                         reg = <0x06000800 0x400>;
343                         interrupts = <0 11 4>,
344                                      <0 15 4>,
345                                      <0 16 4>,
346                                      <0 17 4>,
347                                      <0 120 4>;
348                         clocks = <&apb0_gates 5>;
349                         gpio-controller;
350                         interrupt-controller;
351                         #interrupt-cells = <2>;
352                         #size-cells = <0>;
353                         #gpio-cells = <3>;
354
355                         i2c3_pins_a: i2c3@0 {
356                                 allwinner,pins = "PG10", "PG11";
357                                 allwinner,function = "i2c3";
358                                 allwinner,drive = <0>;
359                                 allwinner,pull = <0>;
360                         };
361
362                         uart0_pins_a: uart0@0 {
363                                 allwinner,pins = "PH12", "PH13";
364                                 allwinner,function = "uart0";
365                                 allwinner,drive = <0>;
366                                 allwinner,pull = <0>;
367                         };
368
369                         uart4_pins_a: uart4@0 {
370                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
371                                 allwinner,function = "uart4";
372                                 allwinner,drive = <0>;
373                                 allwinner,pull = <0>;
374                         };
375                 };
376
377                 uart0: serial@07000000 {
378                         compatible = "snps,dw-apb-uart";
379                         reg = <0x07000000 0x400>;
380                         interrupts = <0 0 4>;
381                         reg-shift = <2>;
382                         reg-io-width = <4>;
383                         clocks = <&apb1_gates 16>;
384                         resets = <&apb1_resets 16>;
385                         status = "disabled";
386                 };
387
388                 uart1: serial@07000400 {
389                         compatible = "snps,dw-apb-uart";
390                         reg = <0x07000400 0x400>;
391                         interrupts = <0 1 4>;
392                         reg-shift = <2>;
393                         reg-io-width = <4>;
394                         clocks = <&apb1_gates 17>;
395                         resets = <&apb1_resets 17>;
396                         status = "disabled";
397                 };
398
399                 uart2: serial@07000800 {
400                         compatible = "snps,dw-apb-uart";
401                         reg = <0x07000800 0x400>;
402                         interrupts = <0 2 4>;
403                         reg-shift = <2>;
404                         reg-io-width = <4>;
405                         clocks = <&apb1_gates 18>;
406                         resets = <&apb1_resets 18>;
407                         status = "disabled";
408                 };
409
410                 uart3: serial@07000c00 {
411                         compatible = "snps,dw-apb-uart";
412                         reg = <0x07000c00 0x400>;
413                         interrupts = <0 3 4>;
414                         reg-shift = <2>;
415                         reg-io-width = <4>;
416                         clocks = <&apb1_gates 19>;
417                         resets = <&apb1_resets 19>;
418                         status = "disabled";
419                 };
420
421                 uart4: serial@07001000 {
422                         compatible = "snps,dw-apb-uart";
423                         reg = <0x07001000 0x400>;
424                         interrupts = <0 4 4>;
425                         reg-shift = <2>;
426                         reg-io-width = <4>;
427                         clocks = <&apb1_gates 20>;
428                         resets = <&apb1_resets 20>;
429                         status = "disabled";
430                 };
431
432                 uart5: serial@07001400 {
433                         compatible = "snps,dw-apb-uart";
434                         reg = <0x07001400 0x400>;
435                         interrupts = <0 5 4>;
436                         reg-shift = <2>;
437                         reg-io-width = <4>;
438                         clocks = <&apb1_gates 21>;
439                         resets = <&apb1_resets 21>;
440                         status = "disabled";
441                 };
442
443                 i2c0: i2c@07002800 {
444                         compatible = "allwinner,sun6i-a31-i2c";
445                         reg = <0x07002800 0x400>;
446                         interrupts = <0 6 4>;
447                         clocks = <&apb1_gates 0>;
448                         resets = <&apb1_resets 0>;
449                         status = "disabled";
450                         #address-cells = <1>;
451                         #size-cells = <0>;
452                 };
453
454                 i2c1: i2c@07002c00 {
455                         compatible = "allwinner,sun6i-a31-i2c";
456                         reg = <0x07002c00 0x400>;
457                         interrupts = <0 7 4>;
458                         clocks = <&apb1_gates 1>;
459                         resets = <&apb1_resets 1>;
460                         status = "disabled";
461                         #address-cells = <1>;
462                         #size-cells = <0>;
463                 };
464
465                 i2c2: i2c@07003000 {
466                         compatible = "allwinner,sun6i-a31-i2c";
467                         reg = <0x07003000 0x400>;
468                         interrupts = <0 8 4>;
469                         clocks = <&apb1_gates 2>;
470                         resets = <&apb1_resets 2>;
471                         status = "disabled";
472                         #address-cells = <1>;
473                         #size-cells = <0>;
474                 };
475
476                 i2c3: i2c@07003400 {
477                         compatible = "allwinner,sun6i-a31-i2c";
478                         reg = <0x07003400 0x400>;
479                         interrupts = <0 9 4>;
480                         clocks = <&apb1_gates 3>;
481                         resets = <&apb1_resets 3>;
482                         status = "disabled";
483                         #address-cells = <1>;
484                         #size-cells = <0>;
485                 };
486
487                 i2c4: i2c@07003800 {
488                         compatible = "allwinner,sun6i-a31-i2c";
489                         reg = <0x07003800 0x400>;
490                         interrupts = <0 10 4>;
491                         clocks = <&apb1_gates 4>;
492                         resets = <&apb1_resets 4>;
493                         status = "disabled";
494                         #address-cells = <1>;
495                         #size-cells = <0>;
496                 };
497
498                 r_wdt: watchdog@08001000 {
499                         compatible = "allwinner,sun6i-a31-wdt";
500                         reg = <0x08001000 0x20>;
501                         interrupts = <0 36 4>;
502                 };
503
504                 r_uart: serial@08002800 {
505                         compatible = "snps,dw-apb-uart";
506                         reg = <0x08002800 0x400>;
507                         interrupts = <0 38 4>;
508                         reg-shift = <2>;
509                         reg-io-width = <4>;
510                         clocks = <&osc24M>;
511                         status = "disabled";
512                 };
513         };
514 };