]> git.kernelconcepts.de Git - karo-tx-linux.git/blob - arch/arm/boot/dts/tegra20.dtsi
Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux...
[karo-tx-linux.git] / arch / arm / boot / dts / tegra20.dtsi
1 /include/ "skeleton.dtsi"
2
3 / {
4         compatible = "nvidia,tegra20";
5         interrupt-parent = <&intc>;
6
7         aliases {
8                 serial0 = &uarta;
9                 serial1 = &uartb;
10                 serial2 = &uartc;
11                 serial3 = &uartd;
12                 serial4 = &uarte;
13         };
14
15         host1x {
16                 compatible = "nvidia,tegra20-host1x", "simple-bus";
17                 reg = <0x50000000 0x00024000>;
18                 interrupts = <0 65 0x04   /* mpcore syncpt */
19                               0 67 0x04>; /* mpcore general */
20                 clocks = <&tegra_car 28>;
21
22                 #address-cells = <1>;
23                 #size-cells = <1>;
24
25                 ranges = <0x54000000 0x54000000 0x04000000>;
26
27                 mpe {
28                         compatible = "nvidia,tegra20-mpe";
29                         reg = <0x54040000 0x00040000>;
30                         interrupts = <0 68 0x04>;
31                         clocks = <&tegra_car 60>;
32                 };
33
34                 vi {
35                         compatible = "nvidia,tegra20-vi";
36                         reg = <0x54080000 0x00040000>;
37                         interrupts = <0 69 0x04>;
38                         clocks = <&tegra_car 100>;
39                 };
40
41                 epp {
42                         compatible = "nvidia,tegra20-epp";
43                         reg = <0x540c0000 0x00040000>;
44                         interrupts = <0 70 0x04>;
45                         clocks = <&tegra_car 19>;
46                 };
47
48                 isp {
49                         compatible = "nvidia,tegra20-isp";
50                         reg = <0x54100000 0x00040000>;
51                         interrupts = <0 71 0x04>;
52                         clocks = <&tegra_car 23>;
53                 };
54
55                 gr2d {
56                         compatible = "nvidia,tegra20-gr2d";
57                         reg = <0x54140000 0x00040000>;
58                         interrupts = <0 72 0x04>;
59                         clocks = <&tegra_car 21>;
60                 };
61
62                 gr3d {
63                         compatible = "nvidia,tegra20-gr3d";
64                         reg = <0x54180000 0x00040000>;
65                         clocks = <&tegra_car 24>;
66                 };
67
68                 dc@54200000 {
69                         compatible = "nvidia,tegra20-dc";
70                         reg = <0x54200000 0x00040000>;
71                         interrupts = <0 73 0x04>;
72                         clocks = <&tegra_car 27>, <&tegra_car 121>;
73                         clock-names = "disp1", "parent";
74
75                         rgb {
76                                 status = "disabled";
77                         };
78                 };
79
80                 dc@54240000 {
81                         compatible = "nvidia,tegra20-dc";
82                         reg = <0x54240000 0x00040000>;
83                         interrupts = <0 74 0x04>;
84                         clocks = <&tegra_car 26>, <&tegra_car 121>;
85                         clock-names = "disp2", "parent";
86
87                         rgb {
88                                 status = "disabled";
89                         };
90                 };
91
92                 hdmi {
93                         compatible = "nvidia,tegra20-hdmi";
94                         reg = <0x54280000 0x00040000>;
95                         interrupts = <0 75 0x04>;
96                         clocks = <&tegra_car 51>, <&tegra_car 117>;
97                         clock-names = "hdmi", "parent";
98                         status = "disabled";
99                 };
100
101                 tvo {
102                         compatible = "nvidia,tegra20-tvo";
103                         reg = <0x542c0000 0x00040000>;
104                         interrupts = <0 76 0x04>;
105                         clocks = <&tegra_car 102>;
106                         status = "disabled";
107                 };
108
109                 dsi {
110                         compatible = "nvidia,tegra20-dsi";
111                         reg = <0x54300000 0x00040000>;
112                         clocks = <&tegra_car 48>;
113                         status = "disabled";
114                 };
115         };
116
117         timer@50004600 {
118                 compatible = "arm,cortex-a9-twd-timer";
119                 reg = <0x50040600 0x20>;
120                 interrupts = <1 13 0x304>;
121                 clocks = <&tegra_car 132>;
122         };
123
124         intc: interrupt-controller {
125                 compatible = "arm,cortex-a9-gic";
126                 reg = <0x50041000 0x1000
127                        0x50040100 0x0100>;
128                 interrupt-controller;
129                 #interrupt-cells = <3>;
130         };
131
132         cache-controller {
133                 compatible = "arm,pl310-cache";
134                 reg = <0x50043000 0x1000>;
135                 arm,data-latency = <5 5 2>;
136                 arm,tag-latency = <4 4 2>;
137                 cache-unified;
138                 cache-level = <2>;
139         };
140
141         timer@60005000 {
142                 compatible = "nvidia,tegra20-timer";
143                 reg = <0x60005000 0x60>;
144                 interrupts = <0 0 0x04
145                               0 1 0x04
146                               0 41 0x04
147                               0 42 0x04>;
148         };
149
150         tegra_car: clock {
151                 compatible = "nvidia,tegra20-car";
152                 reg = <0x60006000 0x1000>;
153                 #clock-cells = <1>;
154         };
155
156         apbdma: dma {
157                 compatible = "nvidia,tegra20-apbdma";
158                 reg = <0x6000a000 0x1200>;
159                 interrupts = <0 104 0x04
160                               0 105 0x04
161                               0 106 0x04
162                               0 107 0x04
163                               0 108 0x04
164                               0 109 0x04
165                               0 110 0x04
166                               0 111 0x04
167                               0 112 0x04
168                               0 113 0x04
169                               0 114 0x04
170                               0 115 0x04
171                               0 116 0x04
172                               0 117 0x04
173                               0 118 0x04
174                               0 119 0x04>;
175                 clocks = <&tegra_car 34>;
176         };
177
178         ahb {
179                 compatible = "nvidia,tegra20-ahb";
180                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
181         };
182
183         gpio: gpio {
184                 compatible = "nvidia,tegra20-gpio";
185                 reg = <0x6000d000 0x1000>;
186                 interrupts = <0 32 0x04
187                               0 33 0x04
188                               0 34 0x04
189                               0 35 0x04
190                               0 55 0x04
191                               0 87 0x04
192                               0 89 0x04>;
193                 #gpio-cells = <2>;
194                 gpio-controller;
195                 #interrupt-cells = <2>;
196                 interrupt-controller;
197         };
198
199         pinmux: pinmux {
200                 compatible = "nvidia,tegra20-pinmux";
201                 reg = <0x70000014 0x10   /* Tri-state registers */
202                        0x70000080 0x20   /* Mux registers */
203                        0x700000a0 0x14   /* Pull-up/down registers */
204                        0x70000868 0xa8>; /* Pad control registers */
205         };
206
207         das {
208                 compatible = "nvidia,tegra20-das";
209                 reg = <0x70000c00 0x80>;
210         };
211         
212         tegra_ac97: ac97 {
213                 compatible = "nvidia,tegra20-ac97";
214                 reg = <0x70002000 0x200>;
215                 interrupts = <0 81 0x04>;
216                 nvidia,dma-request-selector = <&apbdma 12>;
217                 clocks = <&tegra_car 3>;
218                 status = "disabled";
219         };
220
221         tegra_i2s1: i2s@70002800 {
222                 compatible = "nvidia,tegra20-i2s";
223                 reg = <0x70002800 0x200>;
224                 interrupts = <0 13 0x04>;
225                 nvidia,dma-request-selector = <&apbdma 2>;
226                 clocks = <&tegra_car 11>;
227                 status = "disabled";
228         };
229
230         tegra_i2s2: i2s@70002a00 {
231                 compatible = "nvidia,tegra20-i2s";
232                 reg = <0x70002a00 0x200>;
233                 interrupts = <0 3 0x04>;
234                 nvidia,dma-request-selector = <&apbdma 1>;
235                 clocks = <&tegra_car 18>;
236                 status = "disabled";
237         };
238
239         /*
240          * There are two serial driver i.e. 8250 based simple serial
241          * driver and APB DMA based serial driver for higher baudrate
242          * and performace. To enable the 8250 based driver, the compatible
243          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
244          * driver, the comptible is "nvidia,tegra20-hsuart".
245          */
246         uarta: serial@70006000 {
247                 compatible = "nvidia,tegra20-uart";
248                 reg = <0x70006000 0x40>;
249                 reg-shift = <2>;
250                 interrupts = <0 36 0x04>;
251                 nvidia,dma-request-selector = <&apbdma 8>;
252                 clocks = <&tegra_car 6>;
253                 status = "disabled";
254         };
255
256         uartb: serial@70006040 {
257                 compatible = "nvidia,tegra20-uart";
258                 reg = <0x70006040 0x40>;
259                 reg-shift = <2>;
260                 interrupts = <0 37 0x04>;
261                 nvidia,dma-request-selector = <&apbdma 9>;
262                 clocks = <&tegra_car 96>;
263                 status = "disabled";
264         };
265
266         uartc: serial@70006200 {
267                 compatible = "nvidia,tegra20-uart";
268                 reg = <0x70006200 0x100>;
269                 reg-shift = <2>;
270                 interrupts = <0 46 0x04>;
271                 nvidia,dma-request-selector = <&apbdma 10>;
272                 clocks = <&tegra_car 55>;
273                 status = "disabled";
274         };
275
276         uartd: serial@70006300 {
277                 compatible = "nvidia,tegra20-uart";
278                 reg = <0x70006300 0x100>;
279                 reg-shift = <2>;
280                 interrupts = <0 90 0x04>;
281                 nvidia,dma-request-selector = <&apbdma 19>;
282                 clocks = <&tegra_car 65>;
283                 status = "disabled";
284         };
285
286         uarte: serial@70006400 {
287                 compatible = "nvidia,tegra20-uart";
288                 reg = <0x70006400 0x100>;
289                 reg-shift = <2>;
290                 interrupts = <0 91 0x04>;
291                 nvidia,dma-request-selector = <&apbdma 20>;
292                 clocks = <&tegra_car 66>;
293                 status = "disabled";
294         };
295
296         pwm: pwm {
297                 compatible = "nvidia,tegra20-pwm";
298                 reg = <0x7000a000 0x100>;
299                 #pwm-cells = <2>;
300                 clocks = <&tegra_car 17>;
301         };
302
303         rtc {
304                 compatible = "nvidia,tegra20-rtc";
305                 reg = <0x7000e000 0x100>;
306                 interrupts = <0 2 0x04>;
307         };
308
309         i2c@7000c000 {
310                 compatible = "nvidia,tegra20-i2c";
311                 reg = <0x7000c000 0x100>;
312                 interrupts = <0 38 0x04>;
313                 #address-cells = <1>;
314                 #size-cells = <0>;
315                 clocks = <&tegra_car 12>, <&tegra_car 124>;
316                 clock-names = "div-clk", "fast-clk";
317                 status = "disabled";
318         };
319
320         spi@7000c380 {
321                 compatible = "nvidia,tegra20-sflash";
322                 reg = <0x7000c380 0x80>;
323                 interrupts = <0 39 0x04>;
324                 nvidia,dma-request-selector = <&apbdma 11>;
325                 #address-cells = <1>;
326                 #size-cells = <0>;
327                 clocks = <&tegra_car 43>;
328                 status = "disabled";
329         };
330
331         i2c@7000c400 {
332                 compatible = "nvidia,tegra20-i2c";
333                 reg = <0x7000c400 0x100>;
334                 interrupts = <0 84 0x04>;
335                 #address-cells = <1>;
336                 #size-cells = <0>;
337                 clocks = <&tegra_car 54>, <&tegra_car 124>;
338                 clock-names = "div-clk", "fast-clk";
339                 status = "disabled";
340         };
341
342         i2c@7000c500 {
343                 compatible = "nvidia,tegra20-i2c";
344                 reg = <0x7000c500 0x100>;
345                 interrupts = <0 92 0x04>;
346                 #address-cells = <1>;
347                 #size-cells = <0>;
348                 clocks = <&tegra_car 67>, <&tegra_car 124>;
349                 clock-names = "div-clk", "fast-clk";
350                 status = "disabled";
351         };
352
353         i2c@7000d000 {
354                 compatible = "nvidia,tegra20-i2c-dvc";
355                 reg = <0x7000d000 0x200>;
356                 interrupts = <0 53 0x04>;
357                 #address-cells = <1>;
358                 #size-cells = <0>;
359                 clocks = <&tegra_car 47>, <&tegra_car 124>;
360                 clock-names = "div-clk", "fast-clk";
361                 status = "disabled";
362         };
363
364         spi@7000d400 {
365                 compatible = "nvidia,tegra20-slink";
366                 reg = <0x7000d400 0x200>;
367                 interrupts = <0 59 0x04>;
368                 nvidia,dma-request-selector = <&apbdma 15>;
369                 #address-cells = <1>;
370                 #size-cells = <0>;
371                 clocks = <&tegra_car 41>;
372                 status = "disabled";
373         };
374
375         spi@7000d600 {
376                 compatible = "nvidia,tegra20-slink";
377                 reg = <0x7000d600 0x200>;
378                 interrupts = <0 82 0x04>;
379                 nvidia,dma-request-selector = <&apbdma 16>;
380                 #address-cells = <1>;
381                 #size-cells = <0>;
382                 clocks = <&tegra_car 44>;
383                 status = "disabled";
384         };
385
386         spi@7000d800 {
387                 compatible = "nvidia,tegra20-slink";
388                 reg = <0x7000d800 0x200>;
389                 interrupts = <0 83 0x04>;
390                 nvidia,dma-request-selector = <&apbdma 17>;
391                 #address-cells = <1>;
392                 #size-cells = <0>;
393                 clocks = <&tegra_car 46>;
394                 status = "disabled";
395         };
396
397         spi@7000da00 {
398                 compatible = "nvidia,tegra20-slink";
399                 reg = <0x7000da00 0x200>;
400                 interrupts = <0 93 0x04>;
401                 nvidia,dma-request-selector = <&apbdma 18>;
402                 #address-cells = <1>;
403                 #size-cells = <0>;
404                 clocks = <&tegra_car 68>;
405                 status = "disabled";
406         };
407
408         kbc {
409                 compatible = "nvidia,tegra20-kbc";
410                 reg = <0x7000e200 0x100>;
411                 interrupts = <0 85 0x04>;
412                 clocks = <&tegra_car 36>;
413                 status = "disabled";
414         };
415
416         pmc {
417                 compatible = "nvidia,tegra20-pmc";
418                 reg = <0x7000e400 0x400>;
419         };
420
421         memory-controller@7000f000 {
422                 compatible = "nvidia,tegra20-mc";
423                 reg = <0x7000f000 0x024
424                        0x7000f03c 0x3c4>;
425                 interrupts = <0 77 0x04>;
426         };
427
428         iommu {
429                 compatible = "nvidia,tegra20-gart";
430                 reg = <0x7000f024 0x00000018    /* controller registers */
431                        0x58000000 0x02000000>;  /* GART aperture */
432         };
433
434         memory-controller@7000f400 {
435                 compatible = "nvidia,tegra20-emc";
436                 reg = <0x7000f400 0x200>;
437                 #address-cells = <1>;
438                 #size-cells = <0>;
439         };
440
441         phy1: usb-phy@c5000400 {
442                 compatible = "nvidia,tegra20-usb-phy";
443                 reg = <0xc5000400 0x3c00>;
444                 phy_type = "utmi";
445                 nvidia,has-legacy-mode;
446                 clocks = <&tegra_car 22>, <&tegra_car 127>;
447                 clock-names = "phy", "pll_u";
448         };
449
450         phy2: usb-phy@c5004400 {
451                 compatible = "nvidia,tegra20-usb-phy";
452                 reg = <0xc5004400 0x3c00>;
453                 phy_type = "ulpi";
454                 clocks = <&tegra_car 94>, <&tegra_car 127>;
455                 clock-names = "phy", "pll_u";
456         };
457
458         phy3: usb-phy@c5008400 {
459                 compatible = "nvidia,tegra20-usb-phy";
460                 reg = <0xc5008400 0x3C00>;
461                 phy_type = "utmi";
462                 clocks = <&tegra_car 22>, <&tegra_car 127>;
463                 clock-names = "phy", "pll_u";
464         };
465
466         usb@c5000000 {
467                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
468                 reg = <0xc5000000 0x4000>;
469                 interrupts = <0 20 0x04>;
470                 phy_type = "utmi";
471                 nvidia,has-legacy-mode;
472                 clocks = <&tegra_car 22>;
473                 nvidia,needs-double-reset;
474                 nvidia,phy = <&phy1>;
475                 status = "disabled";
476         };
477
478         usb@c5004000 {
479                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
480                 reg = <0xc5004000 0x4000>;
481                 interrupts = <0 21 0x04>;
482                 phy_type = "ulpi";
483                 clocks = <&tegra_car 58>;
484                 nvidia,phy = <&phy2>;
485                 status = "disabled";
486         };
487
488         usb@c5008000 {
489                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
490                 reg = <0xc5008000 0x4000>;
491                 interrupts = <0 97 0x04>;
492                 phy_type = "utmi";
493                 clocks = <&tegra_car 59>;
494                 nvidia,phy = <&phy3>;
495                 status = "disabled";
496         };
497
498         sdhci@c8000000 {
499                 compatible = "nvidia,tegra20-sdhci";
500                 reg = <0xc8000000 0x200>;
501                 interrupts = <0 14 0x04>;
502                 clocks = <&tegra_car 14>;
503                 status = "disabled";
504         };
505
506         sdhci@c8000200 {
507                 compatible = "nvidia,tegra20-sdhci";
508                 reg = <0xc8000200 0x200>;
509                 interrupts = <0 15 0x04>;
510                 clocks = <&tegra_car 9>;
511                 status = "disabled";
512         };
513
514         sdhci@c8000400 {
515                 compatible = "nvidia,tegra20-sdhci";
516                 reg = <0xc8000400 0x200>;
517                 interrupts = <0 19 0x04>;
518                 clocks = <&tegra_car 69>;
519                 status = "disabled";
520         };
521
522         sdhci@c8000600 {
523                 compatible = "nvidia,tegra20-sdhci";
524                 reg = <0xc8000600 0x200>;
525                 interrupts = <0 31 0x04>;
526                 clocks = <&tegra_car 15>;
527                 status = "disabled";
528         };
529
530         cpus {
531                 #address-cells = <1>;
532                 #size-cells = <0>;
533
534                 cpu@0 {
535                         device_type = "cpu";
536                         compatible = "arm,cortex-a9";
537                         reg = <0>;
538                 };
539
540                 cpu@1 {
541                         device_type = "cpu";
542                         compatible = "arm,cortex-a9";
543                         reg = <1>;
544                 };
545         };
546
547         pmu {
548                 compatible = "arm,cortex-a9-pmu";
549                 interrupts = <0 56 0x04
550                               0 57 0x04>;
551         };
552 };