arch/arm/boot/dts/wm8505.dtsi

   1 /*
   2  * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
   3  *
   4  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "wm,wm8505";
  13
  14         cpus {
  15                 cpu@0 {
  16                         compatible = "arm,arm926ejs";
  17                 };
  18         };
  19
  20         soc {
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 compatible = "simple-bus";
  24                 ranges;
  25                 interrupt-parent = <&intc0>;
  26
  27                 intc0: interrupt-controller@d8140000 {
  28                         compatible = "via,vt8500-intc";
  29                         interrupt-controller;
  30                         reg = <0xd8140000 0x10000>;
  31                         #interrupt-cells = <1>;
  32                 };
  33
  34                 /* Secondary IC cascaded to intc0 */
  35                 intc1: interrupt-controller@d8150000 {
  36                         compatible = "via,vt8500-intc";
  37                         interrupt-controller;
  38                         #interrupt-cells = <1>;
  39                         reg = <0xD8150000 0x10000>;
  40                         interrupts = <56 57 58 59 60 61 62 63>;
  41                 };
  42
  43                 gpio: gpio-controller@d8110000 {
  44                         compatible = "wm,wm8505-gpio";
  45                         gpio-controller;
  46                         reg = <0xd8110000 0x10000>;
  47                         #gpio-cells = <3>;
  48                 };
  49
  50                 pmc@d8130000 {
  51                         compatible = "via,vt8500-pmc";
  52                         reg = <0xd8130000 0x1000>;
  53                         clocks {
  54                                 #address-cells = <1>;
  55                                 #size-cells = <0>;
  56
  57                                 ref24: ref24M {
  58                                         #clock-cells = <0>;
  59                                         compatible = "fixed-clock";
  60                                         clock-frequency = <24000000>;
  61                                 };
  62                         };
  63                 };
  64
  65                 timer@d8130100 {
  66                         compatible = "via,vt8500-timer";
  67                         reg = <0xd8130100 0x28>;
  68                         interrupts = <36>;
  69                 };
  70
  71                 ehci@d8007100 {
  72                         compatible = "via,vt8500-ehci";
  73                         reg = <0xd8007100 0x200>;
  74                         interrupts = <43>;
  75                 };
  76
  77                 uhci@d8007300 {
  78                         compatible = "platform-uhci";
  79                         reg = <0xd8007300 0x200>;
  80                         interrupts = <43>;
  81                 };
  82
  83                 fb@d8050800 {
  84                         compatible = "wm,wm8505-fb";
  85                         reg = <0xd8050800 0x200>;
  86                         display = <&display>;
  87                         default-mode = <&mode0>;
  88                 };
  89
  90                 ge_rops@d8050400 {
  91                         compatible = "wm,prizm-ge-rops";
  92                         reg = <0xd8050400 0x100>;
  93                 };
  94
  95                 uart@d8200000 {
  96                         compatible = "via,vt8500-uart";
  97                         reg = <0xd8200000 0x1040>;
  98                         interrupts = <32>;
  99                         clocks = <&ref24>;
 100                 };
 101
 102                 uart@d82b0000 {
 103                         compatible = "via,vt8500-uart";
 104                         reg = <0xd82b0000 0x1040>;
 105                         interrupts = <33>;
 106                         clocks = <&ref24>;
 107                 };
 108
 109                 uart@d8210000 {
 110                         compatible = "via,vt8500-uart";
 111                         reg = <0xd8210000 0x1040>;
 112                         interrupts = <47>;
 113                         clocks = <&ref24>;
 114                 };
 115
 116                 uart@d82c0000 {
 117                         compatible = "via,vt8500-uart";
 118                         reg = <0xd82c0000 0x1040>;
 119                         interrupts = <50>;
 120                         clocks = <&ref24>;
 121                 };
 122
 123                 uart@d8370000 {
 124                         compatible = "via,vt8500-uart";
 125                         reg = <0xd8370000 0x1040>;
 126                         interrupts = <31>;
 127                         clocks = <&ref24>;
 128                 };
 129
 130                 uart@d8380000 {
 131                         compatible = "via,vt8500-uart";
 132                         reg = <0xd8380000 0x1040>;
 133                         interrupts = <30>;
 134                         clocks = <&ref24>;
 135                 };
 136
 137                 rtc@d8100000 {
 138                         compatible = "via,vt8500-rtc";
 139                         reg = <0xd8100000 0x10000>;
 140                         interrupts = <48>;
 141                 };
 142         };
 143 };