2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm-offsets.h>
20 #ifdef CONFIG_SPL_BUILD
37 .word 0x12345678 /* now 16*4=64 */
39 ldr pc, _undefined_instruction
40 ldr pc, _software_interrupt
41 ldr pc, _prefetch_abort
47 _undefined_instruction: .word undefined_instruction
48 _software_interrupt: .word software_interrupt
49 _prefetch_abort: .word prefetch_abort
50 _data_abort: .word data_abort
51 _not_used: .word not_used
54 _pad: .word 0x12345678 /* now 16*4=64 */
55 #endif /* CONFIG_SPL_BUILD */
57 .balignl 16,0xdeadbeef
59 *************************************************************************
61 * Startup Code (reset vector)
63 * do important init only if we don't start from memory!
64 * setup Memory and board specific bits prior to relocation.
65 * relocate armboot to ram
68 *************************************************************************
72 /* IRQ stack memory (calculated at run-time) */
73 .globl IRQ_STACK_START
77 /* IRQ stack memory (calculated at run-time) */
78 .globl FIQ_STACK_START
83 /* IRQ stack memory (calculated at run-time) + 8 bytes */
84 .globl IRQ_STACK_START_IN
89 * the actual reset code
94 * set the cpu to SVC32 mode
101 /* the mask ROM code should have PLL and others stable */
102 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
108 /*------------------------------------------------------------------------------*/
110 .globl c_runtime_cpu_setup
116 *************************************************************************
118 * CPU_init_critical registers
120 * setup important registers
121 * setup memory timing
123 *************************************************************************
125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
128 * flush v4 I/D caches
131 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
132 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
135 * disable MMU stuff and caches
137 mrc p15, 0, r0, c1, c0, 0
138 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
139 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
140 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
141 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
142 mcr p15, 0, r0, c1, c0, 0
145 * Jump to board specific initialization... The Mask ROM will have already initialized
146 * basic memory. Go here to bump up clock rate and handle wake up conditions.
148 mov ip, lr /* persevere link reg across call */
149 bl lowlevel_init /* go setup pll,mux,memory */
150 mov lr, ip /* restore link */
151 mov pc, lr /* back to my caller */
152 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
154 #ifndef CONFIG_SPL_BUILD
156 *************************************************************************
160 *************************************************************************
165 #define S_FRAME_SIZE 72
187 #define MODE_SVC 0x13
191 * use bad_save_user_regs for abort/prefetch/undef/swi ...
192 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
195 .macro bad_save_user_regs
196 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
197 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
199 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
200 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
201 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
205 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
206 mov r0, sp @ save current stack into r0 (param register)
209 .macro irq_save_user_regs
210 sub sp, sp, #S_FRAME_SIZE
211 stmia sp, {r0 - r12} @ Calling r0-r12
212 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
213 stmdb r8, {sp, lr}^ @ Calling SP, LR
214 str lr, [r8, #0] @ Save calling PC
216 str r6, [r8, #4] @ Save CPSR
217 str r0, [r8, #8] @ Save OLD_R0
221 .macro irq_restore_user_regs
222 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
224 ldr lr, [sp, #S_PC] @ Get PC
225 add sp, sp, #S_FRAME_SIZE
226 subs pc, lr, #4 @ return & move spsr_svc into cpsr
230 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
232 str lr, [r13] @ save caller lr in position 0 of saved stack
233 mrs lr, spsr @ get the spsr
234 str lr, [r13, #4] @ save spsr in position 1 of saved stack
236 mov r13, #MODE_SVC @ prepare SVC-Mode
238 msr spsr, r13 @ switch modes, make sure moves will execute
239 mov lr, pc @ capture return pc
240 movs pc, lr @ jump to next instruction & switch modes.
243 .macro get_bad_stack_swi
244 sub r13, r13, #4 @ space on current stack for scratch reg.
245 str r0, [r13] @ save R0's value.
246 ldr r0, IRQ_STACK_START_IN @ get data regions start
247 str lr, [r0] @ save caller lr in position 0 of saved stack
248 mrs lr, spsr @ get the spsr
249 str lr, [r0, #4] @ save spsr in position 1 of saved stack
250 ldr lr, [r0] @ restore lr
251 ldr r0, [r13] @ restore r0
252 add r13, r13, #4 @ pop stack entry
255 .macro get_irq_stack @ setup IRQ stack
256 ldr sp, IRQ_STACK_START
259 .macro get_fiq_stack @ setup FIQ stack
260 ldr sp, FIQ_STACK_START
262 #endif /* CONFIG_SPL_BUILD */
267 #ifdef CONFIG_SPL_BUILD
270 bl hang /* hang and never return */
271 #else /* !CONFIG_SPL_BUILD */
273 undefined_instruction:
276 bl do_undefined_instruction
282 bl do_software_interrupt
302 #ifdef CONFIG_USE_IRQ
309 irq_restore_user_regs
314 /* someone ought to write a more effiction fiq_save_user_regs */
317 irq_restore_user_regs
334 #endif /* CONFIG_SPL_BUILD */