2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 /* 1 second delay should be plenty of time for block reset. */
42 #define RESET_MAX_TIMEOUT 1000000
44 #define MXS_BLOCK_SFTRST (1 << 31)
45 #define MXS_BLOCK_CLKGATE (1 << 30)
47 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
48 inline void lowlevel_init(void) {}
50 void reset_cpu(ulong ignored) __attribute__((noreturn));
52 void reset_cpu(ulong ignored)
54 struct mxs_rtc_regs *rtc_regs =
55 (struct mxs_rtc_regs *)MXS_RTC_BASE;
56 struct mxs_lcdif_regs *lcdif_regs =
57 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
60 * Shut down the LCD controller as it interferes with BootROM boot mode
63 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
65 /* Wait 1 uS before doing the actual watchdog reset */
66 writel(1, &rtc_regs->hw_rtc_watchdog);
67 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
69 /* Endless loop, reset will exit from here */
74 void enable_caches(void)
76 #ifndef CONFIG_SYS_ICACHE_OFF
79 #ifndef CONFIG_SYS_DCACHE_OFF
84 #define MX28_HW_DIGCTL_MICROSECONDS (void *)0x8001c0c0
86 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
89 uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
91 /* Wait for at least one microsecond for the bit mask to be set */
92 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
93 if ((readl(®->reg) & mask) == mask) {
94 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
104 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
107 uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
109 /* Wait for at least one microsecond for the bit mask to be cleared */
110 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
111 if ((readl(®->reg) & mask) == 0) {
112 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
122 int mxs_reset_block(struct mxs_register_32 *reg)
125 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
127 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
128 printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
129 reg, readl(®->reg));
134 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
137 writel(MXS_BLOCK_SFTRST, ®->reg_set);
139 /* Wait for CLKGATE being set */
140 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
141 printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n",
142 reg, readl(®->reg));
147 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
149 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
150 printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
151 reg, readl(®->reg));
156 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
158 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
159 printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n",
160 reg, readl(®->reg));
167 void mx28_fixup_vt(uint32_t start_addr)
169 uint32_t *vt = (uint32_t *)0x20;
172 for (i = 0; i < 8; i++)
173 vt[i] = start_addr + (4 * i);
176 #ifdef CONFIG_ARCH_MISC_INIT
177 int arch_misc_init(void)
179 mx28_fixup_vt(gd->relocaddr);
184 #ifdef CONFIG_ARCH_CPU_INIT
185 int arch_cpu_init(void)
187 struct mxs_clkctrl_regs *clkctrl_regs =
188 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
189 extern uint32_t _start;
191 mx28_fixup_vt((uint32_t)&_start);
196 /* Clear bypass bit */
197 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
198 &clkctrl_regs->hw_clkctrl_clkseq_set);
200 /* Set GPMI clock to ref_gpmi / 12 */
201 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
202 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
207 * Configure GPIO unit
211 #ifdef CONFIG_APBH_DMA
220 #if defined(CONFIG_DISPLAY_CPUINFO)
221 static const char *get_cpu_type(void)
223 struct mxs_digctl_regs *digctl_regs =
224 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
226 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
227 case HW_DIGCTL_CHIPID_MX28:
234 static const char *get_cpu_rev(void)
236 struct mxs_digctl_regs *digctl_regs =
237 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
238 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
240 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
241 case HW_DIGCTL_CHIPID_MX28:
253 int print_cpuinfo(void)
255 struct mxs_spl_data *data = (struct mxs_spl_data *)
256 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
258 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
261 mxc_get_clock(MXC_ARM_CLK) / 1000000);
262 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
267 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
269 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
270 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
271 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
272 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
277 * Initializes on-chip ethernet controllers.
279 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
280 int cpu_eth_init(bd_t *bis)
282 struct mxs_clkctrl_regs *clkctrl_regs =
283 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
285 /* Turn on ENET clocks */
286 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
287 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
289 /* Set up ENET PLL for 50 MHz */
290 /* Power on ENET PLL */
291 writel(CLKCTRL_PLL2CTRL0_POWER,
292 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
297 * Enable pad output; must be done BEFORE enabling PLL
298 * according to i.MX28 Ref. Manual Rev. 1, 2010 p. 883
300 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
302 /* Gate on ENET PLL */
303 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
304 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
310 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
313 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
315 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
319 void mx28_adjust_mac(int dev_id, unsigned char *mac)
320 __attribute__((weak, alias("__mx28_adjust_mac")));
322 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
324 #define MXS_OCOTP_MAX_TIMEOUT 1000000
325 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
327 struct mxs_ocotp_regs *ocotp_regs =
328 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
333 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
335 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
336 MXS_OCOTP_MAX_TIMEOUT)) {
337 printf("MXS FEC: Can't get MAC from OCOTP\n");
341 data = readl(&ocotp_regs->hw_ocotp_cust0);
343 mac[2] = (data >> 24) & 0xff;
344 mac[3] = (data >> 16) & 0xff;
345 mac[4] = (data >> 8) & 0xff;
346 mac[5] = data & 0xff;
347 mx28_adjust_mac(dev_id, mac);
350 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
356 int mxs_dram_init(void)
358 struct mxs_spl_data *data = (struct mxs_spl_data *)
359 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
361 if (data->mem_dram_size == 0) {
363 "Error, the RAM size passed up from SPL is 0!\n");
367 gd->ram_size = data->mem_dram_size;
372 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,