arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

   1 /*
   2  * Freescale i.MX28 Boot PMIC init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <config.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30
  31 #include "mxs_init.h"
  32
  33 #ifdef CONFIG_SYS_SPL_VDDD_VAL
  34 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
  35 #else
  36 #define VDDD_VAL        1350
  37 #endif
  38 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
  39 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
  40 #else
  41 #define VDDIO_VAL       3300
  42 #endif
  43 #ifdef CONFIG_SYS_SPL_VDDA_VAL
  44 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
  45 #else
  46 #define VDDA_VAL        1800
  47 #endif
  48 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
  49 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
  50 #else
  51 #define VDDMEM_VAL      1500
  52 #endif
  53
  54 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
  55 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
  56 #else
  57 #define VDDD_BO_VAL     150
  58 #endif
  59 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
  60 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
  61 #else
  62 #define VDDIO_BO_VAL    150
  63 #endif
  64 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
  65 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
  66 #else
  67 #define VDDA_BO_VAL     175
  68 #endif
  69 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
  70 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
  71 #else
  72 #define VDDMEM_BO_VAL   25
  73 #endif
  74
  75 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
  76 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
  77 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
  78 #endif
  79 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
  80 #else
  81 /* Brownout default at 3V */
  82 #define BATT_BO_VAL     ((3000 - 2400) / 40)
  83 #endif
  84
  85 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
  86 static const int fixed_batt_supply = 1;
  87 #else
  88 static const int fixed_batt_supply;
  89 #endif
  90
  91 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
  92
  93 static void mxs_power_clock2xtal(void)
  94 {
  95         struct mxs_clkctrl_regs *clkctrl_regs =
  96                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  97
  98         /* Set XTAL as CPU reference clock */
  99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
 101 }
 102
 103 static void mxs_power_clock2pll(void)
 104 {
 105         struct mxs_clkctrl_regs *clkctrl_regs =
 106                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 107
 108         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
 109                         CLKCTRL_PLL0CTRL0_POWER);
 110         early_delay(100);
 111         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
 112                         CLKCTRL_CLKSEQ_BYPASS_CPU);
 113 }
 114
 115 static int mxs_power_wait_rtc_stat(u32 mask)
 116 {
 117         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
 118         u32 val;
 119         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 120
 121         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
 122                 early_delay(1);
 123                 if (timeout-- < 0)
 124                         break;
 125         }
 126         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
 127 }
 128
 129 static int mxs_power_set_auto_restart(int on)
 130 {
 131         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 132
 133         /*
 134          * Due to the hardware design bug of mx28 EVK-A
 135          * we need to set the AUTO_RESTART bit.
 136          */
 137         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
 138                 return 1;
 139
 140         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
 141                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
 142                 return 0;
 143
 144         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 145                 return 1;
 146
 147         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
 148                         !on * RTC_PERSISTENT0_AUTO_RESTART,
 149                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
 150         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 151                 return 1;
 152
 153         return 0;
 154 }
 155
 156 static void mxs_power_set_linreg(void)
 157 {
 158         /* Set linear regulator 25mV below switching converter */
 159         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 160                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 161                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 162
 163         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 164                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 165                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 166
 167         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 168                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 169                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 170 }
 171
 172 static int mxs_get_batt_volt(void)
 173 {
 174         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 175
 176         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 177         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 178         volt *= 8;
 179         return volt;
 180 }
 181
 182 static int mxs_is_batt_ready(void)
 183 {
 184         return (mxs_get_batt_volt() >= 3600);
 185 }
 186
 187 static int mxs_is_batt_good(void)
 188 {
 189         uint32_t volt = mxs_get_batt_volt();
 190
 191         if ((volt >= 2400) && (volt <= 4300))
 192                 return 1;
 193
 194         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 195                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 196                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 197         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 198                 &power_regs->hw_power_5vctrl_clr);
 199
 200         clrsetbits_le32(&power_regs->hw_power_charge,
 201                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 202                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 203
 204         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 205         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 206                 &power_regs->hw_power_5vctrl_clr);
 207
 208         early_delay(500000);
 209
 210         volt = mxs_get_batt_volt();
 211
 212         if (volt >= 3500)
 213                 return 0;
 214
 215         if (volt >= 2400)
 216                 return 1;
 217
 218         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 219                 &power_regs->hw_power_charge_clr);
 220         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 221
 222         return 0;
 223 }
 224
 225 static void mxs_power_setup_5v_detect(void)
 226 {
 227         /* Start 5V detection */
 228         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 229                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 230                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 231                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 232 }
 233
 234 static void mxs_src_power_init(void)
 235 {
 236         /* Improve efficieny and reduce transient ripple */
 237         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 238                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 239
 240         clrsetbits_le32(&power_regs->hw_power_dclimits,
 241                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 242                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 243
 244         if (!fixed_batt_supply) {
 245                 /* FIXME: This requires the LRADC to be set up! */
 246                 setbits_le32(&power_regs->hw_power_battmonitor,
 247                         POWER_BATTMONITOR_EN_BATADJ);
 248         } else {
 249                 clrbits_le32(&power_regs->hw_power_battmonitor,
 250                         POWER_BATTMONITOR_EN_BATADJ);
 251         }
 252
 253         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 254         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 255                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 256                         POWER_LOOPCTRL_RCSCALE_THRESH |
 257                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 258
 259         clrsetbits_le32(&power_regs->hw_power_minpwr,
 260                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 261
 262         if (!fixed_batt_supply) {
 263                 /* 5V to battery handoff ... FIXME */
 264                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 265                 early_delay(30);
 266                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 267         }
 268 }
 269
 270 static void mxs_power_init_4p2_params(void)
 271 {
 272         /* Setup 4P2 parameters */
 273         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 274                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 275                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 276
 277         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 278                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 279                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 280
 281         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 282                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 283                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 284                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
 285
 286         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 287                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 288                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 289 }
 290
 291 static void mxs_enable_4p2_dcdc_input(int xfer)
 292 {
 293         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 294         uint32_t prev_5v_brnout, prev_5v_droop;
 295
 296         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 297                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 298         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 299                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 300
 301         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 302         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 303                 &power_regs->hw_power_reset);
 304
 305         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 306
 307         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 308                         POWER_5VCTRL_ENABLE_DCDC)) {
 309                 return;
 310         }
 311
 312         /*
 313          * Recording orignal values that will be modified temporarlily
 314          * to handle a chip bug. See chip errata for CQ ENGR00115837
 315          */
 316         tmp = readl(&power_regs->hw_power_5vctrl);
 317         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 318         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 319
 320         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 321
 322         /*
 323          * Disable mechanisms that get erroneously tripped by when setting
 324          * the DCDC4P2 EN_DCDC
 325          */
 326         clrbits_le32(&power_regs->hw_power_5vctrl,
 327                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 328                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 329
 330         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 331
 332         if (xfer) {
 333                 setbits_le32(&power_regs->hw_power_5vctrl,
 334                                 POWER_5VCTRL_DCDC_XFER);
 335                 early_delay(20);
 336                 clrbits_le32(&power_regs->hw_power_5vctrl,
 337                                 POWER_5VCTRL_DCDC_XFER);
 338
 339                 setbits_le32(&power_regs->hw_power_5vctrl,
 340                                 POWER_5VCTRL_ENABLE_DCDC);
 341         } else {
 342                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 343                                 POWER_DCDC4P2_ENABLE_DCDC);
 344         }
 345
 346         early_delay(25);
 347
 348         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 349                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 350
 351         if (vbus_5vdetect)
 352                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 353
 354         if (!pwd_bo)
 355                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 356
 357         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 358                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 359                         &power_regs->hw_power_ctrl_clr);
 360
 361         if (prev_5v_brnout) {
 362                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 363                         &power_regs->hw_power_5vctrl_set);
 364                 writel(POWER_RESET_UNLOCK_KEY,
 365                         &power_regs->hw_power_reset);
 366         } else {
 367                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 368                         &power_regs->hw_power_5vctrl_clr);
 369                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 370                         &power_regs->hw_power_reset);
 371         }
 372
 373         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 374                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 375                         &power_regs->hw_power_ctrl_clr);
 376
 377         if (prev_5v_droop)
 378                 clrbits_le32(&power_regs->hw_power_ctrl,
 379                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 380         else
 381                 setbits_le32(&power_regs->hw_power_ctrl,
 382                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 383 }
 384
 385 static void mxs_power_init_4p2_regulator(void)
 386 {
 387         uint32_t tmp, tmp2;
 388
 389         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 390
 391         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 392
 393         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 394                 &power_regs->hw_power_5vctrl_clr);
 395         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 396
 397         /* Power up the 4p2 rail and logic/control */
 398         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 399                 &power_regs->hw_power_5vctrl_clr);
 400
 401         /*
 402          * Start charging up the 4p2 capacitor. We ramp of this charge
 403          * gradually to avoid large inrush current from the 5V cable which can
 404          * cause transients/problems
 405          */
 406         mxs_enable_4p2_dcdc_input(0);
 407
 408         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 409                 /*
 410                  * If we arrived here, we were unable to recover from mx23 chip
 411                  * errata 5837. 4P2 is disabled and sufficient battery power is
 412                  * not present. Exiting to not enable DCDC power during 5V
 413                  * connected state.
 414                  */
 415                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 416                         POWER_DCDC4P2_ENABLE_DCDC);
 417                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 418                         &power_regs->hw_power_5vctrl_set);
 419                 hang();
 420         }
 421
 422         /*
 423          * Here we set the 4p2 brownout level to something very close to 4.2V.
 424          * We then check the brownout status. If the brownout status is false,
 425          * the voltage is already close to the target voltage of 4.2V so we
 426          * can go ahead and set the 4P2 current limit to our max target limit.
 427          * If the brownout status is true, we need to ramp us the current limit
 428          * so that we don't cause large inrush current issues. We step up the
 429          * current limit until the brownout status is false or until we've
 430          * reached our maximum defined 4p2 current limit.
 431          */
 432         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 433                         POWER_DCDC4P2_BO_MASK,
 434                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 435
 436         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 437                 setbits_le32(&power_regs->hw_power_5vctrl,
 438                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 439         } else {
 440                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 441                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 442                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 443                 while (tmp < 0x3f) {
 444                         if (!(readl(&power_regs->hw_power_sts) &
 445                                         POWER_STS_DCDC_4P2_BO)) {
 446                                 tmp = readl(&power_regs->hw_power_5vctrl);
 447                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 448                                 early_delay(100);
 449                                 writel(tmp, &power_regs->hw_power_5vctrl);
 450                                 break;
 451                         } else {
 452                                 tmp++;
 453                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 454                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 455                                 tmp2 |= tmp <<
 456                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 457                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 458                                 early_delay(100);
 459                         }
 460                 }
 461         }
 462
 463         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 464         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 465 }
 466
 467 static void mxs_power_init_dcdc_4p2_source(void)
 468 {
 469         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 470                 POWER_DCDC4P2_ENABLE_DCDC)) {
 471                 hang();
 472         }
 473
 474         mxs_enable_4p2_dcdc_input(1);
 475
 476         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 477                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 478                         POWER_DCDC4P2_ENABLE_DCDC);
 479                 writel(POWER_5VCTRL_ENABLE_DCDC,
 480                         &power_regs->hw_power_5vctrl_clr);
 481                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 482                         &power_regs->hw_power_5vctrl_set);
 483         }
 484 }
 485
 486 static void mxs_power_enable_4p2(void)
 487 {
 488         uint32_t vdddctrl, vddactrl, vddioctrl;
 489         uint32_t tmp;
 490
 491         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 492         vddactrl = readl(&power_regs->hw_power_vddactrl);
 493         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 494
 495         setbits_le32(&power_regs->hw_power_vdddctrl,
 496                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 497                 POWER_VDDDCTRL_PWDN_BRNOUT);
 498
 499         setbits_le32(&power_regs->hw_power_vddactrl,
 500                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 501                 POWER_VDDACTRL_PWDN_BRNOUT);
 502
 503         setbits_le32(&power_regs->hw_power_vddioctrl,
 504                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 505
 506         mxs_power_init_4p2_params();
 507         mxs_power_init_4p2_regulator();
 508
 509         /* Shutdown battery (none present) */
 510         if (!mxs_is_batt_ready()) {
 511                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 512                                 POWER_DCDC4P2_BO_MASK);
 513                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
 514                                 &power_regs->hw_power_ctrl_clr);
 515                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 516                                 &power_regs->hw_power_ctrl_clr);
 517         }
 518
 519         mxs_power_init_dcdc_4p2_source();
 520
 521         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 522         early_delay(20);
 523         writel(vddactrl, &power_regs->hw_power_vddactrl);
 524         early_delay(20);
 525         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 526
 527         /*
 528          * Check if FET is enabled on either powerout and if so,
 529          * disable load.
 530          */
 531         tmp = 0;
 532         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 533                         POWER_VDDDCTRL_DISABLE_FET);
 534         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 535                         POWER_VDDACTRL_DISABLE_FET);
 536         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 537                         POWER_VDDIOCTRL_DISABLE_FET);
 538         if (tmp)
 539                 writel(POWER_CHARGE_ENABLE_LOAD,
 540                         &power_regs->hw_power_charge_clr);
 541 }
 542
 543 static void mxs_boot_valid_5v(void)
 544 {
 545         /*
 546          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 547          * disconnect event. FIXME
 548          */
 549         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 550                 &power_regs->hw_power_5vctrl_set);
 551
 552         /* Configure polarity to check for 5V disconnection. */
 553         writel(POWER_CTRL_POLARITY_VBUSVALID |
 554                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 555                 &power_regs->hw_power_ctrl_clr);
 556
 557         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 558                 &power_regs->hw_power_ctrl_clr);
 559
 560         mxs_power_enable_4p2();
 561 }
 562
 563 static void mxs_powerdown(void)
 564 {
 565         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 566         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 567                 &power_regs->hw_power_reset);
 568 }
 569
 570 static void mxs_batt_boot(void)
 571 {
 572         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 573         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
 574
 575         clrbits_le32(&power_regs->hw_power_dcdc4p2,
 576                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
 577         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
 578
 579         /* 5V to battery handoff. */
 580         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 581         early_delay(30);
 582         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 583
 584         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 585
 586         clrsetbits_le32(&power_regs->hw_power_minpwr,
 587                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 588
 589         mxs_power_set_linreg();
 590
 591         clrbits_le32(&power_regs->hw_power_vdddctrl,
 592                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
 593
 594         clrbits_le32(&power_regs->hw_power_vddactrl,
 595                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
 596
 597         clrbits_le32(&power_regs->hw_power_vddioctrl,
 598                 POWER_VDDIOCTRL_DISABLE_FET);
 599
 600         setbits_le32(&power_regs->hw_power_5vctrl,
 601                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 602
 603         setbits_le32(&power_regs->hw_power_5vctrl,
 604                 POWER_5VCTRL_ENABLE_DCDC);
 605
 606         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 607                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 608                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 609 }
 610
 611 static void mxs_handle_5v_conflict(void)
 612 {
 613         uint32_t tmp;
 614
 615         setbits_le32(&power_regs->hw_power_vddioctrl,
 616                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 617
 618         for (;;) {
 619                 tmp = readl(&power_regs->hw_power_sts);
 620
 621                 if (tmp & POWER_STS_VDDIO_BO) {
 622                         /*
 623                          * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
 624                          * unreliable
 625                          */
 626                         mxs_powerdown();
 627                         break;
 628                 }
 629
 630                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 631                         mxs_boot_valid_5v();
 632                         break;
 633                 } else {
 634                         mxs_powerdown();
 635                         break;
 636                 }
 637
 638                 if (tmp & POWER_STS_PSWITCH_MASK) {
 639                         mxs_batt_boot();
 640                         break;
 641                 }
 642         }
 643 }
 644
 645 static void mxs_5v_boot(void)
 646 {
 647         /*
 648          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 649          * but their implementation always returns 1 so we omit it here.
 650          */
 651         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 652                 mxs_boot_valid_5v();
 653                 return;
 654         }
 655
 656         early_delay(1000);
 657         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 658                 mxs_boot_valid_5v();
 659                 return;
 660         }
 661
 662         mxs_handle_5v_conflict();
 663 }
 664
 665 static void mxs_fixed_batt_boot(void)
 666 {
 667         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 668
 669         setbits_le32(&power_regs->hw_power_5vctrl,
 670                 POWER_5VCTRL_PWDN_5VBRNOUT |
 671                 POWER_5VCTRL_ENABLE_DCDC |
 672                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
 673                 POWER_5VCTRL_PWDN_5VBRNOUT |
 674                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 675
 676         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 677
 678         clrbits_le32(&power_regs->hw_power_vdddctrl,
 679                 POWER_VDDDCTRL_DISABLE_FET |
 680                 POWER_VDDDCTRL_ENABLE_LINREG |
 681                 POWER_VDDDCTRL_DISABLE_STEPPING);
 682
 683         clrbits_le32(&power_regs->hw_power_vddactrl,
 684                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 685                 POWER_VDDACTRL_DISABLE_STEPPING);
 686
 687         clrbits_le32(&power_regs->hw_power_vddioctrl,
 688                 POWER_VDDIOCTRL_DISABLE_FET |
 689                 POWER_VDDIOCTRL_DISABLE_STEPPING);
 690
 691         /* Stop 5V detection */
 692         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
 693                 &power_regs->hw_power_5vctrl_clr);
 694 }
 695
 696 static void mxs_init_batt_bo(void)
 697 {
 698         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 699                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 700                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 701
 702         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 703         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 704 }
 705
 706 static void mxs_switch_vddd_to_dcdc_source(void)
 707 {
 708         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 709                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 710                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 711
 712         clrbits_le32(&power_regs->hw_power_vdddctrl,
 713                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 714                 POWER_VDDDCTRL_DISABLE_STEPPING);
 715 }
 716
 717 static void mxs_power_configure_power_source(void)
 718 {
 719         struct mxs_lradc_regs *lradc_regs =
 720                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 721
 722         mxs_src_power_init();
 723
 724         if (!fixed_batt_supply) {
 725                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 726                         if (mxs_is_batt_ready()) {
 727                                 /* 5V source detected, good battery detected. */
 728                                 mxs_batt_boot();
 729                         } else {
 730                                 if (!mxs_is_batt_good()) {
 731                                         /* 5V source detected, bad battery detected. */
 732                                         writel(LRADC_CONVERSION_AUTOMATIC,
 733                                                 &lradc_regs->hw_lradc_conversion_clr);
 734                                         clrbits_le32(&power_regs->hw_power_battmonitor,
 735                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
 736                                 }
 737                                 mxs_5v_boot();
 738                         }
 739                 } else {
 740                         /* 5V not detected, booting from battery. */
 741                         mxs_batt_boot();
 742                 }
 743         } else {
 744                 mxs_fixed_batt_boot();
 745         }
 746
 747         mxs_power_clock2pll();
 748
 749         mxs_init_batt_bo();
 750
 751         mxs_switch_vddd_to_dcdc_source();
 752 }
 753
 754 static void mxs_enable_output_rail_protection(void)
 755 {
 756         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 757                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 758
 759         setbits_le32(&power_regs->hw_power_vdddctrl,
 760                         POWER_VDDDCTRL_PWDN_BRNOUT);
 761
 762         setbits_le32(&power_regs->hw_power_vddactrl,
 763                         POWER_VDDACTRL_PWDN_BRNOUT);
 764
 765         setbits_le32(&power_regs->hw_power_vddioctrl,
 766                         POWER_VDDIOCTRL_PWDN_BRNOUT);
 767 }
 768
 769 static int mxs_get_vddio_power_source_off(void)
 770 {
 771         uint32_t tmp;
 772
 773         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
 774                 !(readl(&power_regs->hw_power_5vctrl) &
 775                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
 776
 777                 tmp = readl(&power_regs->hw_power_vddioctrl);
 778                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
 779                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 780                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 781                                 return 1;
 782                         }
 783                 }
 784
 785                 if (!(readl(&power_regs->hw_power_5vctrl) &
 786                         POWER_5VCTRL_ENABLE_DCDC)) {
 787                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 788                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 789                                 return 1;
 790                         }
 791                 }
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int mxs_get_vddd_power_source_off(void)
 798 {
 799         uint32_t tmp;
 800
 801         tmp = readl(&power_regs->hw_power_vdddctrl);
 802         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
 803                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 804                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 805                         return 1;
 806                 }
 807         }
 808
 809         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 810                 if (!(readl(&power_regs->hw_power_5vctrl) &
 811                         POWER_5VCTRL_ENABLE_DCDC)) {
 812                         return 1;
 813                 }
 814         }
 815
 816         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
 817                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 818                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
 819                         return 1;
 820                 }
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int mxs_get_vdda_power_source_off(void)
 827 {
 828         uint32_t tmp;
 829
 830         tmp = readl(&power_regs->hw_power_vddactrl);
 831         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
 832                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 833                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
 834                         return 1;
 835                 }
 836         }
 837
 838         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 839                 if (!(readl(&power_regs->hw_power_5vctrl) &
 840                         POWER_5VCTRL_ENABLE_DCDC)) {
 841                         return 1;
 842                 }
 843         }
 844
 845         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
 846                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 847                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
 848                         return 1;
 849                 }
 850         }
 851
 852         return 0;
 853 }
 854
 855 struct mxs_vddx_cfg {
 856         uint32_t                *reg;
 857         uint8_t                 step_mV;
 858         uint16_t                lowest_mV;
 859         uint16_t                highest_mV;
 860         int                     (*powered_by_linreg)(void);
 861         uint32_t                trg_mask;
 862         uint32_t                bo_irq;
 863         uint32_t                bo_enirq;
 864         uint32_t                bo_offset_mask;
 865         uint32_t                bo_offset_offset;
 866 };
 867
 868 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
 869         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 870                                         hw_power_vddioctrl),
 871         .step_mV                = 50,
 872         .lowest_mV              = 2800,
 873         .highest_mV             = 3600,
 874         .powered_by_linreg      = mxs_get_vddio_power_source_off,
 875         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
 876         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
 877         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
 878         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
 879         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
 880 };
 881
 882 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
 883         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 884                                         hw_power_vdddctrl),
 885         .step_mV                = 25,
 886         .lowest_mV              = 800,
 887         .highest_mV             = 1575,
 888         .powered_by_linreg      = mxs_get_vddd_power_source_off,
 889         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
 890         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
 891         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
 892         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
 893         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
 894 };
 895
 896 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
 897         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 898                                         hw_power_vddactrl),
 899         .step_mV                = 50,
 900         .lowest_mV              = 2800,
 901         .highest_mV             = 3600,
 902         .powered_by_linreg      = mxs_get_vdda_power_source_off,
 903         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
 904         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
 905         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
 906         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
 907         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
 908 };
 909
 910 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
 911         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 912                                         hw_power_vddmemctrl),
 913         .step_mV                = 25,
 914         .lowest_mV              = 1100,
 915         .highest_mV             = 1750,
 916         .bo_offset_mask         = POWER_VDDMEMCTRL_BO_OFFSET_MASK,
 917         .bo_offset_offset       = POWER_VDDMEMCTRL_BO_OFFSET_OFFSET,
 918 };
 919
 920 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 921                                 uint32_t new_target, uint32_t new_brownout)
 922 {
 923         uint32_t cur_target, diff, bo_int = 0;
 924         int powered_by_linreg = 0;
 925         int adjust_up;
 926
 927         if (new_target < cfg->lowest_mV)
 928                 new_target = cfg->lowest_mV;
 929         if (new_target > cfg->highest_mV)
 930                 new_target = cfg->highest_mV;
 931
 932         new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
 933
 934         cur_target = readl(cfg->reg);
 935         cur_target &= cfg->trg_mask;
 936         cur_target *= cfg->step_mV;
 937         cur_target += cfg->lowest_mV;
 938
 939         adjust_up = new_target > cur_target;
 940         if (cfg->powered_by_linreg)
 941                 powered_by_linreg = cfg->powered_by_linreg();
 942
 943         if (adjust_up) {
 944                 if (powered_by_linreg) {
 945                         bo_int = readl(cfg->reg);
 946                         clrbits_le32(cfg->reg, cfg->bo_enirq);
 947                 }
 948                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
 949         }
 950
 951         do {
 952                 if (abs(new_target - cur_target) > 100) {
 953                         if (adjust_up)
 954                                 diff = cur_target + 100;
 955                         else
 956                                 diff = cur_target - 100;
 957                 } else {
 958                         diff = new_target;
 959                 }
 960
 961                 diff -= cfg->lowest_mV;
 962                 diff /= cfg->step_mV;
 963
 964                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
 965
 966                 if (powered_by_linreg ||
 967                         (readl(&power_regs->hw_power_sts) &
 968                                 POWER_STS_VDD5V_GT_VDDIO)) {
 969                         early_delay(500);
 970                 } else {
 971                         while (!(readl(&power_regs->hw_power_sts) &
 972                                         POWER_STS_DC_OK)) {
 973
 974                         }
 975                 }
 976
 977                 cur_target = readl(cfg->reg);
 978                 cur_target &= cfg->trg_mask;
 979                 cur_target *= cfg->step_mV;
 980                 cur_target += cfg->lowest_mV;
 981         } while (new_target > cur_target);
 982
 983         if (adjust_up && powered_by_linreg) {
 984                 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
 985                 if (bo_int & cfg->bo_enirq)
 986                         setbits_le32(cfg->reg, cfg->bo_enirq);
 987         }
 988
 989         clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
 990                         new_brownout << cfg->bo_offset_offset);
 991 }
 992
 993 static void mxs_setup_batt_detect(void)
 994 {
 995         mxs_lradc_init();
 996         mxs_lradc_enable_batt_measurement();
 997         early_delay(10);
 998 }
 999
1000 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1001 #define auto_restart 1
1002 #else
1003 #define auto_restart 0
1004 #endif
1005
1006 void mxs_power_init(void)
1007 {
1008         mxs_power_clock2xtal();
1009         if (mxs_power_set_auto_restart(auto_restart)) {
1010                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1011         }
1012         mxs_power_set_linreg();
1013
1014         if (!fixed_batt_supply) {
1015                 mxs_power_setup_5v_detect();
1016                 mxs_setup_batt_detect();
1017         }
1018
1019         mxs_power_configure_power_source();
1020         mxs_enable_output_rail_protection();
1021
1022         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1023         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1024         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1025 #if VDDMEM_VAL > 0
1026         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1027
1028         setbits_le32(&power_regs->hw_power_vddmemctrl,
1029                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1030         early_delay(500);
1031         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1032                 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1033 #else
1034         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1035                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1036 #endif
1037         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1038                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1039                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1040                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1041         if (!fixed_batt_supply)
1042                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1043                         &power_regs->hw_power_5vctrl_set);
1044 }
1045
1046 #ifdef  CONFIG_SPL_MX28_PSWITCH_WAIT
1047 void mxs_power_wait_pswitch(void)
1048 {
1049         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1050                 ;
1051 }
1052 #endif