2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_SPL_VDDD_VAL
18 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
22 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
23 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
25 #define VDDIO_VAL 3300
27 #ifdef CONFIG_SYS_SPL_VDDA_VAL
28 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
32 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
33 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
35 #define VDDMEM_VAL 1700
38 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
39 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
41 #define VDDD_BO_VAL 150
43 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
44 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
46 #define VDDIO_BO_VAL 150
48 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
49 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
51 #define VDDA_BO_VAL 175
53 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
54 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
56 #define VDDMEM_BO_VAL 25
59 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
60 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
61 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
63 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
65 /* Brownout default at 3V */
66 #define BATT_BO_VAL ((3000 - 2400) / 40)
69 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
70 static const int fixed_batt_supply = 1;
72 static const int fixed_batt_supply;
75 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
78 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
80 * This function switches the CPU core clock from PLL to 24MHz XTAL
81 * oscilator. This is necessary if the PLL is being reconfigured to
82 * prevent crash of the CPU core.
84 static void mxs_power_clock2xtal(void)
86 struct mxs_clkctrl_regs *clkctrl_regs =
87 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
89 /* Set XTAL as CPU reference clock */
90 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
91 &clkctrl_regs->hw_clkctrl_clkseq_set);
95 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
97 * This function switches the CPU core clock from 24MHz XTAL oscilator
98 * to PLL. This can only be called once the PLL has re-locked and once
99 * the PLL is stable after reconfiguration.
101 static void mxs_power_clock2pll(void)
103 struct mxs_clkctrl_regs *clkctrl_regs =
104 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
106 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
107 CLKCTRL_PLL0CTRL0_POWER);
109 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
110 CLKCTRL_CLKSEQ_BYPASS_CPU);
113 static int mxs_power_wait_rtc_stat(u32 mask)
115 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
117 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
119 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
124 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
128 * mxs_power_set_auto_restart() - Set the auto-restart bit
130 * This function ungates the RTC block and sets the AUTO_RESTART
131 * bit to work around a design bug on MX28EVK Rev. A .
133 static int mxs_power_set_auto_restart(int on)
135 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
137 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
140 /* Do nothing if flag already set */
141 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
144 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
145 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
148 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
151 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
152 !on * RTC_PERSISTENT0_AUTO_RESTART,
153 !!on * RTC_PERSISTENT0_AUTO_RESTART);
154 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
161 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
163 * This function configures the VDDIO, VDDA and VDDD linear regulators output
164 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
165 * converter. This is the recommended setting for the case where we use both
166 * linear regulators and DC-DC converter to power the VDDIO rail.
168 static void mxs_power_set_linreg(void)
170 /* Set linear regulator 25mV below switching converter */
171 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
172 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
173 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
175 clrsetbits_le32(&power_regs->hw_power_vddactrl,
176 POWER_VDDACTRL_LINREG_OFFSET_MASK,
177 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
179 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
180 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
181 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
185 * mxs_get_batt_volt() - Measure battery input voltage
187 * This function retrieves the battery input voltage and returns it.
189 static int mxs_get_batt_volt(void)
191 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
193 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
194 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
200 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
202 * This function checks if the battery input voltage is higher than 3.6V and
203 * therefore allows the system to successfully boot using this power source.
205 static int mxs_is_batt_ready(void)
207 return (mxs_get_batt_volt() >= 3600);
211 * mxs_is_batt_good() - Test if battery is operational at all
213 * This function starts recharging the battery and tests if the input current
214 * provided by the 5V input recharging the battery is also sufficient to power
215 * the DC-DC converter.
217 static int mxs_is_batt_good(void)
219 uint32_t volt = mxs_get_batt_volt();
221 if ((volt >= 2400) && (volt <= 4300))
224 clrsetbits_le32(&power_regs->hw_power_5vctrl,
225 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
226 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
227 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
228 &power_regs->hw_power_5vctrl_clr);
230 clrsetbits_le32(&power_regs->hw_power_charge,
231 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
232 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
234 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
235 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
236 &power_regs->hw_power_5vctrl_clr);
240 volt = mxs_get_batt_volt();
242 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
243 &power_regs->hw_power_charge_clr);
244 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
256 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
258 * This function enables the 5V detection comparator and sets the 5V valid
259 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
260 * under high load, the voltage drop on the 5V input won't be so critical
261 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
262 * converter and thus making the system crash.
264 static void mxs_power_setup_5v_detect(void)
266 /* Start 5V detection */
267 clrsetbits_le32(&power_regs->hw_power_5vctrl,
268 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
269 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
270 POWER_5VCTRL_PWRUP_VBUS_CMPS);
274 * mxs_src_power_init() - Preconfigure the power block
276 * This function configures reasonable values for the DC-DC control loop
277 * and battery monitor.
279 static void mxs_src_power_init(void)
281 /* Improve efficieny and reduce transient ripple */
282 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
283 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
285 clrsetbits_le32(&power_regs->hw_power_dclimits,
286 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
287 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
289 if (!fixed_batt_supply) {
290 /* FIXME: This requires the LRADC to be set up! */
291 setbits_le32(&power_regs->hw_power_battmonitor,
292 POWER_BATTMONITOR_EN_BATADJ);
294 clrbits_le32(&power_regs->hw_power_battmonitor,
295 POWER_BATTMONITOR_EN_BATADJ);
298 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
299 clrsetbits_le32(&power_regs->hw_power_loopctrl,
300 POWER_LOOPCTRL_EN_RCSCALE_MASK,
301 POWER_LOOPCTRL_RCSCALE_THRESH |
302 POWER_LOOPCTRL_EN_RCSCALE_8X);
304 clrsetbits_le32(&power_regs->hw_power_minpwr,
305 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
307 if (!fixed_batt_supply) {
308 /* 5V to battery handoff ... FIXME */
309 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
311 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
316 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
318 * This function configures the necessary parameters for the 4P2 linear
319 * regulator to supply the DC-DC converter from 5V input.
321 static void mxs_power_init_4p2_params(void)
323 /* Setup 4P2 parameters */
324 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
325 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
326 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
328 clrsetbits_le32(&power_regs->hw_power_5vctrl,
329 POWER_5VCTRL_HEADROOM_ADJ_MASK,
330 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
332 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
333 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
334 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
335 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
337 clrsetbits_le32(&power_regs->hw_power_5vctrl,
338 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
339 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
343 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
344 * @xfer: Select if the input shall be enabled or disabled
346 * This function enables or disables the 4P2 input into the DC-DC converter.
348 static void mxs_enable_4p2_dcdc_input(int xfer)
350 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
351 uint32_t prev_5v_brnout, prev_5v_droop;
353 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
354 POWER_5VCTRL_PWDN_5VBRNOUT;
355 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
356 POWER_CTRL_ENIRQ_VDD5V_DROOP;
358 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
359 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
360 &power_regs->hw_power_reset);
362 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
364 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
365 POWER_5VCTRL_ENABLE_DCDC)) {
370 * Recording orignal values that will be modified temporarlily
371 * to handle a chip bug. See chip errata for CQ ENGR00115837
373 tmp = readl(&power_regs->hw_power_5vctrl);
374 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
375 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
377 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
380 * Disable mechanisms that get erroneously tripped by when setting
381 * the DCDC4P2 EN_DCDC
383 clrbits_le32(&power_regs->hw_power_5vctrl,
384 POWER_5VCTRL_VBUSVALID_5VDETECT |
385 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
387 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
390 setbits_le32(&power_regs->hw_power_5vctrl,
391 POWER_5VCTRL_DCDC_XFER);
393 clrbits_le32(&power_regs->hw_power_5vctrl,
394 POWER_5VCTRL_DCDC_XFER);
396 setbits_le32(&power_regs->hw_power_5vctrl,
397 POWER_5VCTRL_ENABLE_DCDC);
399 setbits_le32(&power_regs->hw_power_dcdc4p2,
400 POWER_DCDC4P2_ENABLE_DCDC);
405 clrsetbits_le32(&power_regs->hw_power_5vctrl,
406 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
409 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
412 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
414 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
415 writel(POWER_CTRL_VBUS_VALID_IRQ,
416 &power_regs->hw_power_ctrl_clr);
418 if (prev_5v_brnout) {
419 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
420 &power_regs->hw_power_5vctrl_set);
421 writel(POWER_RESET_UNLOCK_KEY,
422 &power_regs->hw_power_reset);
424 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
425 &power_regs->hw_power_5vctrl_clr);
426 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
427 &power_regs->hw_power_reset);
430 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
431 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
432 &power_regs->hw_power_ctrl_clr);
435 clrbits_le32(&power_regs->hw_power_ctrl,
436 POWER_CTRL_ENIRQ_VDD5V_DROOP);
438 setbits_le32(&power_regs->hw_power_ctrl,
439 POWER_CTRL_ENIRQ_VDD5V_DROOP);
443 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
445 * This function enables the 4P2 regulator and switches the DC-DC converter
446 * to use the 4P2 input.
448 static void mxs_power_init_4p2_regulator(void)
452 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
454 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
456 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
457 &power_regs->hw_power_5vctrl_clr);
458 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
460 /* Power up the 4p2 rail and logic/control */
461 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
462 &power_regs->hw_power_5vctrl_clr);
465 * Start charging up the 4p2 capacitor. We ramp of this charge
466 * gradually to avoid large inrush current from the 5V cable which can
467 * cause transients/problems
469 mxs_enable_4p2_dcdc_input(0);
471 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
473 * If we arrived here, we were unable to recover from mx23 chip
474 * errata 5837. 4P2 is disabled and sufficient battery power is
475 * not present. Exiting to not enable DCDC power during 5V
478 clrbits_le32(&power_regs->hw_power_dcdc4p2,
479 POWER_DCDC4P2_ENABLE_DCDC);
480 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
481 &power_regs->hw_power_5vctrl_set);
486 * Here we set the 4p2 brownout level to something very close to 4.2V.
487 * We then check the brownout status. If the brownout status is false,
488 * the voltage is already close to the target voltage of 4.2V so we
489 * can go ahead and set the 4P2 current limit to our max target limit.
490 * If the brownout status is true, we need to ramp up the current limit
491 * so that we don't cause large inrush current issues. We step up the
492 * current limit until the brownout status is false or until we've
493 * reached our maximum defined 4p2 current limit.
495 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
496 POWER_DCDC4P2_BO_MASK,
497 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
499 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
500 setbits_le32(&power_regs->hw_power_5vctrl,
501 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
503 tmp = (readl(&power_regs->hw_power_5vctrl) &
504 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
505 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
507 if (!(readl(&power_regs->hw_power_sts) &
508 POWER_STS_DCDC_4P2_BO)) {
509 tmp = readl(&power_regs->hw_power_5vctrl);
510 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
512 writel(tmp, &power_regs->hw_power_5vctrl);
516 tmp2 = readl(&power_regs->hw_power_5vctrl);
517 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
519 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
520 writel(tmp2, &power_regs->hw_power_5vctrl);
526 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
527 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
531 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
533 * This function configures the DC-DC converter to be supplied from the 4P2
536 static void mxs_power_init_dcdc_4p2_source(void)
538 if (!(readl(&power_regs->hw_power_dcdc4p2) &
539 POWER_DCDC4P2_ENABLE_DCDC)) {
543 mxs_enable_4p2_dcdc_input(1);
545 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
546 clrbits_le32(&power_regs->hw_power_dcdc4p2,
547 POWER_DCDC4P2_ENABLE_DCDC);
548 writel(POWER_5VCTRL_ENABLE_DCDC,
549 &power_regs->hw_power_5vctrl_clr);
550 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
551 &power_regs->hw_power_5vctrl_set);
556 * mxs_power_enable_4p2() - Power up the 4P2 regulator
558 * This function drives the process of powering up the 4P2 linear regulator
559 * and switching the DC-DC converter input over to the 4P2 linear regulator.
561 static void mxs_power_enable_4p2(void)
563 uint32_t vdddctrl, vddactrl, vddioctrl;
566 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
567 vddactrl = readl(&power_regs->hw_power_vddactrl);
568 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
570 setbits_le32(&power_regs->hw_power_vdddctrl,
571 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
572 POWER_VDDDCTRL_PWDN_BRNOUT);
574 setbits_le32(&power_regs->hw_power_vddactrl,
575 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
576 POWER_VDDACTRL_PWDN_BRNOUT);
578 setbits_le32(&power_regs->hw_power_vddioctrl,
579 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
581 mxs_power_init_4p2_params();
582 mxs_power_init_4p2_regulator();
584 /* Shutdown battery (none present) */
585 if (!mxs_is_batt_ready()) {
586 clrbits_le32(&power_regs->hw_power_dcdc4p2,
587 POWER_DCDC4P2_BO_MASK);
588 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
589 &power_regs->hw_power_ctrl_clr);
590 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
591 &power_regs->hw_power_ctrl_clr);
594 mxs_power_init_dcdc_4p2_source();
596 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
598 writel(vddactrl, &power_regs->hw_power_vddactrl);
600 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
603 * Check if FET is enabled on either powerout and if so,
607 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
608 POWER_VDDDCTRL_DISABLE_FET);
609 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
610 POWER_VDDACTRL_DISABLE_FET);
611 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
612 POWER_VDDIOCTRL_DISABLE_FET);
614 writel(POWER_CHARGE_ENABLE_LOAD,
615 &power_regs->hw_power_charge_clr);
619 * mxs_boot_valid_5v() - Boot from 5V supply
621 * This function configures the power block to boot from valid 5V input.
622 * This is called only if the 5V is reliable and can properly supply the
623 * CPU. This function proceeds to configure the 4P2 converter to be supplied
626 static void mxs_boot_valid_5v(void)
629 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
630 * disconnect event. FIXME
632 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
633 &power_regs->hw_power_5vctrl_set);
635 /* Configure polarity to check for 5V disconnection. */
636 writel(POWER_CTRL_POLARITY_VBUSVALID |
637 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
638 &power_regs->hw_power_ctrl_clr);
640 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
641 &power_regs->hw_power_ctrl_clr);
643 mxs_power_enable_4p2();
647 * mxs_powerdown() - Shut down the system
649 * This function powers down the CPU completely.
651 static void mxs_powerdown(void)
653 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
654 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
655 &power_regs->hw_power_reset);
659 * mxs_batt_boot() - Configure the power block to boot from battery input
661 * This function configures the power block to boot from the battery voltage
664 static void mxs_batt_boot(void)
666 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
667 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
669 clrbits_le32(&power_regs->hw_power_dcdc4p2,
670 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
671 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
673 /* 5V to battery handoff. */
674 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
676 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
678 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
680 clrsetbits_le32(&power_regs->hw_power_minpwr,
681 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
683 mxs_power_set_linreg();
685 clrbits_le32(&power_regs->hw_power_vdddctrl,
686 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
688 clrbits_le32(&power_regs->hw_power_vddactrl,
689 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
691 clrbits_le32(&power_regs->hw_power_vddioctrl,
692 POWER_VDDIOCTRL_DISABLE_FET);
694 setbits_le32(&power_regs->hw_power_5vctrl,
695 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
697 setbits_le32(&power_regs->hw_power_5vctrl,
698 POWER_5VCTRL_ENABLE_DCDC);
700 clrsetbits_le32(&power_regs->hw_power_5vctrl,
701 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
702 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
704 mxs_power_enable_4p2();
708 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
710 * This function tests if the 5V input can reliably supply the system. If it
711 * can, then proceed to configuring the system to boot from 5V source, otherwise
712 * try booting from battery supply. If we can not boot from battery supply
713 * either, shut down the system.
715 static void mxs_handle_5v_conflict(void)
719 setbits_le32(&power_regs->hw_power_vddioctrl,
720 POWER_VDDIOCTRL_BO_OFFSET_MASK);
723 tmp = readl(&power_regs->hw_power_sts);
725 if (tmp & POWER_STS_VDDIO_BO) {
727 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
734 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
742 if (tmp & POWER_STS_PSWITCH_MASK) {
750 * mxs_5v_boot() - Configure the power block to boot from 5V input
752 * This function handles configuration of the power block when supplied by
755 static void mxs_5v_boot(void)
758 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
759 * but their implementation always returns 1 so we omit it here.
761 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
767 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
772 mxs_handle_5v_conflict();
776 * mxs_init_batt_bo() - Configure battery brownout threshold
778 * This function configures the battery input brownout threshold. The value
779 * at which the battery brownout happens is configured to 3.0V in the code.
781 static void mxs_fixed_batt_boot(void)
783 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
785 setbits_le32(&power_regs->hw_power_5vctrl,
786 POWER_5VCTRL_ENABLE_DCDC |
787 POWER_5VCTRL_ILIMIT_EQ_ZERO |
788 POWER_5VCTRL_PWDN_5VBRNOUT |
789 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
791 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
793 clrbits_le32(&power_regs->hw_power_vdddctrl,
794 POWER_VDDDCTRL_DISABLE_FET |
795 POWER_VDDDCTRL_ENABLE_LINREG |
796 POWER_VDDDCTRL_DISABLE_STEPPING);
798 clrbits_le32(&power_regs->hw_power_vddactrl,
799 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
800 POWER_VDDACTRL_DISABLE_STEPPING);
802 clrbits_le32(&power_regs->hw_power_vddioctrl,
803 POWER_VDDIOCTRL_DISABLE_FET |
804 POWER_VDDIOCTRL_DISABLE_STEPPING);
806 /* Stop 5V detection */
807 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
808 &power_regs->hw_power_5vctrl_clr);
811 static void mxs_init_batt_bo(void)
813 clrsetbits_le32(&power_regs->hw_power_battmonitor,
814 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
815 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
817 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
818 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
822 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
824 * This function turns off the VDDD linear regulator and therefore makes
825 * the VDDD rail be supplied only by the DC-DC converter.
827 static void mxs_switch_vddd_to_dcdc_source(void)
829 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
830 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
831 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
833 clrbits_le32(&power_regs->hw_power_vdddctrl,
834 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
835 POWER_VDDDCTRL_DISABLE_STEPPING);
839 * mxs_power_configure_power_source() - Configure power block source
841 * This function is the core of the power configuration logic. The function
842 * selects the power block input source and configures the whole power block
843 * accordingly. After the configuration is complete and the system is stable
844 * again, the function switches the CPU clock source back to PLL. Finally,
845 * the function switches the voltage rails to DC-DC converter.
847 static void mxs_power_configure_power_source(void)
849 struct mxs_lradc_regs *lradc_regs =
850 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
852 mxs_src_power_init();
854 if (!fixed_batt_supply) {
855 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
856 if (mxs_is_batt_ready()) {
857 /* 5V source detected, good battery detected. */
860 if (!mxs_is_batt_good()) {
861 /* 5V source detected, bad battery detected. */
862 writel(LRADC_CONVERSION_AUTOMATIC,
863 &lradc_regs->hw_lradc_conversion_clr);
864 clrbits_le32(&power_regs->hw_power_battmonitor,
865 POWER_BATTMONITOR_BATT_VAL_MASK);
870 /* 5V not detected, booting from battery. */
874 mxs_fixed_batt_boot();
877 mxs_power_clock2pll();
881 mxs_switch_vddd_to_dcdc_source();
883 #ifdef CONFIG_SOC_MX23
884 /* Fire up the VDDMEM LinReg now that we're all set. */
885 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
886 &power_regs->hw_power_vddmemctrl);
891 * mxs_enable_output_rail_protection() - Enable power rail protection
893 * This function enables overload protection on the power rails. This is
894 * triggered if the power rails' voltage drops rapidly due to overload and
895 * in such case, the supply to the powerrail is cut-off, protecting the
896 * CPU from damage. Note that under such condition, the system will likely
897 * crash or misbehave.
899 static void mxs_enable_output_rail_protection(void)
901 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
902 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
904 setbits_le32(&power_regs->hw_power_vdddctrl,
905 POWER_VDDDCTRL_PWDN_BRNOUT);
907 setbits_le32(&power_regs->hw_power_vddactrl,
908 POWER_VDDACTRL_PWDN_BRNOUT);
910 setbits_le32(&power_regs->hw_power_vddioctrl,
911 POWER_VDDIOCTRL_PWDN_BRNOUT);
915 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
917 * This function tests if the VDDIO rail is supplied by linear regulator
918 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
919 * returns 0 if powered by the DC-DC converter.
921 static int mxs_get_vddio_power_source_off(void)
925 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
926 !(readl(&power_regs->hw_power_5vctrl) &
927 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
929 tmp = readl(&power_regs->hw_power_vddioctrl);
930 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
931 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
932 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
937 if (!(readl(&power_regs->hw_power_5vctrl) &
938 POWER_5VCTRL_ENABLE_DCDC)) {
939 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
940 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
950 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
952 * This function tests if the VDDD rail is supplied by linear regulator
953 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
954 * returns 0 if powered by the DC-DC converter.
956 static int mxs_get_vddd_power_source_off(void)
960 tmp = readl(&power_regs->hw_power_vdddctrl);
961 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
962 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
963 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
968 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
969 if (!(readl(&power_regs->hw_power_5vctrl) &
970 POWER_5VCTRL_ENABLE_DCDC)) {
975 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
976 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
977 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
985 static int mxs_get_vdda_power_source_off(void)
989 tmp = readl(&power_regs->hw_power_vddactrl);
990 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
991 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
992 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
997 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
998 if (!(readl(&power_regs->hw_power_5vctrl) &
999 POWER_5VCTRL_ENABLE_DCDC)) {
1004 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1005 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1006 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1014 struct mxs_vddx_cfg {
1018 uint16_t highest_mV;
1019 int (*powered_by_linreg)(void);
1023 uint32_t bo_offset_mask;
1024 uint32_t bo_offset_offset;
1029 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1031 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1032 .reg = POWER_REG(hw_power_vddioctrl),
1033 #if defined(CONFIG_SOC_MX23)
1040 .powered_by_linreg = mxs_get_vddio_power_source_off,
1041 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1042 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1043 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1044 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1045 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1050 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1051 .reg = POWER_REG(hw_power_vdddctrl),
1055 .powered_by_linreg = mxs_get_vddd_power_source_off,
1056 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1057 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1058 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1059 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1060 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1065 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1066 .reg = POWER_REG(hw_power_vddactrl),
1070 .powered_by_linreg = mxs_get_vdda_power_source_off,
1071 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1072 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1073 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1074 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1075 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1080 #ifdef CONFIG_SOC_MX23
1081 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1082 .reg = POWER_REG(hw_power_vddmemctrl),
1086 .powered_by_linreg = NULL,
1087 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1090 .bo_offset_mask = 0,
1091 .bo_offset_offset = 0,
1096 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1097 * @cfg: Configuration data of the DC-DC converter rail
1098 * @new_target: New target voltage of the DC-DC converter rail
1099 * @new_brownout: New brownout trigger voltage
1101 * This function configures the output voltage on the DC-DC converter rail.
1102 * The rail is selected by the @cfg argument. The new voltage target is
1103 * selected by the @new_target and the voltage is specified in mV. The
1104 * new brownout value is selected by the @new_brownout argument and the
1105 * value is also in mV.
1107 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1108 uint32_t new_target, uint32_t bo_offset)
1110 uint32_t cur_target, diff, bo_int = 0;
1111 int powered_by_linreg = 0;
1114 if (new_target < cfg->lowest_mV) {
1115 new_target = cfg->lowest_mV;
1117 if (new_target > cfg->highest_mV) {
1118 new_target = cfg->highest_mV;
1121 if (new_target - bo_offset < cfg->bo_min_mV) {
1122 bo_offset = new_target - cfg->bo_min_mV;
1123 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1124 bo_offset = new_target - cfg->bo_max_mV;
1127 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1129 cur_target = readl(cfg->reg);
1130 cur_target &= cfg->trg_mask;
1131 cur_target *= cfg->step_mV;
1132 cur_target += cfg->lowest_mV;
1134 adjust_up = new_target > cur_target;
1135 if (cfg->powered_by_linreg)
1136 powered_by_linreg = cfg->powered_by_linreg();
1138 if (adjust_up && cfg->bo_irq) {
1139 if (powered_by_linreg) {
1140 bo_int = readl(&power_regs->hw_power_ctrl);
1141 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1143 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1147 if (abs(new_target - cur_target) > 100) {
1149 diff = cur_target + 100;
1151 diff = cur_target - 100;
1156 diff -= cfg->lowest_mV;
1157 diff /= cfg->step_mV;
1159 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1161 if (powered_by_linreg ||
1162 (readl(&power_regs->hw_power_sts) &
1163 POWER_STS_VDD5V_GT_VDDIO)) {
1166 while (!(readl(&power_regs->hw_power_sts) &
1172 cur_target = readl(cfg->reg);
1173 cur_target &= cfg->trg_mask;
1174 cur_target *= cfg->step_mV;
1175 cur_target += cfg->lowest_mV;
1176 } while (new_target > cur_target);
1179 if (adjust_up && powered_by_linreg) {
1180 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1181 if (bo_int & cfg->bo_enirq)
1182 writel(cfg->bo_enirq,
1183 &power_regs->hw_power_ctrl_set);
1186 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1187 bo_offset << cfg->bo_offset_offset);
1192 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1194 * This function starts and configures the LRADC block. This allows the
1195 * power initialization code to measure battery voltage and based on this
1196 * knowledge, decide whether to boot at all, boot from battery or boot
1199 static void mxs_setup_batt_detect(void)
1202 mxs_lradc_enable_batt_measurement();
1207 * mxs_ungate_power() - Ungate the POWER block
1209 * This function ungates clock to the power block. In case the power block
1210 * was still gated at this point, it will not be possible to configure the
1211 * block and therefore the power initialization would fail. This function
1212 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1214 static void mxs_ungate_power(void)
1216 #ifdef CONFIG_SOC_MX23
1217 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1221 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1222 #define auto_restart 1
1224 #define auto_restart 0
1228 * mxs_power_init() - The power block init main function
1230 * This function calls all the power block initialization functions in
1231 * proper sequence to start the power block.
1233 void mxs_power_init(void)
1237 mxs_power_clock2xtal();
1238 if (mxs_power_set_auto_restart(auto_restart)) {
1239 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1241 mxs_power_set_linreg();
1243 if (!fixed_batt_supply) {
1244 mxs_power_setup_5v_detect();
1245 mxs_setup_batt_detect();
1248 mxs_power_configure_power_source();
1249 mxs_enable_output_rail_protection();
1251 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1252 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1253 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1254 #ifdef CONFIG_SOC_MX23
1255 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1257 setbits_le32(&power_regs->hw_power_vddmemctrl,
1258 POWER_VDDMEMCTRL_ENABLE_LINREG);
1260 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1261 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1263 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1264 POWER_VDDMEMCTRL_ENABLE_LINREG);
1266 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1267 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1268 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1269 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1270 if (!fixed_batt_supply)
1271 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1272 &power_regs->hw_power_5vctrl_set);
1275 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1277 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1279 * This function waits until the power-switch was pressed to start booting
1282 void mxs_power_wait_pswitch(void)
1284 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))