2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
21 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
32 #define VDDIO_VAL 3300
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
42 #define VDDMEM_VAL 1700
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
48 #define VDDD_BO_VAL 150
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
53 #define VDDIO_BO_VAL 150
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
58 #define VDDA_BO_VAL 175
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
63 #define VDDMEM_BO_VAL 25
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
70 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL ((3000 - 2400) / 40)
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
79 static const int fixed_batt_supply;
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
85 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
87 * This function switches the CPU core clock from PLL to 24MHz XTAL
88 * oscilator. This is necessary if the PLL is being reconfigured to
89 * prevent crash of the CPU core.
91 static void mxs_power_clock2xtal(void)
93 struct mxs_clkctrl_regs *clkctrl_regs =
94 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
96 debug("SPL: Switching CPU clock to 24MHz XTAL\n");
98 /* Set XTAL as CPU reference clock */
99 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100 &clkctrl_regs->hw_clkctrl_clkseq_set);
104 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
106 * This function switches the CPU core clock from 24MHz XTAL oscilator
107 * to PLL. This can only be called once the PLL has re-locked and once
108 * the PLL is stable after reconfiguration.
110 static void mxs_power_clock2pll(void)
112 struct mxs_clkctrl_regs *clkctrl_regs =
113 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
115 debug("SPL: Switching CPU core clock source to PLL\n");
118 * TODO: Are we really? It looks like we turn on PLL0, but we then
119 * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120 * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121 * introduce some instability (causing the CPU core to hang). Maybe
122 * we aren't giving PLL0 enough time to stabilise?
124 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
125 CLKCTRL_PLL0CTRL0_POWER);
129 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130 * wait on the PLL0 LOCK bit?
132 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
133 CLKCTRL_CLKSEQ_BYPASS_CPU);
136 static int mxs_power_wait_rtc_stat(u32 mask)
138 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
140 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
142 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
147 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
151 * mxs_power_set_auto_restart() - Set the auto-restart bit
153 * This function ungates the RTC block and sets the AUTO_RESTART
154 * bit to work around a design bug on MX28EVK Rev. A .
156 static int mxs_power_set_auto_restart(int on)
158 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
160 debug("SPL: Setting auto-restart bit\n");
162 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
165 /* Do nothing if flag already set */
166 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
169 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
173 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
176 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177 !on * RTC_PERSISTENT0_AUTO_RESTART,
178 !!on * RTC_PERSISTENT0_AUTO_RESTART);
179 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
186 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
188 * This function configures the VDDIO, VDDA and VDDD linear regulators output
189 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190 * converter. This is the recommended setting for the case where we use both
191 * linear regulators and DC-DC converter to power the VDDIO rail.
193 static void mxs_power_set_linreg(void)
195 /* Set linear regulator 25mV below switching converter */
196 debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
201 debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202 clrsetbits_le32(&power_regs->hw_power_vddactrl,
203 POWER_VDDACTRL_LINREG_OFFSET_MASK,
204 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
206 debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
213 * mxs_get_batt_volt() - Measure battery input voltage
215 * This function retrieves the battery input voltage and returns it.
217 static int mxs_get_batt_volt(void)
219 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
221 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
225 debug("SPL: Battery Voltage = %dmV\n", volt);
230 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
232 * This function checks if the battery input voltage is higher than 3.6V and
233 * therefore allows the system to successfully boot using this power source.
235 static int mxs_is_batt_ready(void)
237 return (mxs_get_batt_volt() >= 3600);
241 * mxs_is_batt_good() - Test if battery is operational at all
243 * This function starts recharging the battery and tests if the input current
244 * provided by the 5V input recharging the battery is also sufficient to power
245 * the DC-DC converter.
247 static int mxs_is_batt_good(void)
249 uint32_t volt = mxs_get_batt_volt();
251 if ((volt >= 2400) && (volt <= 4300)) {
252 debug("SPL: Battery is good\n");
256 clrsetbits_le32(&power_regs->hw_power_5vctrl,
257 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260 &power_regs->hw_power_5vctrl_clr);
262 clrsetbits_le32(&power_regs->hw_power_charge,
263 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
266 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268 &power_regs->hw_power_5vctrl_clr);
272 volt = mxs_get_batt_volt();
275 debug("SPL: Battery Voltage too high\n");
280 debug("SPL: Battery is good\n");
284 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285 &power_regs->hw_power_charge_clr);
286 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
294 debug("SPL: Battery Voltage too low\n");
299 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
301 * This function enables the 5V detection comparator and sets the 5V valid
302 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303 * under high load, the voltage drop on the 5V input won't be so critical
304 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305 * converter and thus making the system crash.
307 static void mxs_power_setup_5v_detect(void)
309 /* Start 5V detection */
310 debug("SPL: Starting 5V input detection comparator\n");
311 clrsetbits_le32(&power_regs->hw_power_5vctrl,
312 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314 POWER_5VCTRL_PWRUP_VBUS_CMPS);
318 * mxs_src_power_init() - Preconfigure the power block
320 * This function configures reasonable values for the DC-DC control loop
321 * and battery monitor.
323 static void mxs_src_power_init(void)
325 debug("SPL: Pre-Configuring power block\n");
327 /* Improve efficieny and reduce transient ripple */
328 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
329 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
331 clrsetbits_le32(&power_regs->hw_power_dclimits,
332 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
333 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
335 if (!fixed_batt_supply) {
336 /* FIXME: This requires the LRADC to be set up! */
337 setbits_le32(&power_regs->hw_power_battmonitor,
338 POWER_BATTMONITOR_EN_BATADJ);
340 clrbits_le32(&power_regs->hw_power_battmonitor,
341 POWER_BATTMONITOR_EN_BATADJ);
344 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
345 clrsetbits_le32(&power_regs->hw_power_loopctrl,
346 POWER_LOOPCTRL_EN_RCSCALE_MASK,
347 POWER_LOOPCTRL_RCSCALE_THRESH |
348 POWER_LOOPCTRL_EN_RCSCALE_8X);
350 clrsetbits_le32(&power_regs->hw_power_minpwr,
351 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
353 if (!fixed_batt_supply) {
354 /* 5V to battery handoff ... FIXME */
355 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
357 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
362 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
364 * This function configures the necessary parameters for the 4P2 linear
365 * regulator to supply the DC-DC converter from 5V input.
367 static void mxs_power_init_4p2_params(void)
369 debug("SPL: Configuring common 4P2 regulator params\n");
371 /* Setup 4P2 parameters */
372 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
373 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
374 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
376 clrsetbits_le32(&power_regs->hw_power_5vctrl,
377 POWER_5VCTRL_HEADROOM_ADJ_MASK,
378 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
380 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
381 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
382 DCDC4P2_DROPOUT_CONFIG);
384 clrsetbits_le32(&power_regs->hw_power_5vctrl,
385 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
386 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
390 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
391 * @xfer: Select if the input shall be enabled or disabled
393 * This function enables or disables the 4P2 input into the DC-DC converter.
395 static void mxs_enable_4p2_dcdc_input(int xfer)
397 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
398 uint32_t prev_5v_brnout, prev_5v_droop;
400 debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
402 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
403 POWER_5VCTRL_PWDN_5VBRNOUT;
404 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
405 POWER_CTRL_ENIRQ_VDD5V_DROOP;
407 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
408 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
409 &power_regs->hw_power_reset);
411 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
413 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
414 POWER_5VCTRL_ENABLE_DCDC)) {
419 * Recording orignal values that will be modified temporarlily
420 * to handle a chip bug. See chip errata for CQ ENGR00115837
422 tmp = readl(&power_regs->hw_power_5vctrl);
423 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
424 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
426 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
429 * Disable mechanisms that get erroneously tripped by when setting
430 * the DCDC4P2 EN_DCDC
432 clrbits_le32(&power_regs->hw_power_5vctrl,
433 POWER_5VCTRL_VBUSVALID_5VDETECT |
434 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
436 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
439 setbits_le32(&power_regs->hw_power_5vctrl,
440 POWER_5VCTRL_DCDC_XFER);
442 clrbits_le32(&power_regs->hw_power_5vctrl,
443 POWER_5VCTRL_DCDC_XFER);
445 setbits_le32(&power_regs->hw_power_5vctrl,
446 POWER_5VCTRL_ENABLE_DCDC);
448 setbits_le32(&power_regs->hw_power_dcdc4p2,
449 POWER_DCDC4P2_ENABLE_DCDC);
454 clrsetbits_le32(&power_regs->hw_power_5vctrl,
455 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
458 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
461 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
463 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
464 writel(POWER_CTRL_VBUS_VALID_IRQ,
465 &power_regs->hw_power_ctrl_clr);
467 if (prev_5v_brnout) {
468 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
469 &power_regs->hw_power_5vctrl_set);
470 writel(POWER_RESET_UNLOCK_KEY,
471 &power_regs->hw_power_reset);
473 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
474 &power_regs->hw_power_5vctrl_clr);
475 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
476 &power_regs->hw_power_reset);
479 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
480 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
481 &power_regs->hw_power_ctrl_clr);
484 clrbits_le32(&power_regs->hw_power_ctrl,
485 POWER_CTRL_ENIRQ_VDD5V_DROOP);
487 setbits_le32(&power_regs->hw_power_ctrl,
488 POWER_CTRL_ENIRQ_VDD5V_DROOP);
492 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
494 * This function enables the 4P2 regulator and switches the DC-DC converter
495 * to use the 4P2 input.
497 static void mxs_power_init_4p2_regulator(void)
501 debug("SPL: Enabling 4P2 regulator\n");
503 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
505 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
507 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
508 &power_regs->hw_power_5vctrl_clr);
509 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
511 /* Power up the 4p2 rail and logic/control */
512 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
513 &power_regs->hw_power_5vctrl_clr);
516 * Start charging up the 4p2 capacitor. We ramp of this charge
517 * gradually to avoid large inrush current from the 5V cable which can
518 * cause transients/problems
520 debug("SPL: Charging 4P2 capacitor\n");
521 mxs_enable_4p2_dcdc_input(0);
523 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
525 * If we arrived here, we were unable to recover from mx23 chip
526 * errata 5837. 4P2 is disabled and sufficient battery power is
527 * not present. Exiting to not enable DCDC power during 5V
530 clrbits_le32(&power_regs->hw_power_dcdc4p2,
531 POWER_DCDC4P2_ENABLE_DCDC);
532 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
533 &power_regs->hw_power_5vctrl_set);
535 debug("SPL: Unable to recover from mx23 errata 5837\n");
540 * Here we set the 4p2 brownout level to something very close to 4.2V.
541 * We then check the brownout status. If the brownout status is false,
542 * the voltage is already close to the target voltage of 4.2V so we
543 * can go ahead and set the 4P2 current limit to our max target limit.
544 * If the brownout status is true, we need to ramp up the current limit
545 * so that we don't cause large inrush current issues. We step up the
546 * current limit until the brownout status is false or until we've
547 * reached our maximum defined 4p2 current limit.
549 debug("SPL: Setting 4P2 brownout level\n");
550 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
551 POWER_DCDC4P2_BO_MASK,
552 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
554 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
555 setbits_le32(&power_regs->hw_power_5vctrl,
556 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
558 tmp = (readl(&power_regs->hw_power_5vctrl) &
559 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
560 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
562 if (!(readl(&power_regs->hw_power_sts) &
563 POWER_STS_DCDC_4P2_BO)) {
564 tmp = readl(&power_regs->hw_power_5vctrl);
565 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
567 writel(tmp, &power_regs->hw_power_5vctrl);
571 tmp2 = readl(&power_regs->hw_power_5vctrl);
572 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
574 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
575 writel(tmp2, &power_regs->hw_power_5vctrl);
581 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
582 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
586 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
588 * This function configures the DC-DC converter to be supplied from the 4P2
591 static void mxs_power_init_dcdc_4p2_source(void)
593 debug("SPL: Switching DC-DC converters to 4P2\n");
595 if (!(readl(&power_regs->hw_power_dcdc4p2) &
596 POWER_DCDC4P2_ENABLE_DCDC)) {
597 debug("SPL: Already switched - aborting\n");
601 mxs_enable_4p2_dcdc_input(1);
603 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
604 clrbits_le32(&power_regs->hw_power_dcdc4p2,
605 POWER_DCDC4P2_ENABLE_DCDC);
606 writel(POWER_5VCTRL_ENABLE_DCDC,
607 &power_regs->hw_power_5vctrl_clr);
608 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
609 &power_regs->hw_power_5vctrl_set);
614 * mxs_power_enable_4p2() - Power up the 4P2 regulator
616 * This function drives the process of powering up the 4P2 linear regulator
617 * and switching the DC-DC converter input over to the 4P2 linear regulator.
619 static void mxs_power_enable_4p2(void)
621 uint32_t vdddctrl, vddactrl, vddioctrl;
624 debug("SPL: Powering up 4P2 regulator\n");
626 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
627 vddactrl = readl(&power_regs->hw_power_vddactrl);
628 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
630 setbits_le32(&power_regs->hw_power_vdddctrl,
631 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
632 POWER_VDDDCTRL_PWDN_BRNOUT);
634 setbits_le32(&power_regs->hw_power_vddactrl,
635 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
636 POWER_VDDACTRL_PWDN_BRNOUT);
638 setbits_le32(&power_regs->hw_power_vddioctrl,
639 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
641 mxs_power_init_4p2_params();
642 mxs_power_init_4p2_regulator();
644 /* Shutdown battery (none present) */
645 if (!mxs_is_batt_ready()) {
646 clrbits_le32(&power_regs->hw_power_dcdc4p2,
647 POWER_DCDC4P2_BO_MASK);
648 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
649 &power_regs->hw_power_ctrl_clr);
650 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
651 &power_regs->hw_power_ctrl_clr);
654 mxs_power_init_dcdc_4p2_source();
656 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
658 writel(vddactrl, &power_regs->hw_power_vddactrl);
660 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
663 * Check if FET is enabled on either powerout and if so,
667 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
668 POWER_VDDDCTRL_DISABLE_FET);
669 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
670 POWER_VDDACTRL_DISABLE_FET);
671 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
672 POWER_VDDIOCTRL_DISABLE_FET);
674 writel(POWER_CHARGE_ENABLE_LOAD,
675 &power_regs->hw_power_charge_clr);
677 debug("SPL: 4P2 regulator powered-up\n");
681 * mxs_boot_valid_5v() - Boot from 5V supply
683 * This function configures the power block to boot from valid 5V input.
684 * This is called only if the 5V is reliable and can properly supply the
685 * CPU. This function proceeds to configure the 4P2 converter to be supplied
688 static void mxs_boot_valid_5v(void)
690 debug("SPL: Booting from 5V supply\n");
693 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
694 * disconnect event. FIXME
696 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
697 &power_regs->hw_power_5vctrl_set);
699 /* Configure polarity to check for 5V disconnection. */
700 writel(POWER_CTRL_POLARITY_VBUSVALID |
701 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
702 &power_regs->hw_power_ctrl_clr);
704 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
705 &power_regs->hw_power_ctrl_clr);
707 mxs_power_enable_4p2();
711 * mxs_powerdown() - Shut down the system
713 * This function powers down the CPU completely.
715 static void mxs_powerdown(void)
717 debug("Powering Down\n");
719 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
720 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
721 &power_regs->hw_power_reset);
725 * mxs_batt_boot() - Configure the power block to boot from battery input
727 * This function configures the power block to boot from the battery voltage
730 static void mxs_batt_boot(void)
732 debug("SPL: Configuring power block to boot from battery\n");
734 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
735 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
737 clrbits_le32(&power_regs->hw_power_dcdc4p2,
738 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
739 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
741 /* 5V to battery handoff. */
742 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
744 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
746 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
748 clrsetbits_le32(&power_regs->hw_power_minpwr,
749 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
751 mxs_power_set_linreg();
753 clrbits_le32(&power_regs->hw_power_vdddctrl,
754 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
756 clrbits_le32(&power_regs->hw_power_vddactrl,
757 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
759 clrbits_le32(&power_regs->hw_power_vddioctrl,
760 POWER_VDDIOCTRL_DISABLE_FET);
762 setbits_le32(&power_regs->hw_power_5vctrl,
763 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
765 setbits_le32(&power_regs->hw_power_5vctrl,
766 POWER_5VCTRL_ENABLE_DCDC);
768 clrsetbits_le32(&power_regs->hw_power_5vctrl,
769 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
770 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
772 mxs_power_enable_4p2();
776 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
778 * This function tests if the 5V input can reliably supply the system. If it
779 * can, then proceed to configuring the system to boot from 5V source, otherwise
780 * try booting from battery supply. If we can not boot from battery supply
781 * either, shut down the system.
783 static void mxs_handle_5v_conflict(void)
787 debug("SPL: Resolving 5V conflict\n");
789 setbits_le32(&power_regs->hw_power_vddioctrl,
790 POWER_VDDIOCTRL_BO_OFFSET_MASK);
793 tmp = readl(&power_regs->hw_power_sts);
795 if (tmp & POWER_STS_VDDIO_BO) {
797 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
800 debug("SPL: VDDIO has a brownout\n");
805 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
806 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
810 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
816 * TODO: I can't see this being reached. We'll either
817 * powerdown or boot from a stable 5V supply.
819 if (tmp & POWER_STS_PSWITCH_MASK) {
820 debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
828 * mxs_5v_boot() - Configure the power block to boot from 5V input
830 * This function handles configuration of the power block when supplied by
833 static void mxs_5v_boot(void)
835 debug("SPL: Configuring power block to boot from 5V input\n");
838 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
839 * but their implementation always returns 1 so we omit it here.
841 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
842 debug("SPL: 5V VDD good\n");
848 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
849 debug("SPL: 5V VDD good (after delay)\n");
854 debug("SPL: 5V VDD not good\n");
855 mxs_handle_5v_conflict();
858 static void mxs_fixed_batt_boot(void)
860 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
862 setbits_le32(&power_regs->hw_power_5vctrl,
863 POWER_5VCTRL_ENABLE_DCDC |
864 POWER_5VCTRL_ILIMIT_EQ_ZERO |
865 POWER_5VCTRL_PWDN_5VBRNOUT |
866 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
868 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
870 clrbits_le32(&power_regs->hw_power_vdddctrl,
871 POWER_VDDDCTRL_DISABLE_FET |
872 POWER_VDDDCTRL_ENABLE_LINREG |
873 POWER_VDDDCTRL_DISABLE_STEPPING);
875 clrbits_le32(&power_regs->hw_power_vddactrl,
876 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
877 POWER_VDDACTRL_DISABLE_STEPPING);
879 clrbits_le32(&power_regs->hw_power_vddioctrl,
880 POWER_VDDIOCTRL_DISABLE_FET |
881 POWER_VDDIOCTRL_DISABLE_STEPPING);
883 /* Stop 5V detection */
884 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
885 &power_regs->hw_power_5vctrl_clr);
889 * mxs_init_batt_bo() - Configure battery brownout threshold
891 * This function configures the battery input brownout threshold. The value
892 * at which the battery brownout happens is configured to 3.0V in the code.
894 static void mxs_init_batt_bo(void)
896 debug("SPL: Initialising battery brown-out level to 3.0V\n");
899 clrsetbits_le32(&power_regs->hw_power_battmonitor,
900 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
901 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
903 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
904 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
908 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
910 * This function turns off the VDDD linear regulator and therefore makes
911 * the VDDD rail be supplied only by the DC-DC converter.
913 static void mxs_switch_vddd_to_dcdc_source(void)
915 debug("SPL: Switching VDDD to DC-DC converters\n");
917 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
918 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
919 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
921 clrbits_le32(&power_regs->hw_power_vdddctrl,
922 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
923 POWER_VDDDCTRL_DISABLE_STEPPING);
927 * mxs_power_configure_power_source() - Configure power block source
929 * This function is the core of the power configuration logic. The function
930 * selects the power block input source and configures the whole power block
931 * accordingly. After the configuration is complete and the system is stable
932 * again, the function switches the CPU clock source back to PLL. Finally,
933 * the function switches the voltage rails to DC-DC converter.
935 static void mxs_power_configure_power_source(void)
937 struct mxs_lradc_regs *lradc_regs =
938 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
940 debug("SPL: Configuring power source\n");
942 mxs_src_power_init();
944 if (!fixed_batt_supply) {
945 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
946 if (mxs_is_batt_ready()) {
947 /* 5V source detected, good battery detected. */
950 if (!mxs_is_batt_good()) {
951 /* 5V source detected, bad battery detected. */
952 writel(LRADC_CONVERSION_AUTOMATIC,
953 &lradc_regs->hw_lradc_conversion_clr);
954 clrbits_le32(&power_regs->hw_power_battmonitor,
955 POWER_BATTMONITOR_BATT_VAL_MASK);
960 /* 5V not detected, booting from battery. */
964 mxs_fixed_batt_boot();
968 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
971 mxs_power_clock2pll();
975 mxs_switch_vddd_to_dcdc_source();
977 #ifdef CONFIG_SOC_MX23
978 /* Fire up the VDDMEM LinReg now that we're all set. */
979 debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
980 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
981 &power_regs->hw_power_vddmemctrl);
986 * mxs_enable_output_rail_protection() - Enable power rail protection
988 * This function enables overload protection on the power rails. This is
989 * triggered if the power rails' voltage drops rapidly due to overload and
990 * in such case, the supply to the powerrail is cut-off, protecting the
991 * CPU from damage. Note that under such condition, the system will likely
992 * crash or misbehave.
994 static void mxs_enable_output_rail_protection(void)
996 debug("SPL: Enabling output rail protection\n");
998 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
999 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1001 setbits_le32(&power_regs->hw_power_vdddctrl,
1002 POWER_VDDDCTRL_PWDN_BRNOUT);
1004 setbits_le32(&power_regs->hw_power_vddactrl,
1005 POWER_VDDACTRL_PWDN_BRNOUT);
1007 setbits_le32(&power_regs->hw_power_vddioctrl,
1008 POWER_VDDIOCTRL_PWDN_BRNOUT);
1012 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1014 * This function tests if the VDDIO rail is supplied by linear regulator
1015 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1016 * returns 0 if powered by the DC-DC converter.
1018 static int mxs_get_vddio_power_source_off(void)
1022 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1023 !(readl(&power_regs->hw_power_5vctrl) &
1024 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1026 tmp = readl(&power_regs->hw_power_vddioctrl);
1027 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1028 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1029 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1034 if (!(readl(&power_regs->hw_power_5vctrl) &
1035 POWER_5VCTRL_ENABLE_DCDC)) {
1036 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1037 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1047 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1049 * This function tests if the VDDD rail is supplied by linear regulator
1050 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1051 * returns 0 if powered by the DC-DC converter.
1053 static int mxs_get_vddd_power_source_off(void)
1057 tmp = readl(&power_regs->hw_power_vdddctrl);
1058 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1059 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1060 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1065 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1066 if (!(readl(&power_regs->hw_power_5vctrl) &
1067 POWER_5VCTRL_ENABLE_DCDC)) {
1072 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1073 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1074 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1082 static int mxs_get_vdda_power_source_off(void)
1086 tmp = readl(&power_regs->hw_power_vddactrl);
1087 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1088 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1089 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1094 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1095 if (!(readl(&power_regs->hw_power_5vctrl) &
1096 POWER_5VCTRL_ENABLE_DCDC)) {
1101 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1102 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1103 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1111 struct mxs_vddx_cfg {
1115 uint16_t highest_mV;
1116 int (*powered_by_linreg)(void);
1120 uint32_t bo_offset_mask;
1121 uint32_t bo_offset_offset;
1126 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1128 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1129 .reg = POWER_REG(hw_power_vddioctrl),
1130 #if defined(CONFIG_SOC_MX23)
1137 .powered_by_linreg = mxs_get_vddio_power_source_off,
1138 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1139 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1140 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1141 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1142 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1147 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1148 .reg = POWER_REG(hw_power_vdddctrl),
1152 .powered_by_linreg = mxs_get_vddd_power_source_off,
1153 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1154 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1155 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1156 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1157 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1162 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1163 .reg = POWER_REG(hw_power_vddactrl),
1167 .powered_by_linreg = mxs_get_vdda_power_source_off,
1168 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1169 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1170 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1171 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1172 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1177 #ifdef CONFIG_SOC_MX23
1178 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1179 .reg = POWER_REG(hw_power_vddmemctrl),
1183 .powered_by_linreg = NULL,
1184 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1187 .bo_offset_mask = 0,
1188 .bo_offset_offset = 0,
1193 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1194 * @cfg: Configuration data of the DC-DC converter rail
1195 * @new_target: New target voltage of the DC-DC converter rail
1196 * @new_brownout: New brownout trigger voltage
1198 * This function configures the output voltage on the DC-DC converter rail.
1199 * The rail is selected by the @cfg argument. The new voltage target is
1200 * selected by the @new_target and the voltage is specified in mV. The
1201 * new brownout value is selected by the @new_brownout argument and the
1202 * value is also in mV.
1204 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1205 uint32_t new_target, uint32_t bo_offset)
1207 uint32_t cur_target, diff, bo_int = 0;
1208 int powered_by_linreg = 0;
1211 if (new_target < cfg->lowest_mV) {
1212 new_target = cfg->lowest_mV;
1214 if (new_target > cfg->highest_mV) {
1215 new_target = cfg->highest_mV;
1218 if (new_target - bo_offset < cfg->bo_min_mV) {
1219 bo_offset = new_target - cfg->bo_min_mV;
1220 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1221 bo_offset = new_target - cfg->bo_max_mV;
1224 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1226 cur_target = readl(cfg->reg);
1227 cur_target &= cfg->trg_mask;
1228 cur_target *= cfg->step_mV;
1229 cur_target += cfg->lowest_mV;
1231 adjust_up = new_target > cur_target;
1232 if (cfg->powered_by_linreg)
1233 powered_by_linreg = cfg->powered_by_linreg();
1235 if (adjust_up && cfg->bo_irq) {
1236 if (powered_by_linreg) {
1237 bo_int = readl(&power_regs->hw_power_ctrl);
1238 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1240 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1244 if (abs(new_target - cur_target) > 100) {
1246 diff = cur_target + 100;
1248 diff = cur_target - 100;
1253 diff -= cfg->lowest_mV;
1254 diff /= cfg->step_mV;
1256 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1258 if (powered_by_linreg ||
1259 (readl(&power_regs->hw_power_sts) &
1260 POWER_STS_VDD5V_GT_VDDIO)) {
1263 while (!(readl(&power_regs->hw_power_sts) &
1269 cur_target = readl(cfg->reg);
1270 cur_target &= cfg->trg_mask;
1271 cur_target *= cfg->step_mV;
1272 cur_target += cfg->lowest_mV;
1273 } while (new_target > cur_target);
1276 if (adjust_up && powered_by_linreg) {
1277 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1278 if (bo_int & cfg->bo_enirq)
1279 writel(cfg->bo_enirq,
1280 &power_regs->hw_power_ctrl_set);
1283 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1284 bo_offset << cfg->bo_offset_offset);
1289 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1291 * This function starts and configures the LRADC block. This allows the
1292 * power initialization code to measure battery voltage and based on this
1293 * knowledge, decide whether to boot at all, boot from battery or boot
1296 static void mxs_setup_batt_detect(void)
1298 debug("SPL: Starting battery voltage measurement logic\n");
1301 mxs_lradc_enable_batt_measurement();
1306 * mxs_ungate_power() - Ungate the POWER block
1308 * This function ungates clock to the power block. In case the power block
1309 * was still gated at this point, it will not be possible to configure the
1310 * block and therefore the power initialization would fail. This function
1311 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1313 static void mxs_ungate_power(void)
1315 #ifdef CONFIG_SOC_MX23
1316 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1320 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1321 #define auto_restart 1
1323 #define auto_restart 0
1327 * mxs_power_init() - The power block init main function
1329 * This function calls all the power block initialization functions in
1330 * proper sequence to start the power block.
1332 #define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
1334 void mxs_power_init(void)
1336 debug("SPL: Initialising Power Block\n");
1340 mxs_power_clock2xtal();
1341 if (mxs_power_set_auto_restart(auto_restart)) {
1342 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1344 mxs_power_set_linreg();
1346 if (!fixed_batt_supply) {
1347 mxs_power_setup_5v_detect();
1348 mxs_setup_batt_detect();
1351 mxs_power_configure_power_source();
1352 mxs_enable_output_rail_protection();
1354 debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1355 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1356 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1357 debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1358 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1359 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1360 debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1361 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1362 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1363 #ifdef CONFIG_SOC_MX23
1364 debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1365 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1366 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1368 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1369 POWER_VDDMEMCTRL_ENABLE_LINREG);
1371 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1372 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1373 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1374 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1375 if (!fixed_batt_supply)
1376 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1377 &power_regs->hw_power_5vctrl_set);
1380 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1382 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1384 * This function waits until the power-switch was pressed to start booting
1387 void mxs_power_wait_pswitch(void)
1389 debug("SPL: Waiting for power switch input\n");
1390 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))