4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/common_def.h>
28 #include <asm/omap_common.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
33 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
34 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
37 #ifdef CONFIG_SPL_BUILD
38 #define UART_RESET (0x1 << 1)
39 #define UART_CLK_RUNNING_MASK 0x1
40 #define UART_SMART_IDLE_EN (0x1 << 0x3)
44 * early system init of muxing and clocks.
48 /* WDT1 is already running when the bootloader gets control
49 * Disable it to avoid "random" resets
51 writel(0xAAAA, &wdtimer->wdtwspr);
52 while (readl(&wdtimer->wdtwwps) != 0x0)
54 writel(0x5555, &wdtimer->wdtwspr);
55 while (readl(&wdtimer->wdtwwps) != 0x0)
58 #ifdef CONFIG_SPL_BUILD
59 /* Setup the PLLs and the clocks for the peripherals */
65 enable_uart0_pin_mux();
67 regVal = readl(&uart_base->uartsyscfg);
69 writel(regVal, &uart_base->uartsyscfg);
70 while ((readl(&uart_base->uartsyssts) &
71 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
74 /* Disable smart idle */
75 regVal = readl(&uart_base->uartsyscfg);
76 regVal |= UART_SMART_IDLE_EN;
77 writel(regVal, &uart_base->uartsyscfg);
79 /* Initialize the Timer */
82 preloader_console_init();
88 enable_mmc0_pin_mux();
91 /* Initialize timer */
95 writel(0x2, (&timer_base->tscir));
97 /* Wait until the reset is done */
98 while (readl(&timer_base->tiocp_cfg) & 1)
101 /* Start the Timer */
102 writel(0x1, (&timer_base->tclr));
105 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
106 int board_mmc_init(bd_t *bis)
108 return omap_mmc_init(0, 0, 0);
112 void setup_clocks_for_console(void)
114 /* Not yet implemented */