4 * Clock initialization for AM33XX boards.
5 * Derived from OMAP4 boards
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
18 static void setup_post_dividers(const struct dpll_regs *dpll_regs,
19 const struct dpll_params *params)
21 /* Setup post-dividers */
23 writel(params->m2, dpll_regs->cm_div_m2_dpll);
25 writel(params->m3, dpll_regs->cm_div_m3_dpll);
27 writel(params->m4, dpll_regs->cm_div_m4_dpll);
29 writel(params->m5, dpll_regs->cm_div_m5_dpll);
31 writel(params->m6, dpll_regs->cm_div_m6_dpll);
34 static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
36 clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
37 CM_CLKMODE_DPLL_DPLL_EN_MASK,
38 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
41 static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
43 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
44 (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
45 printf("DPLL locking failed for 0x%x\n",
46 dpll_regs->cm_clkmode_dpll);
51 static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
53 clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
54 CM_CLKMODE_DPLL_DPLL_EN_MASK,
55 DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
58 static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
60 if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
61 (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
62 printf("Bypassing DPLL failed 0x%x\n",
63 dpll_regs->cm_clkmode_dpll);
67 static void bypass_dpll(const struct dpll_regs *dpll_regs)
69 do_bypass_dpll(dpll_regs);
70 wait_for_bypass(dpll_regs);
73 void do_setup_dpll(const struct dpll_regs *dpll_regs,
74 const struct dpll_params *params)
81 temp = readl(dpll_regs->cm_clksel_dpll);
83 bypass_dpll(dpll_regs);
86 temp &= ~CM_CLKSEL_DPLL_M_MASK;
87 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
89 temp &= ~CM_CLKSEL_DPLL_N_MASK;
90 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
92 writel(temp, dpll_regs->cm_clksel_dpll);
94 setup_post_dividers(dpll_regs, params);
96 /* Wait till the DPLL locks */
97 do_lock_dpll(dpll_regs);
98 wait_for_lock(dpll_regs);
101 void setup_dplls(void)
103 const struct dpll_params *params;
104 do_setup_dpll(&dpll_core_regs, &dpll_core);
105 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
106 do_setup_dpll(&dpll_per_regs, &dpll_per);
107 writel(0x300, &cmwkup->clkdcoldodpllper);
109 params = get_dpll_ddr_params();
110 do_setup_dpll(&dpll_ddr_regs, params);