3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/types.h>
10 #include <asm/armv7.h>
11 #include <asm/utils.h>
13 #define ARMV7_DCACHE_INVAL_ALL 1
14 #define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
15 #define ARMV7_DCACHE_INVAL_RANGE 3
16 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
18 #ifndef CONFIG_SYS_DCACHE_OFF
20 * Write the level and type you want to Cache Size Selection Register(CSSELR)
21 * to get size details from Current Cache Size ID Register(CCSIDR)
23 static void set_csselr(u32 level, u32 type)
25 u32 csselr = level << 1 | type;
27 /* Write to Cache Size Selection Register(CSSELR) */
28 asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
31 static u32 get_ccsidr(void)
35 /* Read current CP15 Cache Size ID Register */
36 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
40 static u32 get_clidr(void)
44 /* Read current CP15 Cache Level ID Register */
45 asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
49 static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
50 u32 num_ways, u32 way_shift,
57 * For optimal assembly code:
59 * b. have bigger loop inside
61 for (way = num_ways - 1; way >= 0 ; way--) {
62 for (set = num_sets - 1; set >= 0; set--) {
63 setway = (level << 1) | (set << log2_line_len) |
65 /* Invalidate data/unified cache line by set/way */
66 asm volatile (" mcr p15, 0, %0, c7, c6, 2"
70 /* DSB to make sure the operation is complete */
74 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
75 u32 num_ways, u32 way_shift,
82 * For optimal assembly code:
84 * b. have bigger loop inside
86 for (way = num_ways - 1; way >= 0 ; way--) {
87 for (set = num_sets - 1; set >= 0; set--) {
88 setway = (level << 1) | (set << log2_line_len) |
91 * Clean & Invalidate data/unified
92 * cache line by set/way
94 asm volatile (" mcr p15, 0, %0, c7, c14, 2"
98 /* DSB to make sure the operation is complete */
102 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
105 u32 num_sets, num_ways, log2_line_len, log2_num_ways;
108 set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
110 ccsidr = get_ccsidr();
112 log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
113 CCSIDR_LINE_SIZE_OFFSET) + 2;
114 /* Converting from words to bytes */
117 num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
118 CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
119 num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
120 CCSIDR_NUM_SETS_OFFSET) + 1;
122 * According to ARMv7 ARM number of sets and number of ways need
123 * not be a power of 2
125 log2_num_ways = log_2_n_round_up(num_ways);
127 way_shift = (32 - log2_num_ways);
128 if (operation == ARMV7_DCACHE_INVAL_ALL) {
129 v7_inval_dcache_level_setway(level, num_sets, num_ways,
130 way_shift, log2_line_len);
131 } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
132 v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
133 way_shift, log2_line_len);
137 static void v7_maint_dcache_all(u32 operation)
139 u32 level, cache_type, level_start_bit = 0;
140 u32 clidr = get_clidr();
142 for (level = 0; level < 7; level++) {
143 cache_type = (clidr >> level_start_bit) & 0x7;
144 if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
145 (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
146 (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
147 v7_maint_dcache_level_setway(level, operation);
148 level_start_bit += 3;
152 static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
156 /* Align start to cache line boundary */
157 start &= ~(line_len - 1);
158 for (mva = start; mva < stop; mva = mva + line_len) {
159 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
160 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
164 static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
169 * If start address is not aligned to cache-line do not
170 * invalidate the first cache-line
172 if (start & (line_len - 1)) {
173 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
175 /* move to next cache line */
176 start = (start + line_len - 1) & ~(line_len - 1);
180 * If stop address is not aligned to cache-line do not
181 * invalidate the last cache-line
183 if (stop & (line_len - 1)) {
184 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
186 /* align to the beginning of this cache line */
187 stop &= ~(line_len - 1);
190 for (mva = start; mva < stop; mva = mva + line_len) {
191 /* DCIMVAC - Invalidate data cache by MVA to PoC */
192 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
196 static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
198 u32 line_len, ccsidr;
200 ccsidr = get_ccsidr();
201 line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
202 CCSIDR_LINE_SIZE_OFFSET) + 2;
203 /* Converting from words to bytes */
205 /* converting from log2(linelen) to linelen */
206 line_len = 1 << line_len;
209 case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
210 v7_dcache_clean_inval_range(start, stop, line_len);
212 case ARMV7_DCACHE_INVAL_RANGE:
213 v7_dcache_inval_range(start, stop, line_len);
217 /* DSB to make sure the operation is complete */
222 static void v7_inval_tlb(void)
225 /* Invalidate entire unified TLB */
226 "mcr p15, 0, %0, c8, c7, 0\n"
227 /* Invalidate entire data TLB */
228 "mcr p15, 0, %0, c8, c6, 0\n"
229 /* Invalidate entire instruction TLB */
230 "mcr p15, 0, %0, c8, c5, 0\n"
231 /* Full system DSB - make sure that the invalidation is complete */
232 "mcr p15, 0, %0, c7, c10, 4\n"
233 /* Full system ISB - make sure the instruction stream sees it */
234 "mcr p15, 0, %0, c7, c5, 4\n"
238 void invalidate_dcache_all(void)
240 v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
242 v7_outer_cache_inval_all();
246 * Performs a clean & invalidation of the entire data cache
249 void flush_dcache_all(void)
251 v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
253 v7_outer_cache_flush_all();
257 * Invalidates range in all levels of D-cache/unified cache used:
258 * Affects the range [start, stop - 1]
260 void invalidate_dcache_range(unsigned long start, unsigned long stop)
262 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
264 v7_outer_cache_inval_range(start, stop);
268 * Flush range(clean & invalidate) from all levels of D-cache/unified
270 * Affects the range [start, stop - 1]
272 void flush_dcache_range(unsigned long start, unsigned long stop)
274 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
276 v7_outer_cache_flush_range(start, stop);
279 void arm_init_before_mmu(void)
281 v7_outer_cache_enable();
282 invalidate_dcache_all();
286 void mmu_page_table_flush(unsigned long start, unsigned long stop)
288 flush_dcache_range(start, stop);
293 * Flush range from all levels of d-cache/unified-cache used:
294 * Affects the range [start, start + size - 1]
296 void flush_cache(unsigned long start, unsigned long size)
298 flush_dcache_range(start, start + size);
300 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
301 void invalidate_dcache_all(void)
305 void flush_dcache_all(void)
309 void invalidate_dcache_range(unsigned long start, unsigned long stop)
313 void flush_dcache_range(unsigned long start, unsigned long stop)
317 void arm_init_before_mmu(void)
321 void flush_cache(unsigned long start, unsigned long size)
325 void mmu_page_table_flush(unsigned long start, unsigned long stop)
329 void arm_init_domains(void)
332 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
334 #ifndef CONFIG_SYS_ICACHE_OFF
335 /* Invalidate entire I-cache and branch predictor array */
336 void invalidate_icache_all(void)
339 * Invalidate all instruction caches to PoU.
340 * Also flushes branch target cache.
343 "mcr p15, 0, %0, c7, c5, 0\n"
344 /* Invalidate entire branch predictor array */
345 "mcr p15, 0, %0, c7, c5, 6\n"
346 /* Full system DSB - make sure that the invalidation is complete */
347 "mcr p15, 0, %0, c7, c10, 4\n"
348 /* ISB - make sure the instruction stream sees it */
349 "mcr p15, 0, %0, c7, c5, 4\n"
353 void invalidate_icache_all(void)
358 /* Stub implementations for outer cache operations */
359 __weak void v7_outer_cache_enable(void) {}
360 __weak void v7_outer_cache_disable(void) {}
361 __weak void v7_outer_cache_flush_all(void) {}
362 __weak void v7_outer_cache_inval_all(void) {}
363 __weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
364 __weak void v7_outer_cache_inval_range(u32 start, u32 end) {}