2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
29 #ifndef CONFIG_SYS_CLK_FREQ_C210
30 #define CONFIG_SYS_CLK_FREQ_C210 24000000
33 /* exynos4: return pll clock frequency */
34 static unsigned long exynos4_get_pll_clk(int pllreg)
36 struct exynos4_clock *clk =
37 (struct exynos4_clock *)samsung_get_base_clock();
38 unsigned long r, m, p, s, k = 0, mask, fout;
43 r = readl(&clk->apll_con0);
46 r = readl(&clk->mpll_con0);
49 r = readl(&clk->epll_con0);
50 k = readl(&clk->epll_con1);
53 r = readl(&clk->vpll_con0);
54 k = readl(&clk->vpll_con1);
57 printf("Unsupported PLL (%d)\n", pllreg);
62 * APLL_CON: MIDV [25:16]
63 * MPLL_CON: MIDV [25:16]
64 * EPLL_CON: MIDV [24:16]
65 * VPLL_CON: MIDV [24:16]
67 if (pllreg == APLL || pllreg == MPLL)
79 freq = CONFIG_SYS_CLK_FREQ_C210;
83 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
84 fout = (m + k / 65536) * (freq / (p * (1 << s)));
85 } else if (pllreg == VPLL) {
87 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
88 fout = (m + k / 1024) * (freq / (p * (1 << s)));
92 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
93 fout = m * (freq / (p * (1 << (s - 1))));
99 /* exynos4: return ARM clock frequency */
100 static unsigned long exynos4_get_arm_clk(void)
102 struct exynos4_clock *clk =
103 (struct exynos4_clock *)samsung_get_base_clock();
105 unsigned long armclk;
106 unsigned int core_ratio;
107 unsigned int core2_ratio;
109 div = readl(&clk->div_cpu0);
111 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
112 core_ratio = (div >> 0) & 0x7;
113 core2_ratio = (div >> 28) & 0x7;
115 armclk = get_pll_clk(APLL) / (core_ratio + 1);
116 armclk /= (core2_ratio + 1);
121 /* exynos4: return pwm clock frequency */
122 static unsigned long exynos4_get_pwm_clk(void)
124 struct exynos4_clock *clk =
125 (struct exynos4_clock *)samsung_get_base_clock();
126 unsigned long pclk, sclk;
130 if (s5p_get_cpu_rev() == 0) {
135 sel = readl(&clk->src_peril0);
136 sel = (sel >> 24) & 0xf;
139 sclk = get_pll_clk(MPLL);
141 sclk = get_pll_clk(EPLL);
143 sclk = get_pll_clk(VPLL);
151 ratio = readl(&clk->div_peril3);
153 } else if (s5p_get_cpu_rev() == 1) {
154 sclk = get_pll_clk(MPLL);
159 pclk = sclk / (ratio + 1);
164 /* exynos4: return uart clock frequency */
165 static unsigned long exynos4_get_uart_clk(int dev_index)
167 struct exynos4_clock *clk =
168 (struct exynos4_clock *)samsung_get_base_clock();
169 unsigned long uclk, sclk;
182 sel = readl(&clk->src_peril0);
183 sel = (sel >> (dev_index << 2)) & 0xf;
186 sclk = get_pll_clk(MPLL);
188 sclk = get_pll_clk(EPLL);
190 sclk = get_pll_clk(VPLL);
199 * UART3_RATIO [12:15]
200 * UART4_RATIO [16:19]
201 * UART5_RATIO [23:20]
203 ratio = readl(&clk->div_peril0);
204 ratio = (ratio >> (dev_index << 2)) & 0xf;
206 uclk = sclk / (ratio + 1);
211 /* exynos4: set the mmc clock */
212 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
214 struct exynos4_clock *clk =
215 (struct exynos4_clock *)samsung_get_base_clock();
221 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
223 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
226 addr = (unsigned int)&clk->div_fsys1;
228 addr = (unsigned int)&clk->div_fsys2;
233 val &= ~(0xff << ((dev_index << 4) + 8));
234 val |= (div & 0xff) << ((dev_index << 4) + 8);
238 unsigned long get_pll_clk(int pllreg)
240 return exynos4_get_pll_clk(pllreg);
243 unsigned long get_arm_clk(void)
245 return exynos4_get_arm_clk();
248 unsigned long get_pwm_clk(void)
250 return exynos4_get_pwm_clk();
253 unsigned long get_uart_clk(int dev_index)
255 return exynos4_get_uart_clk(dev_index);
258 void set_mmc_clk(int dev_index, unsigned int div)
260 exynos4_set_mmc_clk(dev_index, div);