3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
42 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
43 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
44 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
45 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
47 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
54 * Calculate the frequency of PLLn.
56 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
58 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
59 uint64_t refclk, temp;
62 ctrl = readl(&pll->ctrl);
64 if (ctrl & MXC_DPLLC_CTL_HFSM) {
65 mfn = __raw_readl(&pll->hfs_mfn);
66 mfd = __raw_readl(&pll->hfs_mfd);
67 op = __raw_readl(&pll->hfs_op);
69 mfn = __raw_readl(&pll->mfn);
70 mfd = __raw_readl(&pll->mfd);
71 op = __raw_readl(&pll->op);
74 mfd &= MXC_DPLLC_MFD_MFD_MASK;
75 mfn &= MXC_DPLLC_MFN_MFN_MASK;
76 pdf = op & MXC_DPLLC_OP_PDF_MASK;
77 mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
84 if (mfn >= 0x04000000) {
91 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
95 temp = refclk * mfn_abs;
96 do_div(temp, mfd + 1);
110 u32 get_mcu_main_clk(void)
114 reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
115 MXC_CCM_CACRR_ARM_PODF_OFFSET;
116 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
117 return freq / (reg + 1);
121 * Get the rate of peripheral's root clock.
123 static u32 get_periph_clk(void)
127 reg = __raw_readl(&mxc_ccm->cbcdr);
128 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
129 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
130 reg = __raw_readl(&mxc_ccm->cbcmr);
131 switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
132 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
134 return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
136 return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
144 * Get the rate of ahb clock.
146 static u32 get_ahb_clk(void)
148 uint32_t freq, div, reg;
150 freq = get_periph_clk();
152 reg = __raw_readl(&mxc_ccm->cbcdr);
153 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
154 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
160 * Get the rate of ipg clock.
162 static u32 get_ipg_clk(void)
164 uint32_t freq, reg, div;
166 freq = get_ahb_clk();
168 reg = __raw_readl(&mxc_ccm->cbcdr);
169 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
170 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
176 * Get the rate of ipg_per clock.
178 static u32 get_ipg_per_clk(void)
180 u32 pred1, pred2, podf;
182 if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
183 return get_ipg_clk();
184 /* Fixme: not handle what about lpm*/
185 podf = __raw_readl(&mxc_ccm->cbcdr);
186 pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
187 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
188 pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
189 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
190 podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
191 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
193 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
197 * Get the rate of uart clk.
199 static u32 get_uart_clk(void)
201 unsigned int freq, reg, pred, podf;
203 reg = __raw_readl(&mxc_ccm->cscmr1);
204 switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
205 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
207 freq = decode_pll(mxc_plls[PLL1_CLOCK],
208 CONFIG_SYS_MX5_HCLK);
211 freq = decode_pll(mxc_plls[PLL2_CLOCK],
212 CONFIG_SYS_MX5_HCLK);
215 freq = decode_pll(mxc_plls[PLL3_CLOCK],
216 CONFIG_SYS_MX5_HCLK);
222 reg = __raw_readl(&mxc_ccm->cscdr1);
224 pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
225 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
227 podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
228 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
229 freq /= (pred + 1) * (podf + 1);
235 * This function returns the low power audio clock.
240 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
242 if (((ccsr >> 9) & 1) == 0)
243 ret_val = CONFIG_SYS_MX5_HCLK;
245 ret_val = ((32768 * 1024));
251 * get cspi clock rate.
253 u32 imx_get_cspiclk(void)
255 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
256 u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
257 u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
259 pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
260 >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
261 pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
262 >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
263 clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
264 >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
268 ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
269 CONFIG_SYS_MX5_HCLK) /
270 ((pre_pdf + 1) * (pdf + 1));
273 ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
274 CONFIG_SYS_MX5_HCLK) /
275 ((pre_pdf + 1) * (pdf + 1));
278 ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
279 CONFIG_SYS_MX5_HCLK) /
280 ((pre_pdf + 1) * (pdf + 1));
283 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
291 * The API of get mxc clockes.
293 unsigned int mxc_get_clock(enum mxc_clock clk)
297 return get_mcu_main_clk();
299 return get_ahb_clk();
301 return get_ipg_clk();
303 return get_ipg_per_clk();
305 return get_uart_clk();
307 return imx_get_cspiclk();
309 return decode_pll(mxc_plls[PLL1_CLOCK],
310 CONFIG_SYS_MX5_HCLK);
317 u32 imx_get_uartclk(void)
319 return get_uart_clk();
323 u32 imx_get_fecclk(void)
325 return mxc_get_clock(MXC_IPG_CLK);
329 * Dump some core clockes.
331 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
335 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
336 printf("pll1: %dMHz\n", freq / 1000000);
337 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
338 printf("pll2: %dMHz\n", freq / 1000000);
339 freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
340 printf("pll3: %dMHz\n", freq / 1000000);
342 freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
343 printf("pll4: %dMHz\n", freq / 1000000);
345 printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
346 printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
347 printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
352 /***************************************************/
355 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,