3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
29 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
30 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
31 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
32 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
34 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
38 #define AHB_CLK_ROOT 133333333
39 #define SZ_DEC_1M 1000000
40 #define PLL_PD_MAX 16 /* Actual pd+1 */
41 #define PLL_MFI_MAX 15
49 struct fixed_pll_mfd {
54 static const struct fixed_pll_mfd fixed_mfd[] = {
65 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
66 #define PLL_FREQ_MIN(ref_clk) \
67 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
68 #define MAX_DDR_CLK 420000000
69 #define NFC_CLK_MAX 34000000
71 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
73 int clk_enable(struct clk *clk)
80 if (clk->usecount++ == 0) {
83 ret = clk->enable(clk);
90 void clk_disable(struct clk *clk)
95 if (!(--clk->usecount)) {
99 if (clk->usecount < 0) {
100 printf("%s: clk %p (%s) underflow\n", __func__, clk, clk->name);
105 int clk_get_usecount(struct clk *clk)
110 return clk->usecount;
113 u32 clk_get_rate(struct clk *clk)
121 struct clk *clk_get_parent(struct clk *clk)
129 int clk_set_rate(struct clk *clk, unsigned long rate)
131 if (clk && clk->set_rate)
132 clk->set_rate(clk, rate);
136 long clk_round_rate(struct clk *clk, unsigned long rate)
138 if (clk == NULL || !clk->round_rate)
141 return clk->round_rate(clk, rate);
144 int clk_set_parent(struct clk *clk, struct clk *parent)
146 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
147 clk ? clk->parent : NULL);
149 if (!clk || clk == parent)
152 if (clk->set_parent) {
155 ret = clk->set_parent(clk, parent);
159 clk->parent = parent;
163 void set_usboh3_clk(void)
165 clrsetbits_le32(&mxc_ccm->cscmr1,
166 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
167 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
168 clrsetbits_le32(&mxc_ccm->cscdr1,
169 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
170 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
171 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
172 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
175 void enable_usboh3_clk(unsigned char enable)
177 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
179 clrsetbits_le32(&mxc_ccm->CCGR2,
180 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
181 MXC_CCM_CCGR2_USBOH3_60M(cg));
184 void ipu_clk_enable(void)
186 /* IPU root clock derived from AXI B */
187 clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
188 MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
190 setbits_le32(&mxc_ccm->CCGR5,
191 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
193 /* Handshake with IPU when certain clock rates are changed. */
194 clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
196 /* Handshake with IPU when LPM is entered as its enabled. */
197 clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
200 void ipu_clk_disable(void)
202 clrbits_le32(&mxc_ccm->CCGR5,
203 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
205 /* Handshake with IPU when certain clock rates are changed. */
206 setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
208 /* Handshake with IPU when LPM is entered as its enabled. */
209 setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
212 void ipu_di_clk_enable(int di)
216 setbits_le32(&mxc_ccm->CCGR6,
217 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
220 setbits_le32(&mxc_ccm->CCGR6,
221 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
224 printf("%s: Invalid DI index %d\n", __func__, di);
228 void ipu_di_clk_disable(int di)
232 clrbits_le32(&mxc_ccm->CCGR6,
233 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
236 clrbits_le32(&mxc_ccm->CCGR6,
237 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
240 printf("%s: Invalid DI index %d\n", __func__, di);
245 void ldb_clk_enable(int ldb)
249 setbits_le32(&mxc_ccm->CCGR6,
250 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
253 setbits_le32(&mxc_ccm->CCGR6,
254 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
257 printf("%s: Invalid LDB index %d\n", __func__, ldb);
261 void ldb_clk_disable(int ldb)
265 clrbits_le32(&mxc_ccm->CCGR6,
266 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
269 clrbits_le32(&mxc_ccm->CCGR6,
270 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
273 printf("%s: Invalid LDB index %d\n", __func__, ldb);
278 #ifdef CONFIG_I2C_MXC
279 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
280 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
284 #if defined(CONFIG_MX51)
286 #elif defined(CONFIG_MX53)
290 mask = MXC_CCM_CCGR_CG_MASK <<
291 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
293 setbits_le32(&mxc_ccm->CCGR1, mask);
295 clrbits_le32(&mxc_ccm->CCGR1, mask);
300 void set_usb_phy_clk(void)
302 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
305 #if defined(CONFIG_MX51)
306 void enable_usb_phy1_clk(unsigned char enable)
308 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
310 clrsetbits_le32(&mxc_ccm->CCGR2,
311 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
312 MXC_CCM_CCGR2_USB_PHY(cg));
315 void enable_usb_phy2_clk(unsigned char enable)
317 /* i.MX51 has a single USB PHY clock, so do nothing here. */
319 #elif defined(CONFIG_MX53)
320 void enable_usb_phy1_clk(unsigned char enable)
322 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
324 clrsetbits_le32(&mxc_ccm->CCGR4,
325 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
326 MXC_CCM_CCGR4_USB_PHY1(cg));
329 void enable_usb_phy2_clk(unsigned char enable)
331 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
333 clrsetbits_le32(&mxc_ccm->CCGR4,
334 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
335 MXC_CCM_CCGR4_USB_PHY2(cg));
340 * Calculate the frequency of PLLn.
342 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
345 int mfd, mfn, mfi, pdf, ret;
346 uint64_t refclk, temp;
349 ctrl = readl(&pll->ctrl);
351 if (ctrl & MXC_DPLLC_CTL_HFSM) {
352 mfn = readl(&pll->hfs_mfn);
353 mfd = readl(&pll->hfs_mfd);
354 op = readl(&pll->hfs_op);
356 mfn = readl(&pll->mfn);
357 mfd = readl(&pll->mfd);
358 op = readl(&pll->op);
361 mfd &= MXC_DPLLC_MFD_MFD_MASK;
362 mfn &= MXC_DPLLC_MFN_MFN_MASK;
363 pdf = op & MXC_DPLLC_OP_PDF_MASK;
364 mfi = MXC_DPLLC_OP_MFI_RD(op);
371 if (mfn >= 0x04000000) {
378 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
381 temp = refclk * mfn_abs;
382 do_div(temp, mfd + 1);
396 * This function returns the Frequency Pre-Multiplier clock.
398 static u32 get_fpm(void)
401 u32 ccr = readl(&mxc_ccm->ccr);
403 if (ccr & MXC_CCM_CCR_FPM_MULT)
408 return MXC_CLK32 * mult;
413 * This function returns the low power audio clock.
415 static u32 get_lp_apm(void)
418 u32 ccsr = readl(&mxc_ccm->ccsr);
420 if (ccsr & MXC_CCM_CCSR_LP_APM)
421 #if defined(CONFIG_MX51)
423 #elif defined(CONFIG_MX53)
424 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
435 u32 get_mcu_main_clk(void)
439 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
440 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
441 return freq / (reg + 1);
445 * Get the rate of peripheral's root clock.
447 u32 get_periph_clk(void)
451 reg = readl(&mxc_ccm->cbcdr);
452 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
453 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
454 reg = readl(&mxc_ccm->cbcmr);
455 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
457 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
459 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
469 * Get the rate of ipg clock.
471 static u32 get_ipg_clk(void)
473 uint32_t freq, reg, div;
475 freq = get_ahb_clk();
477 reg = readl(&mxc_ccm->cbcdr);
478 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
484 * Get the rate of ipg_per clock.
486 static u32 get_ipg_per_clk(void)
488 u32 freq, pred1, pred2, podf;
490 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
491 return get_ipg_clk();
493 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
496 freq = get_periph_clk();
497 podf = readl(&mxc_ccm->cbcdr);
498 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
499 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
500 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
501 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
504 /* Get the output clock rate of a standard PLL MUX for peripherals. */
505 static u32 get_standard_pll_sel_clk(u32 clk_sel)
509 switch (clk_sel & 0x3) {
511 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
514 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
517 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
528 * Get the rate of uart clk.
530 static u32 get_uart_clk(void)
532 unsigned int clk_sel, freq, reg, pred, podf;
534 reg = readl(&mxc_ccm->cscmr1);
535 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
536 freq = get_standard_pll_sel_clk(clk_sel);
538 reg = readl(&mxc_ccm->cscdr1);
539 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
540 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
541 freq /= (pred + 1) * (podf + 1);
547 * get cspi clock rate.
549 static u32 imx_get_cspiclk(void)
551 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
552 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
553 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
555 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
556 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
557 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
558 freq = get_standard_pll_sel_clk(clk_sel);
559 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
564 * get esdhc clock rate.
566 static u32 get_esdhc_clk(u32 port)
568 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
569 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
570 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
574 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
575 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
576 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
579 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
580 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
581 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
584 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
585 return get_esdhc_clk(1);
587 return get_esdhc_clk(0);
589 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
590 return get_esdhc_clk(1);
592 return get_esdhc_clk(0);
597 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
601 static u32 get_axi_a_clk(void)
603 u32 cbcdr = readl(&mxc_ccm->cbcdr);
604 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
606 return get_periph_clk() / (pdf + 1);
609 static u32 get_axi_b_clk(void)
611 u32 cbcdr = readl(&mxc_ccm->cbcdr);
612 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
614 return get_periph_clk() / (pdf + 1);
617 static u32 get_emi_slow_clk(void)
619 u32 cbcdr = readl(&mxc_ccm->cbcdr);
620 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
621 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
624 return get_ahb_clk() / (pdf + 1);
626 return get_periph_clk() / (pdf + 1);
629 static u32 get_ddr_clk(void)
632 u32 cbcmr = readl(&mxc_ccm->cbcmr);
633 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
635 u32 cbcdr = readl(&mxc_ccm->cbcdr);
636 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
637 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
639 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
640 ret_val /= ddr_clk_podf + 1;
645 switch (ddr_clk_sel) {
647 ret_val = get_axi_a_clk();
650 ret_val = get_axi_b_clk();
653 ret_val = get_emi_slow_clk();
656 ret_val = get_ahb_clk();
666 * The API of get mxc clocks.
668 unsigned int mxc_get_clock(enum mxc_clock clk)
672 return get_mcu_main_clk();
674 return get_ahb_clk();
676 return get_ipg_clk();
679 return get_ipg_per_clk();
681 return get_uart_clk();
683 return imx_get_cspiclk();
685 return get_esdhc_clk(0);
687 return get_esdhc_clk(1);
689 return get_esdhc_clk(2);
691 return get_esdhc_clk(3);
693 return get_ipg_clk();
695 return get_ahb_clk();
697 return get_ddr_clk();
704 u32 imx_get_uartclk(void)
706 return get_uart_clk();
709 u32 imx_get_fecclk(void)
711 return get_ipg_clk();
714 static int gcd(int m, int n)
729 * This is to calculate various parameters based on reference clock and
730 * targeted clock based on the equation:
731 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
732 * This calculation is based on a fixed MFD value for simplicity.
734 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
736 int pd, mfi = 1, mfn, mfd;
741 * Make sure targeted freq is in the valid range.
742 * Otherwise the following calculation might be wrong!!!
744 if (target < PLL_FREQ_MIN(ref) ||
745 target > PLL_FREQ_MAX(ref)) {
746 printf("Targeted pll clock should be within [%d - %d]\n",
747 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
748 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
752 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
753 if (fixed_mfd[i].ref_clk_hz == ref) {
754 mfd = fixed_mfd[i].mfd;
759 if (i == ARRAY_SIZE(fixed_mfd))
762 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
763 t1 = (u64)target * pd;
764 do_div(t1, (4 * ref));
766 if (mfi > PLL_MFI_MAX)
773 * Now got pd and mfi already
775 * mfn = (((target * pd) / 4 - ref * mfi) * mfd) / ref;
777 t1 = (u64)target * pd;
779 t1 = (t1 - ref * mfi) * mfd;
789 debug("ref=%d, target=%d, pd=%d, mfi=%d, mfn=%d, mfd=%d\n",
790 ref, target, pd, mfi, mfn, mfd);
799 #define calc_div(tgt_clk, src_clk, limit) ({ \
801 if (((src_clk) % (tgt_clk)) <= 100) \
802 v = (src_clk) / (tgt_clk); \
804 v = ((src_clk) / (tgt_clk)) + 1;\
810 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
812 __raw_writel(0x1232, &pll->ctrl); \
813 __raw_writel(0x2, &pll->config); \
814 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
816 __raw_writel(fn, &(pll->mfn)); \
817 __raw_writel((fd) - 1, &pll->mfd); \
818 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
820 __raw_writel(fn, &pll->hfs_mfn); \
821 __raw_writel((fd) - 1, &pll->hfs_mfd); \
822 __raw_writel(0x1232, &pll->ctrl); \
823 while (!__raw_readl(&pll->ctrl) & 0x1) \
827 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
829 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
830 struct mxc_pll_reg *pll = mxc_plls[index];
834 /* Switch ARM to PLL2 clock */
835 __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
836 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
837 pll_param->mfi, pll_param->mfn,
840 __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
843 /* Switch to pll2 bypass clock */
844 __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
845 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
846 pll_param->mfi, pll_param->mfn,
849 __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
852 /* Switch to pll3 bypass clock */
853 __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
854 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
855 pll_param->mfi, pll_param->mfn,
858 __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
862 /* Switch to pll4 bypass clock */
863 __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
864 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
865 pll_param->mfi, pll_param->mfn,
868 __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
878 static int __adjust_core_voltage_stub(u32 freq)
882 int adjust_core_voltage(u32 freq)
883 __attribute__((weak, alias("__adjust_core_voltage_stub")));
885 /* Config CPU clock */
886 static int config_core_clk(u32 ref, u32 freq)
889 struct pll_param pll_param;
890 u32 cur_freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
892 if (freq == cur_freq)
895 memset(&pll_param, 0, sizeof(struct pll_param));
897 /* The case that periph uses PLL1 is not considered here */
898 ret = calc_pll_params(ref, freq, &pll_param);
900 printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n",
901 freq / 1000000, freq / 1000 % 1000,
902 ref / 1000000, ref / 1000 % 1000);
905 if (freq > cur_freq) {
906 ret = adjust_core_voltage(freq);
908 printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
909 cur_freq / 1000000, cur_freq / 1000 % 1000,
910 freq / 1000000, freq / 1000 % 1000);
913 ret = config_pll_clk(PLL1_CLOCK, &pll_param);
915 adjust_core_voltage(cur_freq);
918 ret = config_pll_clk(PLL1_CLOCK, &pll_param);
922 ret = adjust_core_voltage(freq);
924 printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
925 cur_freq / 1000000, cur_freq / 1000 % 1000,
926 freq / 1000000, freq / 1000 % 1000);
927 calc_pll_params(ref, cur_freq, &pll_param);
928 config_pll_clk(PLL1_CLOCK, &pll_param);
934 static int config_nfc_clk(u32 nfc_clk)
936 u32 parent_rate = get_emi_slow_clk();
941 div = parent_rate / nfc_clk;
944 if (parent_rate / div > NFC_CLK_MAX)
946 clrsetbits_le32(&mxc_ccm->cbcdr,
947 MXC_CCM_CBCDR_NFC_PODF_MASK,
948 MXC_CCM_CBCDR_NFC_PODF(div - 1));
949 while (readl(&mxc_ccm->cdhipr) != 0)
954 void enable_nfc_clk(unsigned char enable)
956 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
958 clrsetbits_le32(&mxc_ccm->CCGR5,
959 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
960 MXC_CCM_CCGR5_EMI_ENFC(cg));
963 /* Config main_bus_clock for periphs */
964 static int config_periph_clk(u32 ref, u32 freq)
967 struct pll_param pll_param;
969 memset(&pll_param, 0, sizeof(struct pll_param));
971 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
972 ret = calc_pll_params(ref, freq, &pll_param);
974 printf("Error:Can't find pll parameters: %d\n",
978 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
979 readl(&mxc_ccm->cbcmr))) {
981 return config_pll_clk(PLL1_CLOCK, &pll_param);
984 return config_pll_clk(PLL3_CLOCK, &pll_param);
994 static int config_ddr_clk(u32 emi_clk)
997 s32 shift = 0, clk_sel, div = 1;
998 u32 cbcmr = readl(&mxc_ccm->cbcmr);
1000 if (emi_clk > MAX_DDR_CLK) {
1001 printf("Warning:DDR clock should not exceed %d MHz\n",
1002 MAX_DDR_CLK / SZ_DEC_1M);
1003 emi_clk = MAX_DDR_CLK;
1006 clk_src = get_periph_clk();
1007 /* Find DDR clock input */
1008 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
1026 if ((clk_src % emi_clk) < 10000000)
1027 div = clk_src / emi_clk;
1029 div = (clk_src / emi_clk) + 1;
1033 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
1034 while (readl(&mxc_ccm->cdhipr) != 0)
1036 writel(0x0, &mxc_ccm->ccdr);
1042 * This function assumes the expected core clock has to be changed by
1043 * modifying the PLL. This is NOT true always but for most of the times,
1044 * it is. So it assumes the PLL output freq is the same as the expected
1045 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1046 * In the latter case, it will try to increase the presc value until
1047 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1048 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1049 * on the targeted PLL and reference input clock to the PLL. Lastly,
1050 * it sets the register based on these values along with the dividers.
1051 * Note 1) There is no value checking for the passed-in divider values
1052 * so the caller has to make sure those values are sensible.
1053 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1054 * exceed NFC_CLK_MAX.
1055 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1056 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1057 * 4) This function should not have allowed diag_printf() calls since
1058 * the serial driver has been stoped. But leave then here to allow
1059 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1061 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1067 if (config_core_clk(ref, freq))
1070 case MXC_PERIPH_CLK:
1071 if (config_periph_clk(ref, freq))
1075 if (config_ddr_clk(freq))
1079 if (config_nfc_clk(freq))
1083 printf("Warning:Unsupported or invalid clock type\n");
1091 * The clock for the external interface can be set to use internal clock
1092 * if fuse bank 4, row 3, bit 2 is set.
1093 * This is an undocumented feature and it was confirmed by Freescale's support:
1094 * Fuses (but not pins) may be used to configure SATA clocks.
1095 * Particularly the i.MX53 Fuse_Map contains the next information
1096 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
1097 * '00' - 100MHz (External)
1098 * '01' - 50MHz (External)
1099 * '10' - 120MHz, internal (USB PHY)
1102 void mxc_set_sata_internal_clock(void)
1105 (u32 *)(IIM_BASE_ADDR + 0x180c);
1109 clrsetbits_le32(tmp_base, 0x6, 0x4);
1114 * Dump some core clockes.
1116 #define pr_clk_val(c, v) { \
1117 printf("%-11s %3lu.%03lu MHz\n", #c, \
1118 (v) / 1000000, (v) / 1000 % 1000); \
1121 #define pr_clk(c) { \
1122 unsigned long __clk = mxc_get_clock(MXC_##c##_CLK); \
1123 pr_clk_val(c, __clk); \
1126 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1130 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
1131 pr_clk_val(PLL1, freq);
1132 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
1133 pr_clk_val(PLL2, freq);
1134 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
1135 pr_clk_val(PLL3, freq);
1137 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
1138 pr_clk_val(PLL4, freq);
1146 #ifdef CONFIG_MXC_SPI
1152 /***************************************************/
1155 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,