3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
42 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
43 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
44 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
45 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
47 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
54 * Calculate the frequency of PLLn.
56 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
58 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
59 uint64_t refclk, temp;
62 ctrl = readl(&pll->ctrl);
64 if (ctrl & MXC_DPLLC_CTL_HFSM) {
65 mfn = __raw_readl(&pll->hfs_mfn);
66 mfd = __raw_readl(&pll->hfs_mfd);
67 op = __raw_readl(&pll->hfs_op);
69 mfn = __raw_readl(&pll->mfn);
70 mfd = __raw_readl(&pll->mfd);
71 op = __raw_readl(&pll->op);
74 mfd &= MXC_DPLLC_MFD_MFD_MASK;
75 mfn &= MXC_DPLLC_MFN_MFN_MASK;
76 pdf = op & MXC_DPLLC_OP_PDF_MASK;
77 mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
84 if (mfn >= 0x04000000) {
91 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
95 temp = refclk * mfn_abs;
96 do_div(temp, mfd + 1);
110 u32 get_mcu_main_clk(void)
114 reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
115 MXC_CCM_CACRR_ARM_PODF_OFFSET;
116 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
117 return freq / (reg + 1);
121 * Get the rate of peripheral's root clock.
123 static u32 get_periph_clk(void)
127 reg = __raw_readl(&mxc_ccm->cbcdr);
128 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
129 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
130 reg = __raw_readl(&mxc_ccm->cbcmr);
131 switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
132 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
134 return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
136 return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
144 * Get the rate of ipg clock.
146 static u32 get_ipg_clk(void)
148 u32 ahb_podf, ipg_podf;
150 ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
151 ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
152 MXC_CCM_CBCDR_IPG_PODF_OFFSET;
153 ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
154 MXC_CCM_CBCDR_AHB_PODF_OFFSET;
155 return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
159 * Get the rate of ipg_per clock.
161 static u32 get_ipg_per_clk(void)
163 u32 pred1, pred2, podf;
165 if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
166 return get_ipg_clk();
167 /* Fixme: not handle what about lpm*/
168 podf = __raw_readl(&mxc_ccm->cbcdr);
169 pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
170 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
171 pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
172 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
173 podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
174 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
176 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
180 * Get the rate of uart clk.
182 static u32 get_uart_clk(void)
184 unsigned int freq, reg, pred, podf;
186 reg = __raw_readl(&mxc_ccm->cscmr1);
187 switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
188 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
190 freq = decode_pll(mxc_plls[PLL1_CLOCK],
191 CONFIG_SYS_MX5_HCLK);
194 freq = decode_pll(mxc_plls[PLL2_CLOCK],
195 CONFIG_SYS_MX5_HCLK);
198 freq = decode_pll(mxc_plls[PLL3_CLOCK],
199 CONFIG_SYS_MX5_HCLK);
205 reg = __raw_readl(&mxc_ccm->cscdr1);
207 pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
208 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
210 podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
211 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
212 freq /= (pred + 1) * (podf + 1);
218 * This function returns the low power audio clock.
223 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
225 if (((ccsr >> 9) & 1) == 0)
226 ret_val = CONFIG_SYS_MX5_HCLK;
228 ret_val = ((32768 * 1024));
234 * get cspi clock rate.
236 u32 imx_get_cspiclk(void)
238 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
239 u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
240 u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
242 pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
243 >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
244 pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
245 >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
246 clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
247 >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
251 ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
252 CONFIG_SYS_MX5_HCLK) /
253 ((pre_pdf + 1) * (pdf + 1));
256 ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
257 CONFIG_SYS_MX5_HCLK) /
258 ((pre_pdf + 1) * (pdf + 1));
261 ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
262 CONFIG_SYS_MX5_HCLK) /
263 ((pre_pdf + 1) * (pdf + 1));
266 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
274 * The API of get mxc clockes.
276 unsigned int mxc_get_clock(enum mxc_clock clk)
280 return get_mcu_main_clk();
284 return get_ipg_clk();
286 return get_ipg_per_clk();
288 return get_uart_clk();
290 return imx_get_cspiclk();
292 return decode_pll(mxc_plls[PLL1_CLOCK],
293 CONFIG_SYS_MX5_HCLK);
300 u32 imx_get_uartclk(void)
302 return get_uart_clk();
306 u32 imx_get_fecclk(void)
308 return mxc_get_clock(MXC_IPG_CLK);
312 * Dump some core clockes.
314 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
318 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
319 printf("pll1: %dMHz\n", freq / 1000000);
320 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
321 printf("pll2: %dMHz\n", freq / 1000000);
322 freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
323 printf("pll3: %dMHz\n", freq / 1000000);
325 freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
326 printf("pll4: %dMHz\n", freq / 1000000);
328 printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
329 printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
334 /***************************************************/
337 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,