2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <generated/asm-offsets.h>
12 #include <linux/linkage.h>
14 .section ".text.init", "x"
16 .macro init_arm_erratum
17 /* ARM erratum ID #468414 */
18 mrc 15, 0, r1, c1, c0, 1
19 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
20 mcr 15, 0, r1, c1, c0, 1
24 * L2CC Cache setup/invalidation/disable
27 /* explicitly disable L2 cache */
28 mrc 15, 0, r0, c1, c0, 1
30 mcr 15, 0, r0, c1, c0, 1
32 /* reconfigure L2 cache aux control reg */
33 ldr r0, =0xC0 | /* tag RAM */ \
34 0x4 | /* data RAM */ \
35 1 << 24 | /* disable write allocate delay */ \
36 1 << 23 | /* disable write allocate combine */ \
37 1 << 22 /* disable write allocate */
39 #if defined(CONFIG_MX51)
40 ldr r3, [r4, #ROM_SI_REV]
43 /* disable write combine for TO 2 and lower revs */
44 orrls r0, r0, #1 << 25
47 mcr 15, 1, r0, c9, c0, 2
50 mrc 15, 0, r0, c1, c0, 1
52 mcr 15, 0, r0, c1, c0, 1
56 /* AIPS setup - Only setup MPROTx registers.
57 * The PACR default values are good.*/
60 * Set all MPROTx to be non-bufferable, trusted for R/W,
61 * not forced to user-mode.
63 ldr r0, =AIPS1_BASE_ADDR
67 ldr r0, =AIPS2_BASE_ADDR
71 * Clear the on and off peripheral modules Supervisor Protect bit
72 * for SDMA to access them. Did not change the AIPS control registers
73 * (offset 0x20) access type
80 /* VPU and IPU given higher priority (0x4)
81 * IPU accesses with ID=0x1 given highest priority (=0xA)
83 ldr r0, =M4IF_BASE_ADDR
99 .macro setup_pll pll, freq
111 str r1, [r3, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
113 str r1, [r3, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
115 ldr r1, [r2, #W_DP_OP]
116 str r1, [r3, #PLL_DP_OP]
117 str r1, [r3, #PLL_DP_HFS_OP]
119 ldr r1, [r2, #W_DP_MFD]
120 str r1, [r3, #PLL_DP_MFD]
121 str r1, [r3, #PLL_DP_HFS_MFD]
123 ldr r1, [r2, #W_DP_MFN]
124 str r1, [r3, #PLL_DP_MFN]
125 str r1, [r3, #PLL_DP_HFS_MFN]
128 str r1, [r3, #PLL_DP_CTL]
129 1: ldr r1, [r3, #PLL_DP_CTL]
133 /* r10 saved upper lr */
136 .macro setup_pll_errata pll, freq
138 str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
140 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
141 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
146 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
147 str r5, [r2, #PLL_DP_HFS_MFN]
150 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
152 2: ldr r1, [r2, #PLL_DP_CONFIG]
156 ldr r1, =100 /* Wait at least 4 us */
161 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
165 ldr r0, =CCM_BASE_ADDR
166 #if defined (CONFIG_MX51)
167 /* Gate off clocks to the peripherals first */
169 str r1, [r0, #CLKCTL_CCGR0]
170 str r4, [r0, #CLKCTL_CCGR1]
171 str r4, [r0, #CLKCTL_CCGR2]
172 str r4, [r0, #CLKCTL_CCGR3]
175 str r1, [r0, #CLKCTL_CCGR4]
177 str r1, [r0, #CLKCTL_CCGR5]
179 str r1, [r0, #CLKCTL_CCGR6]
181 /* Disable IPU and HSC dividers */
183 str r1, [r0, #CLKCTL_CCDR]
185 /* Make sure to switch the DDR away from PLL 1 */
187 str r1, [r0, #CLKCTL_CBCDR]
188 /* make sure divider effective */
189 1: ldr r1, [r0, #CLKCTL_CDHIPR]
193 /* Switch ARM to step clock */
195 str r1, [r0, #CLKCTL_CCSR]
197 #if defined(CONFIG_MX51_PLL_ERRATA)
198 setup_pll PLL1_BASE_ADDR, 864
199 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
201 #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
202 setup_pll PLL1_BASE_ADDR, 800
203 #elif CONFIG_SYS_CPU_CLK == 600
204 setup_pll PLL1_BASE_ADDR, 600
206 #error Unsupported CONFIG_SYS_CPU_CLK value
210 setup_pll PLL3_BASE_ADDR, 665
212 /* Switch peripheral to PLL 3 */
213 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
214 str r1, [r0, #CLKCTL_CBCMR]
216 str r1, [r0, #CLKCTL_CBCDR]
217 setup_pll PLL2_BASE_ADDR, 665
219 /* Switch peripheral to PLL2 */
221 str r1, [r0, #CLKCTL_CBCDR]
222 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
223 str r1, [r0, #CLKCTL_CBCMR]
225 setup_pll PLL3_BASE_ADDR, 216
227 /* Set the platform clock dividers */
228 ldr r0, =ARM_BASE_ADDR
232 ldr r0, =CCM_BASE_ADDR
234 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
235 ldr r3, [r4, #ROM_SI_REV]
240 str r1, [r0, #CLKCTL_CACRR]
242 /* Switch ARM back to PLL 1 */
243 str r4, [r0, #CLKCTL_CCSR]
246 /* Use lp_apm (24MHz) source for perclk */
247 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
248 str r1, [r0, #CLKCTL_CBCMR]
249 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
250 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
251 str r1, [r0, #CLKCTL_CBCDR]
253 /* Restore the default values in the Gate registers */
255 str r1, [r0, #CLKCTL_CCGR0]
256 str r1, [r0, #CLKCTL_CCGR1]
257 str r1, [r0, #CLKCTL_CCGR2]
258 str r1, [r0, #CLKCTL_CCGR3]
259 str r1, [r0, #CLKCTL_CCGR4]
260 str r1, [r0, #CLKCTL_CCGR5]
261 str r1, [r0, #CLKCTL_CCGR6]
263 /* Use PLL 2 for UART's, get 66.5MHz from it */
265 str r1, [r0, #CLKCTL_CSCMR1]
267 str r1, [r0, #CLKCTL_CSCDR1]
268 /* make sure divider effective */
269 1: ldr r1, [r0, #CLKCTL_CDHIPR]
273 str r4, [r0, #CLKCTL_CCDR]
275 /* for cko - for ARM div by 8 */
277 add r1, r1, #0x00000F0
278 str r1, [r0, #CLKCTL_CCOSR]
279 #else /* CONFIG_MX53 */
280 /* Gate off clocks to the peripherals first */
282 str r1, [r0, #CLKCTL_CCGR0]
283 str r4, [r0, #CLKCTL_CCGR1]
284 str r4, [r0, #CLKCTL_CCGR2]
285 str r4, [r0, #CLKCTL_CCGR3]
286 str r4, [r0, #CLKCTL_CCGR7]
288 str r1, [r0, #CLKCTL_CCGR4]
290 str r1, [r0, #CLKCTL_CCGR5]
292 str r1, [r0, #CLKCTL_CCGR6]
294 /* Switch ARM to step clock */
296 str r1, [r0, #CLKCTL_CCSR]
298 #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
299 setup_pll PLL1_BASE_ADDR, 800
300 #elif CONFIG_SYS_CPU_CLK == 600
301 setup_pll PLL1_BASE_ADDR, 600
303 #error Unsupported CONFIG_SYS_CPU_CLK value
306 setup_pll PLL3_BASE_ADDR, 400
308 /* Switch peripheral to PLL3 */
309 ldr r0, =CCM_BASE_ADDR
311 str r1, [r0, #CLKCTL_CBCMR]
313 str r1, [r0, #CLKCTL_CBCDR]
314 /* make sure change is effective */
315 1: ldr r1, [r0, #CLKCTL_CDHIPR]
319 setup_pll PLL2_BASE_ADDR, 400
321 /* Switch peripheral to PLL2 */
323 str r1, [r0, #CLKCTL_CBCDR]
326 str r1, [r0, #CLKCTL_CBCMR]
328 /* change uart clk parent to pll2 */
329 ldr r1, [r0, #CLKCTL_CSCMR1]
331 orr r1, r1, #(0x1 << 24)
332 str r1, [r0, #CLKCTL_CSCMR1]
334 /* make sure change is effective */
335 1: ldr r1, [r0, #CLKCTL_CDHIPR]
339 setup_pll PLL3_BASE_ADDR, 216
341 setup_pll PLL4_BASE_ADDR, 455
343 #else /* CONFIG_TX53 */
344 /* Switch peripheral to PLL 3 */
345 ldr r1, [r0, #CLKCTL_CBCMR]
347 orr r1, r1, #(1 << 12)
348 str r1, [r0, #CLKCTL_CBCMR]
350 ldr r1, [r0, #CLKCTL_CBCDR]
351 orr r1, r1, #(1 << 25)
352 str r1, [r0, #CLKCTL_CBCDR]
354 /* make sure change is effective */
355 ldr r1, [r0, #CLKCTL_CDHIPR]
359 #if CONFIG_SYS_SDRAM_CLK == 533
360 setup_pll PLL2_BASE_ADDR, 533
361 #elif CONFIG_SYS_SDRAM_CLK == 400
362 setup_pll PLL2_BASE_ADDR, 400
363 #elif CONFIG_SYS_SDRAM_CLK == 333
364 setup_pll PLL2_BASE_ADDR, 333
366 #error Unsupported CONFIG_SYS_SDRAM_CLK
369 /* Switch peripheral to PLL2 */
370 ldr r1, [r0, #CLKCTL_CBCDR]
372 str r1, [r0, #CLKCTL_CBCDR]
374 ldr r1, [r0, #CLKCTL_CBCMR]
377 str r1, [r0, #CLKCTL_CBCMR]
379 setup_pll PLL3_BASE_ADDR, 216
381 /* Set the platform clock dividers */
382 ldr r0, =ARM_BASE_ADDR
386 ldr r0, =CCM_BASE_ADDR
388 str r1, [r0, #CLKCTL_CACRR]
390 /* Switch ARM back to PLL 1. */
392 str r1, [r0, #CLKCTL_CCSR]
394 /* make uart div=6 */
395 ldr r1, [r0, #CLKCTL_CSCDR1]
398 str r1, [r0, #CLKCTL_CSCDR1]
399 /* make sure divider effective */
400 1: ldr r1, [r0, #CLKCTL_CDHIPR]
404 /* Restore the default values in the Gate registers */
406 str r1, [r0, #CLKCTL_CCGR0]
407 str r1, [r0, #CLKCTL_CCGR1]
408 str r1, [r0, #CLKCTL_CCGR2]
409 str r1, [r0, #CLKCTL_CCGR3]
410 str r1, [r0, #CLKCTL_CCGR4]
411 str r1, [r0, #CLKCTL_CCGR5]
412 str r1, [r0, #CLKCTL_CCGR6]
413 str r1, [r0, #CLKCTL_CCGR7]
416 str r1, [r0, #CLKCTL_CCDR]
418 /* for cko - for ARM div by 8 */
420 add r1, r1, #0x00000F0
421 str r1, [r0, #CLKCTL_CCOSR]
423 #endif /* CONFIG_MX53 */
428 mov r4, #0 /* Fix R4 to 0 */
430 #if defined(CONFIG_SYS_MAIN_PWR_ON)
431 ldr r0, =GPIO1_BASE_ADDR
451 ENDPROC(lowlevel_init)
453 /* Board level setting value */
454 #if defined(CONFIG_MX51_PLL_ERRATA)
455 W_DP_864: .word DP_OP_864
458 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
460 W_DP_800: .word DP_OP_800
464 #if defined(CONFIG_MX51)
465 W_DP_665: .word DP_OP_665
468 W_DP_600: .word DP_OP_600
472 W_DP_216: .word DP_OP_216
475 W_DP_400: .word DP_OP_400
478 W_DP_455: .word DP_OP_455
481 W_DP_533: .word DP_OP_533