2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #define PLL_LOCK_BIT (1 << 31)
121 static inline int wait_pll_lock(u32 *reg)
126 while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
132 if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
137 #ifdef CONFIG_MXC_OCOTP
138 void enable_ocotp_clk(unsigned char enable)
141 static int enabled __attribute__((section(".data")));
144 printf("ERROR: unbalanced enable/disable ocotp_clk\n");
147 if (enable && enabled++)
149 if (!enable && --enabled)
152 reg = __raw_readl(&imx_ccm->CCGR2);
154 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
156 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
157 __raw_writel(reg, &imx_ccm->CCGR2);
161 #ifdef CONFIG_NAND_MXS
162 void setup_gpmi_io_clk(u32 cfg)
164 /* Disable clocks per ERR007177 from MX6 errata */
165 clrbits_le32(&imx_ccm->CCGR4,
166 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
167 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
168 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
169 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
170 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
172 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
174 clrsetbits_le32(&imx_ccm->cs2cdr,
175 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
176 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
177 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
180 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
181 setbits_le32(&imx_ccm->CCGR4,
182 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
183 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
184 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
185 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
186 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
190 void enable_usboh3_clk(unsigned char enable)
194 reg = __raw_readl(&imx_ccm->CCGR6);
196 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
198 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
199 __raw_writel(reg, &imx_ccm->CCGR6);
203 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
204 void enable_enet_clk(unsigned char enable)
208 if (is_cpu_type(MXC_CPU_MX6UL)) {
209 mask = MXC_CCM_CCGR3_ENET_MASK;
210 addr = &imx_ccm->CCGR3;
212 mask = MXC_CCM_CCGR1_ENET_MASK;
213 addr = &imx_ccm->CCGR1;
217 setbits_le32(addr, mask);
219 clrbits_le32(addr, mask);
223 #ifdef CONFIG_MXC_UART
224 void enable_uart_clk(unsigned char enable)
228 if (is_cpu_type(MXC_CPU_MX6UL))
229 mask = MXC_CCM_CCGR5_UART_MASK;
231 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
234 setbits_le32(&imx_ccm->CCGR5, mask);
236 clrbits_le32(&imx_ccm->CCGR5, mask);
241 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
248 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
250 setbits_le32(&imx_ccm->CCGR6, mask);
252 clrbits_le32(&imx_ccm->CCGR6, mask);
258 #ifdef CONFIG_SYS_I2C_MXC
259 /* i2c_num can be from 0 - 3 */
260 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
269 mask = MXC_CCM_CCGR_CG_MASK
270 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
272 reg = __raw_readl(&imx_ccm->CCGR2);
277 __raw_writel(reg, &imx_ccm->CCGR2);
279 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
280 mask = MXC_CCM_CCGR6_I2C4_MASK;
281 addr = &imx_ccm->CCGR6;
283 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
284 addr = &imx_ccm->CCGR1;
286 reg = __raw_readl(addr);
291 __raw_writel(reg, addr);
297 /* spi_num can be from 0 - SPI_MAX_NUM */
298 int enable_spi_clk(unsigned char enable, unsigned spi_num)
303 if (spi_num > SPI_MAX_NUM)
306 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
307 reg = __raw_readl(&imx_ccm->CCGR1);
312 __raw_writel(reg, &imx_ccm->CCGR1);
316 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
319 u32 pll_num, pll_denom;
324 div = __raw_readl(&anatop->pll_arm);
325 if (div & BM_ANADIG_PLL_ARM_BYPASS)
326 /* Assume the bypass clock is always derived from OSC */
328 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
330 return infreq * div / 2;
332 div = __raw_readl(&anatop->pll_528);
333 if (div & BM_ANADIG_PLL_528_BYPASS)
335 div &= BM_ANADIG_PLL_528_DIV_SELECT;
337 return infreq * (20 + div * 2);
339 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
340 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
342 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
344 return infreq * (20 + div * 2);
346 div = __raw_readl(&anatop->pll_audio);
347 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
348 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
351 pll_num = __raw_readl(&anatop->pll_audio_num);
352 pll_denom = __raw_readl(&anatop->pll_audio_denom);
354 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
355 BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
357 printf("Invalid post divider value for PLL_AUDIO\n");
360 post_div = 1 << (2 - post_div);
361 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
363 freq = (u64)infreq * pll_num / pll_denom;
364 freq += infreq * div;
365 return lldiv(freq, post_div);
367 div = __raw_readl(&anatop->pll_video);
368 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
369 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
372 pll_num = __raw_readl(&anatop->pll_video_num);
373 pll_denom = __raw_readl(&anatop->pll_video_denom);
375 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
376 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
378 printf("Invalid post divider value for PLL_VIDEO\n");
381 post_div = 1 << (2 - post_div);
382 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
384 freq = (u64)infreq * pll_num / pll_denom;
385 freq += infreq * div;
386 return lldiv(freq, post_div);
388 div = __raw_readl(&anatop->pll_enet);
389 if (div & BM_ANADIG_PLL_ENET_BYPASS)
391 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
393 return 25000000 * (div + (div >> 1) + 1);
395 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
396 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
398 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
400 return infreq * (20 + div * 2);
402 div = __raw_readl(&anatop->pll_mlb);
403 if (div & BM_ANADIG_PLL_MLB_BYPASS)
405 /* fallthru: unknown external clock provided on MLB_CLK pin */
412 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
419 if (!is_cpu_type(MXC_CPU_MX6UL)) {
421 /* No PFD3 on PPL2 */
425 div = __raw_readl(&anatop->pfd_528);
426 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
429 div = __raw_readl(&anatop->pfd_480);
430 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
433 /* No PFD on other PLL */
437 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
438 ANATOP_PFD_FRAC_SHIFT(pfd_num));
441 static u32 get_mcu_main_clk(void)
445 reg = __raw_readl(&imx_ccm->cacrr);
446 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
447 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
448 freq = decode_pll(PLL_ARM, MXC_HCLK);
450 return freq / (reg + 1);
453 u32 get_periph_clk(void)
455 u32 reg, div = 0, freq = 0;
457 reg = __raw_readl(&imx_ccm->cbcdr);
458 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
459 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
460 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
461 reg = __raw_readl(&imx_ccm->cbcmr);
462 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
463 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
467 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
475 reg = __raw_readl(&imx_ccm->cbcmr);
476 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
477 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
481 freq = decode_pll(PLL_528, MXC_HCLK);
484 freq = mxc_get_pll_pfd(PLL_528, 2);
487 freq = mxc_get_pll_pfd(PLL_528, 0);
490 /* static / 2 divider */
491 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
496 return freq / (div + 1);
499 static u32 get_ipg_clk(void)
503 reg = __raw_readl(&imx_ccm->cbcdr);
504 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
505 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
507 return get_ahb_clk() / (ipg_podf + 1);
510 static u32 get_ipg_per_clk(void)
512 u32 reg, perclk_podf;
514 reg = __raw_readl(&imx_ccm->cscmr1);
515 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
516 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
517 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
518 return MXC_HCLK; /* OSC 24Mhz */
521 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
523 return get_ipg_clk() / (perclk_podf + 1);
526 static u32 get_uart_clk(void)
529 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
530 reg = __raw_readl(&imx_ccm->cscdr1);
532 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
533 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
534 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
538 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
539 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
541 return freq / (uart_podf + 1);
544 static u32 get_cspi_clk(void)
548 reg = __raw_readl(&imx_ccm->cscdr2);
549 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
550 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
552 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
553 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
554 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
555 return MXC_HCLK / (cspi_podf + 1);
558 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
561 static u32 get_axi_clk(void)
563 u32 root_freq, axi_podf;
564 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
566 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
567 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
569 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
570 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
571 root_freq = mxc_get_pll_pfd(PLL_528, 2);
573 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
575 root_freq = get_periph_clk();
577 return root_freq / (axi_podf + 1);
580 static u32 get_emi_slow_clk(void)
582 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
584 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
585 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
586 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
587 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
588 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
590 switch (emi_clk_sel) {
592 root_freq = get_axi_clk();
595 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
598 root_freq = mxc_get_pll_pfd(PLL_528, 2);
601 root_freq = mxc_get_pll_pfd(PLL_528, 0);
605 return root_freq / (emi_slow_podf + 1);
608 static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
610 switch (nfc_clk_sel) {
612 return mxc_get_pll_pfd(PLL_528, 0);
615 return decode_pll(PLL_528, MXC_HCLK);
618 return decode_pll(PLL_USBOTG, MXC_HCLK);
621 return mxc_get_pll_pfd(PLL_528, 2);
624 return mxc_get_pll_pfd(PLL_USBOTG, 3);
630 static u32 get_nfc_clk(void)
632 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
633 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
634 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
635 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
636 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
637 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
638 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
639 u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
641 return root_freq / (pred + 1) / (podf + 1);
644 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
645 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
646 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
648 static int set_nfc_clk(u32 ref, u32 freq_khz)
650 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
657 u32 freq = freq_khz * 1000;
658 int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
660 for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
664 if (ref < num_sel && ref != nfc_clk_sel)
667 switch (nfc_clk_sel) {
669 root_freq = mxc_get_pll_pfd(PLL_528, 0);
672 root_freq = decode_pll(PLL_528, MXC_HCLK);
675 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
678 root_freq = mxc_get_pll_pfd(PLL_528, 2);
681 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
684 if (root_freq < freq)
687 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
688 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
689 act_freq = root_freq / pred / podf;
690 err = (freq - act_freq) / (freq / 1000);
691 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
692 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
696 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
697 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
698 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
705 if (nfc_val == ~0 || min_err > 100)
708 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
709 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
710 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
711 #ifdef CONFIG_NAND_MXS
712 setup_gpmi_io_clk(nfc_val);
714 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
718 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
723 static u32 get_mmdc_ch0_clk(void)
725 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
726 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
728 u32 freq, podf, per2_clk2_podf;
730 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
731 is_cpu_type(MXC_CPU_MX6SL)) {
732 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
733 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
734 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
735 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
736 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
737 if (is_cpu_type(MXC_CPU_MX6SL)) {
738 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
741 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
743 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
744 freq = decode_pll(PLL_528, MXC_HCLK);
746 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
751 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
752 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
754 freq = decode_pll(PLL_528, MXC_HCLK);
757 freq = mxc_get_pll_pfd(PLL_528, 2);
760 freq = mxc_get_pll_pfd(PLL_528, 0);
763 /* static / 2 divider */
764 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
768 return freq / (podf + 1) / (per2_clk2_podf + 1);
770 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
771 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
772 return get_periph_clk() / (podf + 1);
776 #ifdef CONFIG_FSL_QSPI
777 /* qspi_num can be from 0 - 1 */
778 void enable_qspi_clk(int qspi_num)
781 /* Enable QuadSPI clock */
784 /* disable the clock gate */
785 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
787 /* set 50M : (50 = 396 / 2 / 4) */
788 reg = readl(&imx_ccm->cscmr1);
789 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
790 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
791 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
792 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
793 writel(reg, &imx_ccm->cscmr1);
795 /* enable the clock gate */
796 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
800 * disable the clock gate
801 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
802 * disable both of them.
804 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
805 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
807 /* set 50M : (50 = 396 / 2 / 4) */
808 reg = readl(&imx_ccm->cs2cdr);
809 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
810 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
811 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
812 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
813 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
814 writel(reg, &imx_ccm->cs2cdr);
816 /*enable the clock gate*/
817 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
818 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
826 #ifdef CONFIG_FEC_MXC
827 int enable_fec_anatop_clock(enum enet_freq freq)
830 s32 timeout = 100000;
832 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
835 reg = readl(&anatop->pll_enet);
836 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
839 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
840 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
841 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
842 writel(reg, &anatop->pll_enet);
844 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
851 /* Enable FEC clock */
852 reg |= BM_ANADIG_PLL_ENET_ENABLE;
853 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
854 writel(reg, &anatop->pll_enet);
856 #ifdef CONFIG_SOC_MX6SX
858 * Set enet ahb clock to 200MHz
859 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
861 reg = readl(&imx_ccm->chsccdr);
862 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
863 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
864 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
866 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
868 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
869 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
870 writel(reg, &imx_ccm->chsccdr);
872 /* Enable enet system clock */
873 reg = readl(&imx_ccm->CCGR3);
874 reg |= MXC_CCM_CCGR3_ENET_MASK;
875 writel(reg, &imx_ccm->CCGR3);
881 static u32 get_usdhc_clk(u32 port)
883 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
884 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
885 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
889 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
890 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
891 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
895 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
896 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
897 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
901 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
902 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
903 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
907 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
908 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
909 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
917 root_freq = mxc_get_pll_pfd(PLL_528, 0);
919 root_freq = mxc_get_pll_pfd(PLL_528, 2);
921 return root_freq / (usdhc_podf + 1);
924 u32 imx_get_uartclk(void)
926 return get_uart_clk();
929 u32 imx_get_fecclk(void)
931 return mxc_get_clock(MXC_IPG_CLK);
934 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
935 static int enable_enet_pll(uint32_t en)
938 s32 timeout = 100000;
941 reg = readl(&anatop->pll_enet);
942 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
943 writel(reg, &anatop->pll_enet);
944 reg |= BM_ANADIG_PLL_ENET_ENABLE;
946 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
951 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
952 writel(reg, &anatop->pll_enet);
954 writel(reg, &anatop->pll_enet);
959 #ifdef CONFIG_CMD_SATA
960 static void ungate_sata_clock(void)
962 /* Enable SATA clock. */
963 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
966 int enable_sata_clock(void)
969 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
972 void disable_sata_clock(void)
974 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
978 #ifdef CONFIG_PCIE_IMX
979 static void ungate_pcie_clock(void)
981 /* Enable PCIe clock. */
982 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
985 int enable_pcie_clock(void)
992 * The register ANATOP_MISC1 is not documented in the Freescale
993 * MX6RM. The register that is mapped in the ANATOP space and
994 * marked as ANATOP_MISC1 is actually documented in the PMU section
995 * of the datasheet as PMU_MISC1.
997 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
998 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
999 * for PCI express link that is clocked from the i.MX6.
1001 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1002 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1003 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1004 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1005 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1007 if (is_cpu_type(MXC_CPU_MX6SX))
1008 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1010 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1012 clrsetbits_le32(&anatop_regs->ana_misc1,
1013 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1014 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1015 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1017 /* PCIe reference clock sourced from AXI. */
1018 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1020 /* Party time! Ungate the clock to the PCIe. */
1021 #ifdef CONFIG_CMD_SATA
1022 ungate_sata_clock();
1024 ungate_pcie_clock();
1026 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1027 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1031 #ifdef CONFIG_SECURE_BOOT
1032 void hab_caam_clock_enable(unsigned char enable)
1036 /* CG4 ~ CG6, CAAM clocks */
1037 reg = __raw_readl(&imx_ccm->CCGR0);
1039 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1040 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1041 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1043 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1044 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1045 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1046 __raw_writel(reg, &imx_ccm->CCGR0);
1049 reg = __raw_readl(&imx_ccm->CCGR6);
1051 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1053 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1054 __raw_writel(reg, &imx_ccm->CCGR6);
1058 static void enable_pll3(void)
1060 /* make sure pll3 is enabled */
1061 if ((readl(&anatop->usb1_pll_480_ctrl) &
1062 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1063 /* enable pll's power */
1064 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1065 &anatop->usb1_pll_480_ctrl_set);
1066 writel(0x80, &anatop->ana_misc2_clr);
1067 /* wait for pll lock */
1068 while ((readl(&anatop->usb1_pll_480_ctrl) &
1069 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1071 /* disable bypass */
1072 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1073 &anatop->usb1_pll_480_ctrl_clr);
1074 /* enable pll output */
1075 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1076 &anatop->usb1_pll_480_ctrl_set);
1080 void enable_thermal_clk(void)
1085 void ipu_clk_enable(void)
1087 u32 reg = readl(&imx_ccm->CCGR3);
1088 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1089 writel(reg, &imx_ccm->CCGR3);
1092 void ipu_clk_disable(void)
1094 u32 reg = readl(&imx_ccm->CCGR3);
1095 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1096 writel(reg, &imx_ccm->CCGR3);
1099 void ipu_di_clk_enable(int di)
1103 setbits_le32(&imx_ccm->CCGR3,
1104 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1107 setbits_le32(&imx_ccm->CCGR3,
1108 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1111 printf("%s: Invalid DI index %d\n", __func__, di);
1115 void ipu_di_clk_disable(int di)
1119 clrbits_le32(&imx_ccm->CCGR3,
1120 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1123 clrbits_le32(&imx_ccm->CCGR3,
1124 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1127 printf("%s: Invalid DI index %d\n", __func__, di);
1131 void ldb_clk_enable(int ldb)
1135 setbits_le32(&imx_ccm->CCGR3,
1136 MXC_CCM_CCGR3_LDB_DI0_MASK);
1139 setbits_le32(&imx_ccm->CCGR3,
1140 MXC_CCM_CCGR3_LDB_DI1_MASK);
1143 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1147 void ldb_clk_disable(int ldb)
1151 clrbits_le32(&imx_ccm->CCGR3,
1152 MXC_CCM_CCGR3_LDB_DI0_MASK);
1155 clrbits_le32(&imx_ccm->CCGR3,
1156 MXC_CCM_CCGR3_LDB_DI1_MASK);
1159 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1163 #ifdef CONFIG_VIDEO_MXS
1164 void lcdif_clk_enable(void)
1166 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1167 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1170 void lcdif_clk_disable(void)
1172 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1173 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1176 #define CBCMR_LCDIF_MASK MXC_CCM_CBCMR_LCDIF_PODF_MASK
1177 #define CSCDR2_LCDIF_MASK (MXC_CCM_CSCDR2_LCDIF_PRED_MASK | \
1178 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1180 static u32 get_lcdif_root_clk(u32 cscdr2)
1182 int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1183 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1184 int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1185 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1188 switch (lcdif_clk_sel) {
1190 switch (lcdif_pre_clk_sel) {
1192 root_freq = decode_pll(PLL_528, MXC_HCLK);
1195 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1198 root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1201 root_freq = mxc_get_pll_pfd(PLL_528, 0);
1204 root_freq = mxc_get_pll_pfd(PLL_528, 1);
1207 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1214 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1217 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1220 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1229 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1233 u64 freq = freq_khz * 1000;
1234 u32 post_div_mask = 1 << (2 - post_div);
1240 const int min_div = 27;
1241 const int max_div = 54;
1242 const int div_mask = 0x7f;
1243 const u32 max_freq = ref * max_div / post_div;
1244 const u32 min_freq = ref * min_div / post_div;
1246 if (freq > max_freq || freq < min_freq) {
1247 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1248 freq_khz / 1000, freq_khz % 1000,
1249 min_freq / 1000000, min_freq / 1000 % 1000,
1250 max_freq / 1000000, max_freq / 1000 % 1000);
1255 int m = lldiv(freq * d + ref - 1, ref);
1259 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1260 d, m, max_div, min_div);
1261 if (m > max_div || m < min_div)
1266 debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1271 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1272 d, m, f, freq, err);
1273 if (err < min_err) {
1278 if (min_err == ~0) {
1279 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1280 freq_khz / 1000, freq_khz % 1000);
1284 debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1285 mul, post_div, num, denom,
1286 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1287 ref * mul / post_div / 1000000,
1288 ref * mul / post_div / 1000 % 1000);
1290 reg = readl(&anatop->pll_video);
1291 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1293 reg = (reg & ~(div_mask |
1294 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1295 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1296 writel(reg, &anatop->pll_video);
1298 ret = wait_pll_lock(&anatop->pll_video);
1300 printf("Video PLL failed to lock\n");
1304 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1308 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1310 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1311 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1314 u32 freq = freq_khz * 1000;
1319 u32 min_pll_khz = ref * min_div / 4 / 1000;
1320 u32 max_pll_khz = ref * max_div / 1000;
1331 if (freq_khz > max_pll_khz)
1334 for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1335 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1336 m <= max_div; m++) {
1340 u32 root_freq = ref * m / pd;
1342 div = DIV_ROUND_UP(root_freq, freq);
1344 while (pred * podf == 0 && div <= 64) {
1347 for (p1 = 1; p1 <= 8; p1++) {
1348 for (p2 = 1; p2 <= 8; p2++) {
1349 if (p1 * p2 == div) {
1356 if (pred * podf == 0) {
1360 if (pred * podf == 0)
1363 /* relative error in per mille */
1364 act_freq = root_freq / div;
1365 err = abs(act_freq - freq) / freq_khz;
1367 if (err < min_err) {
1381 pll_khz = ref / 1000 * best_m;
1382 if (pll_khz > max_pll_khz)
1385 if (pll_khz < min_pll_khz)
1388 err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1392 cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1393 cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1395 if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1396 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1397 (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1398 clrsetbits_le32(&imx_ccm->cbcmr,
1402 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1404 if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1405 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1406 (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1407 clrsetbits_le32(&imx_ccm->cscdr2,
1411 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1416 void mxs_set_lcdclk(u32 khz)
1418 set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1421 static u32 get_lcdif_clk(void)
1423 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1424 u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1425 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1426 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1427 u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1428 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1429 u32 root_freq = get_lcdif_root_clk(cscdr2);
1431 return root_freq / pred / podf;
1435 unsigned int mxc_get_clock(enum mxc_clock clk)
1439 return get_mcu_main_clk();
1441 return get_periph_clk();
1443 return get_ahb_clk();
1445 return get_ipg_clk();
1446 case MXC_IPG_PERCLK:
1448 return get_ipg_per_clk();
1450 return get_uart_clk();
1452 return get_cspi_clk();
1454 return get_axi_clk();
1455 case MXC_EMI_SLOW_CLK:
1456 return get_emi_slow_clk();
1458 return get_mmdc_ch0_clk();
1460 return get_usdhc_clk(0);
1461 case MXC_ESDHC2_CLK:
1462 return get_usdhc_clk(1);
1463 case MXC_ESDHC3_CLK:
1464 return get_usdhc_clk(2);
1465 case MXC_ESDHC4_CLK:
1466 return get_usdhc_clk(3);
1468 return get_ahb_clk();
1470 return get_nfc_clk();
1471 #ifdef CONFIG_VIDEO_MXS
1473 return get_lcdif_clk();
1476 printf("Unsupported MXC CLK: %d\n", clk);
1482 /* Config CPU clock */
1483 static int set_arm_clk(u32 ref, u32 freq_khz)
1491 const int min_div = 54;
1492 const int max_div = 108;
1493 const int div_mask = 0x7f;
1494 const u32 max_freq = ref * max_div / 2;
1495 const u32 min_freq = ref * min_div / 8 / 2;
1497 if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1498 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1499 freq_khz / 1000, freq_khz % 1000,
1500 min_freq / 1000000, min_freq / 1000 % 1000,
1501 max_freq / 1000000, max_freq / 1000 % 1000);
1505 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1506 int m = freq_khz * 2 * d / (ref / 1000);
1511 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1516 f = ref * m / d / 2;
1517 if (f > freq_khz * 1000) {
1518 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1522 f = ref * m / d / 2;
1524 err = freq_khz * 1000 - f;
1525 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1526 d, m, f, freq_khz, err);
1527 if (err < min_err) {
1537 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1538 mul, div, freq_khz / 1000, freq_khz % 1000,
1539 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1541 reg = readl(&anatop->pll_arm);
1542 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1544 reg = (reg & ~div_mask) | mul;
1545 writel(reg, &anatop->pll_arm);
1547 writel(div - 1, &imx_ccm->cacrr);
1549 ret = wait_pll_lock(&anatop->pll_video);
1551 printf("ARM PLL failed to lock\n");
1555 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1561 * This function assumes the expected core clock has to be changed by
1562 * modifying the PLL. This is NOT true always but for most of the times,
1563 * it is. So it assumes the PLL output freq is the same as the expected
1564 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1565 * In the latter case, it will try to increase the presc value until
1566 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1567 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1568 * on the targeted PLL and reference input clock to the PLL. Lastly,
1569 * it sets the register based on these values along with the dividers.
1570 * Note 1) There is no value checking for the passed-in divider values
1571 * so the caller has to make sure those values are sensible.
1572 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1573 * exceed NFC_CLK_MAX.
1575 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1583 ret = set_arm_clk(ref, freq);
1587 ret = set_nfc_clk(ref, freq);
1591 printf("Warning: Unsupported or invalid clock type: %d\n",
1600 * Dump some core clocks.
1602 #define print_pll(pll) { \
1603 u32 __pll = decode_pll(pll, MXC_HCLK); \
1604 printf("%-12s %4d.%03d MHz\n", #pll, \
1605 __pll / 1000000, __pll / 1000 % 1000); \
1608 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1610 #define print_clk(clk) { \
1611 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1612 printf("%-12s %4d.%03d MHz\n", #clk, \
1613 __clk / 1000000, __clk / 1000 % 1000); \
1616 #define print_pfd(pll, pfd) { \
1617 u32 __pfd = readl(&anatop->pfd_##pll); \
1618 if (__pfd & (0x80 << 8 * pfd)) { \
1619 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1621 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1622 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1624 pll * 18 * 1000 / __pfd % 1000); \
1628 static void do_mx6_showclocks(void)
1632 print_pll(PLL_USBOTG);
1633 print_pll(PLL_AUDIO);
1634 print_pll(PLL_VIDEO);
1635 print_pll(PLL_ENET);
1636 print_pll(PLL_USB2);
1658 print_clk(EMI_SLOW);
1662 #ifdef CONFIG_VIDEO_MXS
1667 static struct clk_lookup {
1670 } mx6_clk_lookup[] = {
1671 { "arm", MXC_ARM_CLK, },
1672 { "nfc", MXC_NFC_CLK, },
1675 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1679 unsigned long ref = ~0UL;
1682 do_mx6_showclocks();
1683 return CMD_RET_SUCCESS;
1684 } else if (argc == 2 || argc > 4) {
1685 return CMD_RET_USAGE;
1688 freq = simple_strtoul(argv[2], NULL, 0);
1690 printf("Invalid clock frequency %lu\n", freq);
1691 return CMD_RET_FAILURE;
1694 ref = simple_strtoul(argv[3], NULL, 0);
1696 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1697 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1698 switch (mx6_clk_lookup[i].index) {
1701 return CMD_RET_USAGE;
1706 if (argc > 3 && ref > 3) {
1707 printf("Invalid clock selector value: %lu\n", ref);
1708 return CMD_RET_FAILURE;
1712 printf("Setting %s clock to %lu MHz\n",
1713 mx6_clk_lookup[i].name, freq);
1714 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1716 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1717 printf("%s clock set to %lu.%03lu MHz\n",
1718 mx6_clk_lookup[i].name,
1719 freq / 1000000, freq / 1000 % 1000);
1720 return CMD_RET_SUCCESS;
1723 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1724 printf("clock %s not found; supported clocks are:\n", argv[1]);
1725 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1726 printf("\t%s\n", mx6_clk_lookup[i].name);
1729 printf("Failed to set clock %s to %s MHz\n",
1732 return CMD_RET_FAILURE;
1735 #ifndef CONFIG_SOC_MX6SX
1736 void enable_ipu_clock(void)
1738 int reg = readl(&imx_ccm->CCGR3);
1739 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1740 writel(reg, &imx_ccm->CCGR3);
1743 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1744 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1748 /***************************************************/
1751 clocks, 4, 0, do_clocks,
1752 "display/set clocks",
1753 " - display clock settings\n"
1754 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"