2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #define PLL_LOCK_BIT (1 << 31)
121 static inline int wait_pll_lock(u32 *reg)
126 while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
132 if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
137 #ifdef CONFIG_MXC_OCOTP
138 void enable_ocotp_clk(unsigned char enable)
142 reg = __raw_readl(&imx_ccm->CCGR2);
144 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
146 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
147 __raw_writel(reg, &imx_ccm->CCGR2);
151 #ifdef CONFIG_NAND_MXS
152 void setup_gpmi_io_clk(u32 cfg)
154 /* Disable clocks per ERR007177 from MX6 errata */
155 clrbits_le32(&imx_ccm->CCGR4,
156 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
158 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
159 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
160 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
164 clrsetbits_le32(&imx_ccm->cs2cdr,
165 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
166 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
167 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
170 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
171 setbits_le32(&imx_ccm->CCGR4,
172 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
173 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
174 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
175 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
176 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
180 void enable_usboh3_clk(unsigned char enable)
184 reg = __raw_readl(&imx_ccm->CCGR6);
186 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
188 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
189 __raw_writel(reg, &imx_ccm->CCGR6);
193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
194 void enable_enet_clk(unsigned char enable)
198 if (is_cpu_type(MXC_CPU_MX6UL)) {
199 mask = MXC_CCM_CCGR3_ENET_MASK;
200 addr = &imx_ccm->CCGR3;
202 mask = MXC_CCM_CCGR1_ENET_MASK;
203 addr = &imx_ccm->CCGR1;
207 setbits_le32(addr, mask);
209 clrbits_le32(addr, mask);
213 #ifdef CONFIG_MXC_UART
214 void enable_uart_clk(unsigned char enable)
218 if (is_cpu_type(MXC_CPU_MX6UL))
219 mask = MXC_CCM_CCGR5_UART_MASK;
221 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
224 setbits_le32(&imx_ccm->CCGR5, mask);
226 clrbits_le32(&imx_ccm->CCGR5, mask);
231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
238 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
240 setbits_le32(&imx_ccm->CCGR6, mask);
242 clrbits_le32(&imx_ccm->CCGR6, mask);
248 #ifdef CONFIG_SYS_I2C_MXC
249 /* i2c_num can be from 0 - 3 */
250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
259 mask = MXC_CCM_CCGR_CG_MASK
260 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
262 reg = __raw_readl(&imx_ccm->CCGR2);
267 __raw_writel(reg, &imx_ccm->CCGR2);
269 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
270 mask = MXC_CCM_CCGR6_I2C4_MASK;
271 addr = &imx_ccm->CCGR6;
273 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
274 addr = &imx_ccm->CCGR1;
276 reg = __raw_readl(addr);
281 __raw_writel(reg, addr);
287 /* spi_num can be from 0 - SPI_MAX_NUM */
288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
293 if (spi_num > SPI_MAX_NUM)
296 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
297 reg = __raw_readl(&imx_ccm->CCGR1);
302 __raw_writel(reg, &imx_ccm->CCGR1);
306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
309 u32 pll_num, pll_denom;
314 div = __raw_readl(&anatop->pll_arm);
315 if (div & BM_ANADIG_PLL_ARM_BYPASS)
316 /* Assume the bypass clock is always derived from OSC */
318 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
320 return infreq * div / 2;
322 div = __raw_readl(&anatop->pll_528);
323 if (div & BM_ANADIG_PLL_528_BYPASS)
325 div &= BM_ANADIG_PLL_528_DIV_SELECT;
327 return infreq * (20 + div * 2);
329 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
330 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
332 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
334 return infreq * (20 + div * 2);
336 div = __raw_readl(&anatop->pll_audio);
337 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
338 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
341 pll_num = __raw_readl(&anatop->pll_audio_num);
342 pll_denom = __raw_readl(&anatop->pll_audio_denom);
344 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
345 BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
347 printf("Invalid post divider value for PLL_AUDIO\n");
350 post_div = 1 << (2 - post_div);
351 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
353 freq = (u64)infreq * pll_num / pll_denom;
354 freq += infreq * div;
355 return lldiv(freq, post_div);
357 div = __raw_readl(&anatop->pll_video);
358 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
359 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
362 pll_num = __raw_readl(&anatop->pll_video_num);
363 pll_denom = __raw_readl(&anatop->pll_video_denom);
365 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
366 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
368 printf("Invalid post divider value for PLL_VIDEO\n");
371 post_div = 1 << (2 - post_div);
372 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
374 freq = (u64)infreq * pll_num / pll_denom;
375 freq += infreq * div;
376 return lldiv(freq, post_div);
378 div = __raw_readl(&anatop->pll_enet);
379 if (div & BM_ANADIG_PLL_ENET_BYPASS)
381 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
383 return 25000000 * (div + (div >> 1) + 1);
385 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
386 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
388 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
390 return infreq * (20 + div * 2);
392 div = __raw_readl(&anatop->pll_mlb);
393 if (div & BM_ANADIG_PLL_MLB_BYPASS)
395 /* fallthru: unknown external clock provided on MLB_CLK pin */
402 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
409 if (!is_cpu_type(MXC_CPU_MX6UL)) {
411 /* No PFD3 on PPL2 */
415 div = __raw_readl(&anatop->pfd_528);
416 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
419 div = __raw_readl(&anatop->pfd_480);
420 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
423 /* No PFD on other PLL */
427 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
428 ANATOP_PFD_FRAC_SHIFT(pfd_num));
431 static u32 get_mcu_main_clk(void)
435 reg = __raw_readl(&imx_ccm->cacrr);
436 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
437 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
438 freq = decode_pll(PLL_ARM, MXC_HCLK);
440 return freq / (reg + 1);
443 u32 get_periph_clk(void)
445 u32 reg, div = 0, freq = 0;
447 reg = __raw_readl(&imx_ccm->cbcdr);
448 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
449 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
450 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
451 reg = __raw_readl(&imx_ccm->cbcmr);
452 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
453 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
457 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
465 reg = __raw_readl(&imx_ccm->cbcmr);
466 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
467 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
471 freq = decode_pll(PLL_528, MXC_HCLK);
474 freq = mxc_get_pll_pfd(PLL_528, 2);
477 freq = mxc_get_pll_pfd(PLL_528, 0);
480 /* static / 2 divider */
481 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
486 return freq / (div + 1);
489 static u32 get_ipg_clk(void)
493 reg = __raw_readl(&imx_ccm->cbcdr);
494 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
495 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
497 return get_ahb_clk() / (ipg_podf + 1);
500 static u32 get_ipg_per_clk(void)
502 u32 reg, perclk_podf;
504 reg = __raw_readl(&imx_ccm->cscmr1);
505 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
506 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
507 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
508 return MXC_HCLK; /* OSC 24Mhz */
511 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
513 return get_ipg_clk() / (perclk_podf + 1);
516 static u32 get_uart_clk(void)
519 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
520 reg = __raw_readl(&imx_ccm->cscdr1);
522 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
523 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
524 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
528 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
529 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
531 return freq / (uart_podf + 1);
534 static u32 get_cspi_clk(void)
538 reg = __raw_readl(&imx_ccm->cscdr2);
539 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
540 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
542 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
543 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
544 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
545 return MXC_HCLK / (cspi_podf + 1);
548 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
551 static u32 get_axi_clk(void)
553 u32 root_freq, axi_podf;
554 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
556 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
557 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
559 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
560 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
561 root_freq = mxc_get_pll_pfd(PLL_528, 2);
563 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
565 root_freq = get_periph_clk();
567 return root_freq / (axi_podf + 1);
570 static u32 get_emi_slow_clk(void)
572 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
574 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
575 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
576 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
577 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
578 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
580 switch (emi_clk_sel) {
582 root_freq = get_axi_clk();
585 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
588 root_freq = mxc_get_pll_pfd(PLL_528, 2);
591 root_freq = mxc_get_pll_pfd(PLL_528, 0);
595 return root_freq / (emi_slow_podf + 1);
598 static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
600 switch (nfc_clk_sel) {
602 return mxc_get_pll_pfd(PLL_528, 0);
605 return decode_pll(PLL_528, MXC_HCLK);
608 return decode_pll(PLL_USBOTG, MXC_HCLK);
611 return mxc_get_pll_pfd(PLL_528, 2);
614 return mxc_get_pll_pfd(PLL_USBOTG, 3);
620 static u32 get_nfc_clk(void)
622 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
623 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
624 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
625 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
626 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
627 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
628 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
629 u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
631 return root_freq / (pred + 1) / (podf + 1);
634 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
635 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
636 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
638 static int set_nfc_clk(u32 ref, u32 freq_khz)
640 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
647 u32 freq = freq_khz * 1000;
648 int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
650 for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
654 if (ref < num_sel && ref != nfc_clk_sel)
657 switch (nfc_clk_sel) {
659 root_freq = mxc_get_pll_pfd(PLL_528, 0);
662 root_freq = decode_pll(PLL_528, MXC_HCLK);
665 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
668 root_freq = mxc_get_pll_pfd(PLL_528, 2);
671 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
674 if (root_freq < freq)
677 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
678 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
679 act_freq = root_freq / pred / podf;
680 err = (freq - act_freq) * 100 / freq;
681 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
682 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
686 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
687 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
688 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
695 if (nfc_val == ~0 || min_err > 10)
698 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
699 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
700 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
701 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
704 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
709 static u32 get_mmdc_ch0_clk(void)
711 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
712 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
714 u32 freq, podf, per2_clk2_podf;
716 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
717 is_cpu_type(MXC_CPU_MX6SL)) {
718 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
719 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
720 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
721 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
722 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
723 if (is_cpu_type(MXC_CPU_MX6SL)) {
724 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
727 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
729 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
730 freq = decode_pll(PLL_528, MXC_HCLK);
732 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
737 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
738 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
740 freq = decode_pll(PLL_528, MXC_HCLK);
743 freq = mxc_get_pll_pfd(PLL_528, 2);
746 freq = mxc_get_pll_pfd(PLL_528, 0);
749 /* static / 2 divider */
750 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
754 return freq / (podf + 1) / (per2_clk2_podf + 1);
756 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
757 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
758 return get_periph_clk() / (podf + 1);
762 #ifdef CONFIG_FSL_QSPI
763 /* qspi_num can be from 0 - 1 */
764 void enable_qspi_clk(int qspi_num)
767 /* Enable QuadSPI clock */
770 /* disable the clock gate */
771 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
773 /* set 50M : (50 = 396 / 2 / 4) */
774 reg = readl(&imx_ccm->cscmr1);
775 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
776 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
777 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
778 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
779 writel(reg, &imx_ccm->cscmr1);
781 /* enable the clock gate */
782 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
786 * disable the clock gate
787 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
788 * disable both of them.
790 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
791 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
793 /* set 50M : (50 = 396 / 2 / 4) */
794 reg = readl(&imx_ccm->cs2cdr);
795 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
796 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
797 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
798 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
799 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
800 writel(reg, &imx_ccm->cs2cdr);
802 /*enable the clock gate*/
803 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
804 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
812 #ifdef CONFIG_FEC_MXC
813 int enable_fec_anatop_clock(enum enet_freq freq)
816 s32 timeout = 100000;
818 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
821 reg = readl(&anatop->pll_enet);
822 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
825 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
826 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
827 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
828 writel(reg, &anatop->pll_enet);
830 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
837 /* Enable FEC clock */
838 reg |= BM_ANADIG_PLL_ENET_ENABLE;
839 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
840 writel(reg, &anatop->pll_enet);
842 #ifdef CONFIG_SOC_MX6SX
844 * Set enet ahb clock to 200MHz
845 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
847 reg = readl(&imx_ccm->chsccdr);
848 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
849 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
850 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
852 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
854 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
855 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
856 writel(reg, &imx_ccm->chsccdr);
858 /* Enable enet system clock */
859 reg = readl(&imx_ccm->CCGR3);
860 reg |= MXC_CCM_CCGR3_ENET_MASK;
861 writel(reg, &imx_ccm->CCGR3);
867 static u32 get_usdhc_clk(u32 port)
869 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
870 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
871 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
875 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
876 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
877 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
881 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
882 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
883 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
887 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
888 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
889 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
893 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
894 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
895 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
903 root_freq = mxc_get_pll_pfd(PLL_528, 0);
905 root_freq = mxc_get_pll_pfd(PLL_528, 2);
907 return root_freq / (usdhc_podf + 1);
910 u32 imx_get_uartclk(void)
912 return get_uart_clk();
915 u32 imx_get_fecclk(void)
917 return mxc_get_clock(MXC_IPG_CLK);
920 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
921 static int enable_enet_pll(uint32_t en)
924 s32 timeout = 100000;
927 reg = readl(&anatop->pll_enet);
928 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
929 writel(reg, &anatop->pll_enet);
930 reg |= BM_ANADIG_PLL_ENET_ENABLE;
932 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
937 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
938 writel(reg, &anatop->pll_enet);
940 writel(reg, &anatop->pll_enet);
945 #ifdef CONFIG_CMD_SATA
946 static void ungate_sata_clock(void)
948 /* Enable SATA clock. */
949 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
952 int enable_sata_clock(void)
955 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
958 void disable_sata_clock(void)
960 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
964 #ifdef CONFIG_PCIE_IMX
965 static void ungate_pcie_clock(void)
967 /* Enable PCIe clock. */
968 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
971 int enable_pcie_clock(void)
978 * The register ANATOP_MISC1 is not documented in the Freescale
979 * MX6RM. The register that is mapped in the ANATOP space and
980 * marked as ANATOP_MISC1 is actually documented in the PMU section
981 * of the datasheet as PMU_MISC1.
983 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
984 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
985 * for PCI express link that is clocked from the i.MX6.
987 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
988 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
989 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
990 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
991 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
993 if (is_cpu_type(MXC_CPU_MX6SX))
994 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
996 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
998 clrsetbits_le32(&anatop_regs->ana_misc1,
999 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1000 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1001 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1003 /* PCIe reference clock sourced from AXI. */
1004 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1006 /* Party time! Ungate the clock to the PCIe. */
1007 #ifdef CONFIG_CMD_SATA
1008 ungate_sata_clock();
1010 ungate_pcie_clock();
1012 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1013 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1017 #ifdef CONFIG_SECURE_BOOT
1018 void hab_caam_clock_enable(unsigned char enable)
1022 /* CG4 ~ CG6, CAAM clocks */
1023 reg = __raw_readl(&imx_ccm->CCGR0);
1025 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1026 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1027 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1029 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1030 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1031 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1032 __raw_writel(reg, &imx_ccm->CCGR0);
1035 reg = __raw_readl(&imx_ccm->CCGR6);
1037 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1039 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1040 __raw_writel(reg, &imx_ccm->CCGR6);
1044 static void enable_pll3(void)
1046 /* make sure pll3 is enabled */
1047 if ((readl(&anatop->usb1_pll_480_ctrl) &
1048 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1049 /* enable pll's power */
1050 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1051 &anatop->usb1_pll_480_ctrl_set);
1052 writel(0x80, &anatop->ana_misc2_clr);
1053 /* wait for pll lock */
1054 while ((readl(&anatop->usb1_pll_480_ctrl) &
1055 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1057 /* disable bypass */
1058 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1059 &anatop->usb1_pll_480_ctrl_clr);
1060 /* enable pll output */
1061 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1062 &anatop->usb1_pll_480_ctrl_set);
1066 void enable_thermal_clk(void)
1071 void ipu_clk_enable(void)
1073 u32 reg = readl(&imx_ccm->CCGR3);
1074 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1075 writel(reg, &imx_ccm->CCGR3);
1078 void ipu_clk_disable(void)
1080 u32 reg = readl(&imx_ccm->CCGR3);
1081 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1082 writel(reg, &imx_ccm->CCGR3);
1085 void ipu_di_clk_enable(int di)
1089 setbits_le32(&imx_ccm->CCGR3,
1090 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1093 setbits_le32(&imx_ccm->CCGR3,
1094 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1097 printf("%s: Invalid DI index %d\n", __func__, di);
1101 void ipu_di_clk_disable(int di)
1105 clrbits_le32(&imx_ccm->CCGR3,
1106 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1109 clrbits_le32(&imx_ccm->CCGR3,
1110 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1113 printf("%s: Invalid DI index %d\n", __func__, di);
1117 void ldb_clk_enable(int ldb)
1121 setbits_le32(&imx_ccm->CCGR3,
1122 MXC_CCM_CCGR3_LDB_DI0_MASK);
1125 setbits_le32(&imx_ccm->CCGR3,
1126 MXC_CCM_CCGR3_LDB_DI1_MASK);
1129 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1133 void ldb_clk_disable(int ldb)
1137 clrbits_le32(&imx_ccm->CCGR3,
1138 MXC_CCM_CCGR3_LDB_DI0_MASK);
1141 clrbits_le32(&imx_ccm->CCGR3,
1142 MXC_CCM_CCGR3_LDB_DI1_MASK);
1145 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1149 #ifdef CONFIG_VIDEO_MXS
1150 void lcdif_clk_enable(void)
1152 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1153 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1156 void lcdif_clk_disable(void)
1158 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1159 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1162 #define CBCMR_LCDIF_MASK MXC_CCM_CBCMR_LCDIF_PODF_MASK
1163 #define CSCDR2_LCDIF_MASK (MXC_CCM_CSCDR2_LCDIF_PRED_MASK | \
1164 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1166 static u32 get_lcdif_root_clk(u32 cscdr2)
1168 int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1169 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1170 int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1171 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1174 switch (lcdif_clk_sel) {
1176 switch (lcdif_pre_clk_sel) {
1178 root_freq = decode_pll(PLL_528, MXC_HCLK);
1181 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1184 root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1187 root_freq = mxc_get_pll_pfd(PLL_528, 0);
1190 root_freq = mxc_get_pll_pfd(PLL_528, 1);
1193 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1200 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1203 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1206 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1215 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1219 u64 freq = freq_khz * 1000;
1220 u32 post_div_mask = 1 << (2 - post_div);
1226 const int min_div = 27;
1227 const int max_div = 54;
1228 const int div_mask = 0x7f;
1229 const u32 max_freq = ref * max_div / post_div;
1230 const u32 min_freq = ref * min_div / post_div;
1232 if (freq > max_freq || freq < min_freq) {
1233 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1234 freq_khz / 1000, freq_khz % 1000,
1235 min_freq / 1000000, min_freq / 1000 % 1000,
1236 max_freq / 1000000, max_freq / 1000 % 1000);
1241 int m = lldiv(freq * d + ref - 1, ref);
1245 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1246 d, m, max_div, min_div);
1247 if (m > max_div || m < min_div)
1252 debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1257 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1258 d, m, f, freq, err);
1259 if (err < min_err) {
1264 if (min_err == ~0) {
1265 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1266 freq_khz / 1000, freq_khz % 1000);
1270 debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1271 mul, post_div, num, denom,
1272 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1273 ref * mul / post_div / 1000000,
1274 ref * mul / post_div / 1000 % 1000);
1276 reg = readl(&anatop->pll_video);
1277 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1279 reg = (reg & ~(div_mask |
1280 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1281 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1282 writel(reg, &anatop->pll_video);
1284 ret = wait_pll_lock(&anatop->pll_video);
1286 printf("Video PLL failed to lock\n");
1290 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1294 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1296 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1297 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1300 u32 freq = freq_khz * 1000;
1305 u32 min_pll_khz = ref * min_div / 4 / 1000;
1306 u32 max_pll_khz = ref * max_div / 1000;
1317 if (freq_khz > max_pll_khz)
1320 for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1321 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1322 m <= max_div; m++) {
1326 u32 root_freq = ref * m / pd;
1328 div = DIV_ROUND_UP(root_freq, freq);
1330 while (pred * podf == 0 && div <= 64) {
1333 for (p1 = 1; p1 <= 8; p1++) {
1334 for (p2 = 1; p2 <= 8; p2++) {
1335 if (p1 * p2 == div) {
1342 if (pred * podf == 0) {
1346 if (pred * podf == 0)
1349 /* relative error in per mille */
1350 act_freq = root_freq / div;
1351 err = abs(act_freq - freq) / freq_khz;
1353 if (err < min_err) {
1367 pll_khz = ref / 1000 * best_m;
1368 if (pll_khz > max_pll_khz)
1371 if (pll_khz < min_pll_khz)
1374 err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1378 cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1379 cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1381 if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1382 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1383 (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1384 clrsetbits_le32(&imx_ccm->cbcmr,
1388 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1390 if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1391 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1392 (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1393 clrsetbits_le32(&imx_ccm->cscdr2,
1397 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1402 void mxs_set_lcdclk(u32 khz)
1404 set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1407 static u32 get_lcdif_clk(void)
1409 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1410 u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1411 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1412 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1413 u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1414 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1415 u32 root_freq = get_lcdif_root_clk(cscdr2);
1417 return root_freq / pred / podf;
1421 unsigned int mxc_get_clock(enum mxc_clock clk)
1425 return get_mcu_main_clk();
1427 return get_periph_clk();
1429 return get_ahb_clk();
1431 return get_ipg_clk();
1432 case MXC_IPG_PERCLK:
1434 return get_ipg_per_clk();
1436 return get_uart_clk();
1438 return get_cspi_clk();
1440 return get_axi_clk();
1441 case MXC_EMI_SLOW_CLK:
1442 return get_emi_slow_clk();
1444 return get_mmdc_ch0_clk();
1446 return get_usdhc_clk(0);
1447 case MXC_ESDHC2_CLK:
1448 return get_usdhc_clk(1);
1449 case MXC_ESDHC3_CLK:
1450 return get_usdhc_clk(2);
1451 case MXC_ESDHC4_CLK:
1452 return get_usdhc_clk(3);
1454 return get_ahb_clk();
1456 return get_nfc_clk();
1457 #ifdef CONFIG_VIDEO_MXS
1459 return get_lcdif_clk();
1462 printf("Unsupported MXC CLK: %d\n", clk);
1468 /* Config CPU clock */
1469 static int set_arm_clk(u32 ref, u32 freq_khz)
1477 const int min_div = 54;
1478 const int max_div = 108;
1479 const int div_mask = 0x7f;
1480 const u32 max_freq = ref * max_div / 2;
1481 const u32 min_freq = ref * min_div / 8 / 2;
1483 if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1484 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1485 freq_khz / 1000, freq_khz % 1000,
1486 min_freq / 1000000, min_freq / 1000 % 1000,
1487 max_freq / 1000000, max_freq / 1000 % 1000);
1491 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1492 int m = freq_khz * 2 * d / (ref / 1000);
1497 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1502 f = ref * m / d / 2;
1503 if (f > freq_khz * 1000) {
1504 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1508 f = ref * m / d / 2;
1510 err = freq_khz * 1000 - f;
1511 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1512 d, m, f, freq_khz, err);
1513 if (err < min_err) {
1523 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1524 mul, div, freq_khz / 1000, freq_khz % 1000,
1525 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1527 reg = readl(&anatop->pll_arm);
1528 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1530 reg = (reg & ~div_mask) | mul;
1531 writel(reg, &anatop->pll_arm);
1533 writel(div - 1, &imx_ccm->cacrr);
1535 ret = wait_pll_lock(&anatop->pll_video);
1537 printf("ARM PLL failed to lock\n");
1541 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1547 * This function assumes the expected core clock has to be changed by
1548 * modifying the PLL. This is NOT true always but for most of the times,
1549 * it is. So it assumes the PLL output freq is the same as the expected
1550 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1551 * In the latter case, it will try to increase the presc value until
1552 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1553 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1554 * on the targeted PLL and reference input clock to the PLL. Lastly,
1555 * it sets the register based on these values along with the dividers.
1556 * Note 1) There is no value checking for the passed-in divider values
1557 * so the caller has to make sure those values are sensible.
1558 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1559 * exceed NFC_CLK_MAX.
1561 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1569 ret = set_arm_clk(ref, freq);
1573 ret = set_nfc_clk(ref, freq);
1577 printf("Warning: Unsupported or invalid clock type: %d\n",
1586 * Dump some core clocks.
1588 #define print_pll(pll) { \
1589 u32 __pll = decode_pll(pll, MXC_HCLK); \
1590 printf("%-12s %4d.%03d MHz\n", #pll, \
1591 __pll / 1000000, __pll / 1000 % 1000); \
1594 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1596 #define print_clk(clk) { \
1597 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1598 printf("%-12s %4d.%03d MHz\n", #clk, \
1599 __clk / 1000000, __clk / 1000 % 1000); \
1602 #define print_pfd(pll, pfd) { \
1603 u32 __pfd = readl(&anatop->pfd_##pll); \
1604 if (__pfd & (0x80 << 8 * pfd)) { \
1605 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1607 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1608 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1610 pll * 18 * 1000 / __pfd % 1000); \
1614 static void do_mx6_showclocks(void)
1618 print_pll(PLL_USBOTG);
1619 print_pll(PLL_AUDIO);
1620 print_pll(PLL_VIDEO);
1621 print_pll(PLL_ENET);
1622 print_pll(PLL_USB2);
1644 print_clk(EMI_SLOW);
1648 #ifdef CONFIG_VIDEO_MXS
1653 static struct clk_lookup {
1656 } mx6_clk_lookup[] = {
1657 { "arm", MXC_ARM_CLK, },
1658 { "nfc", MXC_NFC_CLK, },
1661 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1665 unsigned long ref = ~0UL;
1668 do_mx6_showclocks();
1669 return CMD_RET_SUCCESS;
1670 } else if (argc == 2 || argc > 4) {
1671 return CMD_RET_USAGE;
1674 freq = simple_strtoul(argv[2], NULL, 0);
1676 printf("Invalid clock frequency %lu\n", freq);
1677 return CMD_RET_FAILURE;
1680 ref = simple_strtoul(argv[3], NULL, 0);
1682 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1683 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1684 switch (mx6_clk_lookup[i].index) {
1687 return CMD_RET_USAGE;
1692 if (argc > 3 && ref > 3) {
1693 printf("Invalid clock selector value: %lu\n", ref);
1694 return CMD_RET_FAILURE;
1698 printf("Setting %s clock to %lu MHz\n",
1699 mx6_clk_lookup[i].name, freq);
1700 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1702 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1703 printf("%s clock set to %lu.%03lu MHz\n",
1704 mx6_clk_lookup[i].name,
1705 freq / 1000000, freq / 1000 % 1000);
1706 return CMD_RET_SUCCESS;
1709 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1710 printf("clock %s not found; supported clocks are:\n", argv[1]);
1711 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1712 printf("\t%s\n", mx6_clk_lookup[i].name);
1715 printf("Failed to set clock %s to %s MHz\n",
1718 return CMD_RET_FAILURE;
1721 #ifndef CONFIG_SOC_MX6SX
1722 void enable_ipu_clock(void)
1724 int reg = readl(&imx_ccm->CCGR3);
1725 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1726 writel(reg, &imx_ccm->CCGR3);
1729 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1730 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1734 /***************************************************/
1737 clocks, 4, 0, do_clocks,
1738 "display/set clocks",
1739 " - display clock settings\n"
1740 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"