2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 Clock control functions */
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tegra2.h>
32 * Get the oscillator frequency, from the corresponding hardware configuration
35 enum clock_osc_freq clock_get_osc_freq(void)
37 struct clk_rst_ctlr *clkrst =
38 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
41 reg = readl(&clkrst->crc_osc_ctrl);
42 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
45 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
46 u32 divp, u32 cpcon, u32 lfcon)
48 struct clk_rst_ctlr *clkrst =
49 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
53 assert(clock_id_isvalid(clkid));
54 pll = &clkrst->crc_pll[clkid];
57 * We cheat by treating all PLL (except PLLU) in the same fashion.
58 * This works only because:
59 * - same fields are always mapped at same offsets, except DCCON
60 * - DCCON is always 0, doesn't conflict
61 * - M,N, P of PLLP values are ignored for PLLP
63 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
64 writel(data, &pll->pll_misc);
66 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
67 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
69 if (clkid == CLOCK_ID_USB)
70 data |= divp << PLLU_VCO_FREQ_SHIFT;
72 data |= divp << PLL_DIVP_SHIFT;
73 writel(data, &pll->pll_base);
75 /* calculate the stable time */
76 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
79 void clock_set_enable(enum periph_id periph_id, int enable)
81 struct clk_rst_ctlr *clkrst =
82 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
83 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
86 /* Enable/disable the clock to this peripheral */
87 assert(clock_periph_id_isvalid(periph_id));
90 reg |= PERIPH_MASK(periph_id);
92 reg &= ~PERIPH_MASK(periph_id);
96 void clock_enable(enum periph_id clkid)
98 clock_set_enable(clkid, 1);
101 void clock_disable(enum periph_id clkid)
103 clock_set_enable(clkid, 0);
106 void reset_set_enable(enum periph_id periph_id, int enable)
108 struct clk_rst_ctlr *clkrst =
109 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
110 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
113 /* Enable/disable reset to the peripheral */
114 assert(clock_periph_id_isvalid(periph_id));
117 reg |= PERIPH_MASK(periph_id);
119 reg &= ~PERIPH_MASK(periph_id);
123 void reset_periph(enum periph_id periph_id, int us_delay)
125 /* Put peripheral into reset */
126 reset_set_enable(periph_id, 1);
130 reset_set_enable(periph_id, 0);
135 void reset_cmplx_set_enable(int cpu, int which, int reset)
137 struct clk_rst_ctlr *clkrst =
138 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
141 /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
142 assert(cpu >= 0 && cpu < 2);
145 /* either enable or disable those reset for that CPU */
147 writel(mask, &clkrst->crc_cpu_cmplx_set);
149 writel(mask, &clkrst->crc_cpu_cmplx_clr);