2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/clk.h>
14 #define SLCR_LOCK_MAGIC 0x767B
15 #define SLCR_UNLOCK_MAGIC 0xDF0D
17 #define SLCR_IDCODE_MASK 0x1F000
18 #define SLCR_IDCODE_SHIFT 12
21 * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
23 * @peri_name: Name of the peripheral for checking MIO status
24 * @get_pins: Pointer to array of get pin for this peripheral
25 * @num_pins: Number of pins for this peripheral
27 * @check_val: Required check value to get the status of periph
29 struct zynq_slcr_mio_get_status {
30 const char *peri_name;
37 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
40 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
42 void zynq_slcr_lock(void)
45 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
50 void zynq_slcr_unlock(void)
53 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
58 /* Reset the entire system */
59 void zynq_slcr_cpu_reset(void)
62 * Unlock the SLCR then reset the system.
63 * Note that this seems to require raw i/o
64 * functions or there's a lockup?
69 * Clear 0x0F000000 bits of reboot status register to workaround
70 * the FSBL not loading the bitstream after soft-reboot
71 * This is a temporary solution until we know more.
73 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
75 writel(1, &slcr_base->pss_rst_ctrl);
78 /* Setup clk for network */
79 void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
86 printf("Non existing GEM id %d\n", gem_id);
90 ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
95 /* Configure GEM_RCLK_CTRL */
96 writel(1, &slcr_base->gem1_rclk_ctrl);
98 /* Configure GEM_RCLK_CTRL */
99 writel(1, &slcr_base->gem0_rclk_ctrl);
106 void zynq_slcr_devcfg_disable(void)
110 /* Disable AXI interface by asserting FPGA resets */
111 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
113 /* Set Level Shifters DT618760 */
114 writel(0xA, &slcr_base->lvl_shftr_en);
119 void zynq_slcr_devcfg_enable(void)
123 /* Set Level Shifters DT618760 */
124 writel(0xF, &slcr_base->lvl_shftr_en);
126 /* Enable AXI interface by de-asserting FPGA resets */
127 writel(0x0, &slcr_base->fpga_rst_ctrl);
132 u32 zynq_slcr_get_boot_mode(void)
134 /* Get the bootmode register value */
135 return readl(&slcr_base->boot_mode);
138 u32 zynq_slcr_get_idcode(void)
140 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
145 * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
147 * @periph: Name of the peripheral
149 * Returns count to indicate the number of pins configured for the
152 int zynq_slcr_get_mio_pin_status(const char *periph)
154 const struct zynq_slcr_mio_get_status *mio_ptr;
158 for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
159 if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
160 mio_ptr = &mio_periphs[i];
161 for (j = 0; j < mio_ptr->num_pins; j++) {
162 val = readl(&slcr_base->mio_pin
163 [mio_ptr->get_pins[j]]);
164 if ((val & mio_ptr->mask) == mio_ptr->check_val)